/gfx-drm/usr/src/uts/intel/io/i915/ |
H A D | i915_drv.c | 1188 ((reg) < 0x40000) && \ 1189 ((reg) != FORCEWAKE)) 1206 reg); in hsw_unclaimed_reg_clear() 1312 if (NEEDS_FORCE_WAKE(dev_priv, reg)) in i915_write8() 1334 if (NEEDS_FORCE_WAKE(dev_priv, reg)) in i915_write16() 1356 if (NEEDS_FORCE_WAKE(dev_priv, reg)) in i915_write32() 1378 if (NEEDS_FORCE_WAKE(dev_priv, reg)) in i915_write64() 1438 reg->val = I915_READ64(reg->offset); in i915_reg_read_ioctl() 1441 reg->val = I915_READ(reg->offset); in i915_reg_read_ioctl() 1444 reg->val = I915_READ16(reg->offset); in i915_reg_read_ioctl() [all …]
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H A D | intel_hdmi.c | 215 POSTING_READ(reg); in ibx_write_infoframe() 258 POSTING_READ(reg); in cpt_write_infoframe() 298 POSTING_READ(reg); in vlv_write_infoframe() 413 POSTING_READ(reg); in g4x_set_infoframes() 443 POSTING_READ(reg); in g4x_set_infoframes() 470 POSTING_READ(reg); in ibx_set_infoframes() 504 POSTING_READ(reg); in ibx_set_infoframes() 529 POSTING_READ(reg); in cpt_set_infoframes() 539 POSTING_READ(reg); in cpt_set_infoframes() 573 POSTING_READ(reg); in vlv_set_infoframes() [all …]
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H A D | intel_sideband.c | 104 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg) in vlv_dpio_read() argument 109 DPIO_OPCODE_REG_READ, reg, &val); in vlv_dpio_read() 114 void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val) in vlv_dpio_write() argument 117 DPIO_OPCODE_REG_WRITE, reg, &val); in vlv_dpio_write() 121 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, in intel_sbi_read() argument 133 I915_WRITE(SBI_ADDR, (reg << 16)); in intel_sbi_read() 150 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, in intel_sbi_write() argument 163 I915_WRITE(SBI_ADDR, (reg << 16)); in intel_sbi_write()
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H A D | intel_display.c | 894 int reg; in assert_pll() local 948 int reg; in assert_fdi_tx() local 974 int reg; in assert_fdi_rx() local 991 int reg; in assert_fdi_tx_pll_enabled() local 1011 int reg; in assert_fdi_rx_pll_enabled() local 1052 int reg; in assert_pipe() local 1079 int reg; in assert_plane() local 1174 int reg; in assert_pch_transcoder_disabled() local 1280 int reg; in assert_pch_ports_disabled() local 1319 int reg; in intel_enable_pll() local [all …]
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H A D | i915_drv.h | 2008 #define I915_READ(reg) i915_read32(dev_priv, (reg)) argument 2010 #define I915_READ_NOTRACE(reg) DRM_READ32(dev_priv->regs, (reg)) argument 2012 #define I915_READ16(reg) i915_read16(dev_priv, (reg)) argument 2013 #define I915_WRITE16(reg,val) i915_write16(dev_priv, (reg), (u16)(val)) argument 2014 #define I915_READ16_NOTRACE(reg) DRM_READ16(dev_priv->regs, (reg)) argument 2016 #define I915_READ8(reg) i915_read8(dev_priv, (reg)) argument 2017 #define I915_WRITE8(reg,val) i915_write8(dev_priv, (reg), (u8)(val)) argument 2019 #define I915_READ64(reg) i915_read64(dev_priv, (reg)) argument 2020 #define POSTING_READ(reg) (void)DRM_READ32(dev_priv->regs, (reg)) argument 2021 #define POSTING_READ16(reg) (void)DRM_READ16(dev_priv->regs, (reg)) argument [all …]
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H A D | intel_lvds.c | 53 u32 reg; member 76 tmp = I915_READ(lvds_encoder->reg); in intel_lvds_get_hw_state() 136 temp = I915_READ(lvds_encoder->reg); in intel_pre_pll_enable_lvds() 184 I915_WRITE(lvds_encoder->reg, temp); in intel_pre_pll_enable_lvds() 206 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); in intel_enable_lvds() 209 POSTING_READ(lvds_encoder->reg); in intel_enable_lvds() 237 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); in intel_disable_lvds() 238 POSTING_READ(lvds_encoder->reg); in intel_disable_lvds() 854 val = I915_READ(lvds_encoder->reg); in compute_is_dual_link_lvds() 971 lvds_encoder->reg = PCH_LVDS; in intel_lvds_init() [all …]
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H A D | i915_gem.c | 1769 if (reg->obj) { in i915_gem_restore_fences() 1770 i915_gem_object_update_fence(reg->obj, reg, in i915_gem_restore_fences() 2247 if (reg < 8) in i915_write_fence_reg() 2248 reg = FENCE_REG_830_0 + reg * 4; in i915_write_fence_reg() 2250 reg = FENCE_REG_945_8 + (reg - 8) * 4; in i915_write_fence_reg() 2400 if (!reg->obj) in i915_find_fence_reg() 2401 return reg; in i915_find_fence_reg() 2404 avail = reg; in i915_find_fence_reg() 2415 return reg; in i915_find_fence_reg() 2463 if (reg == NULL) in i915_gem_object_get_fence() [all …]
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H A D | intel_panel.c | 529 uint32_t reg, tmp; in intel_panel_disable_backlight() local 531 reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2; in intel_panel_disable_backlight() 533 I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE); in intel_panel_disable_backlight() 563 uint32_t reg, tmp; in intel_panel_enable_backlight() local 565 reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2; in intel_panel_enable_backlight() 568 tmp = I915_READ(reg); in intel_panel_enable_backlight() 587 I915_WRITE(reg, tmp); in intel_panel_enable_backlight() 588 POSTING_READ(reg); in intel_panel_enable_backlight() 589 I915_WRITE(reg, tmp | BLM_PWM_ENABLE); in intel_panel_enable_backlight()
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H A D | intel_ddi.c | 94 u32 reg; in intel_prepare_ddi_buffers() local 109 I915_WRITE(reg, ddi_translations[i]); in intel_prepare_ddi_buffers() 110 reg += 4; in intel_prepare_ddi_buffers() 149 uint32_t reg = DDI_BUF_CTL(port); in intel_wait_ddi_buf_idle() local 643 uint32_t reg, val; in intel_ddi_pll_mode_set() local 679 reg = WRPLL_CTL1; in intel_ddi_pll_mode_set() 685 reg = WRPLL_CTL2; in intel_ddi_pll_mode_set() 706 reg = SPLL_CTL; in intel_ddi_pll_mode_set() 724 I915_WRITE(reg, val); in intel_ddi_pll_mode_set() 854 uint32_t val = I915_READ(reg); in intel_ddi_disable_transcoder_func() [all …]
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H A D | intel_ringbuffer.h | 230 int reg) in intel_read_status_page() argument 233 return regs[reg]; in intel_read_status_page() 238 int reg, u32 value) in intel_write_status_page() argument 241 regs[reg] = value; in intel_write_status_page()
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H A D | i915_suspend.c | 37 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg) in i915_read_indexed() argument 41 I915_WRITE8(index_port, reg); in i915_read_indexed() 45 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable) in i915_read_ar() argument 50 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg); in i915_read_ar() 54 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable) in i915_write_ar() argument 59 I915_WRITE8(VGA_AR_INDEX, palette_enable | reg); in i915_write_ar() 63 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 va… in i915_write_indexed() argument 67 I915_WRITE8(index_port, reg); in i915_write_indexed()
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H A D | i915_gem_context.c | 114 u32 reg; in get_context_size() local 118 reg = I915_READ(CXT_SIZE); in get_context_size() 119 ret = GEN6_CXT_TOTAL_SIZE(reg) * 64; in get_context_size() 122 reg = I915_READ(GEN7_CXT_SIZE); in get_context_size() 126 ret = GEN7_CXT_TOTAL_SIZE(reg) * 64; in get_context_size()
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H A D | dvo_ch7017.c | 386 #define DUMP(reg) \ in ch7017_dump_regs() argument 388 (void) ch7017_read(dvo, reg, &val); \ in ch7017_dump_regs() 389 DRM_DEBUG_KMS(#reg ": %02x\n", val); \ in ch7017_dump_regs()
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H A D | i915_gem_debug.c | 56 uint32_t reg; member 65 add_instdone_bit(uint32_t reg, uint32_t bit, const char *name) in add_instdone_bit() argument 67 instdone_bits[num_instdone_bits].reg = reg; in add_instdone_bit() 361 #define ring_read(ring, reg) I915_READ(ring->mmio + reg) argument 453 if (top_bit->bit->reg == INST_DONE_1) in update_idle_bit()
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H A D | intel_pm.c | 1098 u32 reg; in pineview_update_wm() local 1118 reg = I915_READ(DSPFW1); in pineview_update_wm() 1119 reg &= ~DSPFW_SR_MASK; in pineview_update_wm() 1121 I915_WRITE(DSPFW1, reg); in pineview_update_wm() 1128 reg = I915_READ(DSPFW3); in pineview_update_wm() 1131 I915_WRITE(DSPFW3, reg); in pineview_update_wm() 2738 int sprite_wm, reg; in sandybridge_update_sprite_wm() local 2746 reg = WM0_PIPEA_ILK; in sandybridge_update_sprite_wm() 2749 reg = WM0_PIPEB_ILK; in sandybridge_update_sprite_wm() 2752 reg = WM0_PIPEC_IVB; in sandybridge_update_sprite_wm() [all …]
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H A D | i915_ums.c | 54 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B); in i915_save_palette() local 62 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B; in i915_save_palette() 70 array[i] = I915_READ(reg + (i << 2)); in i915_save_palette() 76 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B); in i915_restore_palette() local 84 reg = (pipe == PIPE_A) ? _LGC_PALETTE_A : _LGC_PALETTE_B; in i915_restore_palette() 92 I915_WRITE(reg + (i << 2), array[i]); in i915_restore_palette()
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H A D | i915_irq.c | 320 u32 reg = PIPESTAT(pipe); in i915_enable_pipestat() local 328 I915_WRITE(reg, pipestat); in i915_enable_pipestat() 329 POSTING_READ(reg); in i915_enable_pipestat() 335 u32 reg = PIPESTAT(pipe); in i915_disable_pipestat() local 342 I915_WRITE(reg, pipestat); in i915_disable_pipestat() 343 POSTING_READ(reg); in i915_disable_pipestat() 417 return I915_READ(reg); in gm45_get_vblank_counter() 942 int reg = PIPESTAT(pipe); in valleyview_irq_handler() local 3011 int reg = PIPESTAT(pipe); in i8xx_irq_handler() local 3184 int reg = PIPESTAT(pipe); in i915_irq_handler() local [all …]
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H A D | intel_sprite.c | 506 int reg = DSPCNTR(intel_crtc->plane); in intel_enable_primary() local 514 I915_WRITE(reg, I915_READ(reg) | DISPLAY_PLANE_ENABLE); in intel_enable_primary() 523 int reg = DSPCNTR(intel_crtc->plane); in intel_disable_primary() local 528 I915_WRITE(reg, I915_READ(reg) & ~DISPLAY_PLANE_ENABLE); in intel_disable_primary()
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H A D | intel_i2c.c | 43 int reg; member 209 bus->gpio_reg = dev_priv->gpio_mmio_base + gmbus_ports[pin - 1].reg; in intel_gpio_setup()
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H A D | i915_dma.c | 71 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg) in intel_read_legacy_status_page() argument 75 return regs[reg]; in intel_read_legacy_status_page() 77 return intel_read_status_page(LP_RING(dev_priv), reg); in intel_read_legacy_status_page() 80 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg) argument
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H A D | i915_reg.h | 3397 #define I915_MODIFY_DISPBASE(reg, gfx_addr) \ argument 3398 (I915_WRITE((reg), (gfx_addr) | I915_LO_DISPBASE(I915_READ(reg)))) 4692 #define GEN7_PARITY_ERROR_ROW(reg) \ argument 4693 ((reg & GEN7_L3CDERRST1_ROW_MASK) >> 14) 4694 #define GEN7_PARITY_ERROR_BANK(reg) \ argument 4695 ((reg & GEN7_L3CDERRST1_BANK_MASK) >> 11) 4696 #define GEN7_PARITY_ERROR_SUBBANK(reg) \ argument 4697 ((reg & GEN7_L3CDERRST1_SUBBANK_MASK) >> 8)
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H A D | intel_ringbuffer.c | 975 u32 reg = RING_INSTPM(ring->mmio_base); in intel_ring_setup_status_page() local 976 I915_WRITE(reg, in intel_ring_setup_status_page() 979 if (wait_for((I915_READ(reg) & INSTPM_SYNC_FLUSH) == 0, in intel_ring_setup_status_page()
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/gfx-drm/usr/src/uts/intel/io/radeon/ |
H A D | r300_cmdbuf.c | 153 for (i = ((reg) >> 2); i < ((reg) >> 2) + (count); i++)\ in r300_init_reg_flags() 159 #define ADD_RANGE(reg, count) ADD_RANGE_MARK(reg, count, MARK_SAFE) in r300_init_reg_flags() argument 251 if (reg & ~0xffff) in r300_check_range() 253 for (i = (reg >> 2); i < (reg >> 2) + count; i++) in r300_check_range() 263 int reg; in r300_emit_carefully_checked_packet0() local 291 reg + i * 4, r300_reg_flags[(reg >> 2) + i]); in r300_emit_carefully_checked_packet0() 317 int reg; in r300_emit_packet0() local 330 if (reg + sz * 4 >= 0x10000) { in r300_emit_packet0() 332 reg, sz); in r300_emit_packet0() 336 if (r300_check_range(reg, sz)) { in r300_emit_packet0() [all …]
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H A D | radeon_drv.h | 1006 #define RADEON_READ(reg) \ argument 1007 DRM_READ32(dev_priv->mmio, (reg)) 1008 #define RADEON_WRITE(reg, val) \ argument 1010 #define RADEON_READ8(reg) \ argument 1011 DRM_READ8(dev_priv->mmio, (reg)) 1012 #define RADEON_WRITE8(reg, val) \ argument 1013 DRM_WRITE8(dev_priv->mmio, (reg), (val)) 1029 #define CP_PACKET0(reg, n) \ argument 1031 #define CP_PACKET0_TABLE(reg, n) \ argument 1175 #define OUT_RING_REG(reg, val) do { \ argument [all …]
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H A D | radeon_drm.h | 281 unsigned char cmd_type, reg, n_bufs, flags; member
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