xref: /illumos-gate/usr/src/uts/common/io/mwl/mwl_var.h (revision cb2cd10c)
1 /*
2  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
3  * Use is subject to license terms.
4  */
5 
6 /*
7  * Copyright (c) 2007-2009 Sam Leffler, Errno Consulting
8  * Copyright (c) 2007-2009 Marvell Semiconductor, Inc.
9  * All rights reserved.
10  *
11  * Redistribution and use in source and binary forms, with or without
12  * modification, are permitted provided that the following conditions
13  * are met:
14  * 1. Redistributions of source code must retain the above copyright
15  *    notice, this list of conditions and the following disclaimer,
16  *    without modification.
17  * 2. Redistributions in binary form must reproduce at minimum a disclaimer
18  *    similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
19  *    redistribution must be conditioned upon including a substantially
20  *    similar Disclaimer requirement for further binary redistribution.
21  *
22  * NO WARRANTY
23  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
24  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
25  * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
26  * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
27  * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
28  * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
31  * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
33  * THE POSSIBILITY OF SUCH DAMAGES.
34  */
35 
36 /*
37  * Definitions for the Marvell 88W8363 Wireless LAN controller.
38  */
39 
40 #ifndef	_MWL_VAR_H
41 #define	_MWL_VAR_H
42 
43 #ifdef __cplusplus
44 extern "C" {
45 #endif
46 
47 #include <sys/note.h>
48 #include "mwl_reg.h"
49 
50 #define	MWL_CMDBUF_SIZE		0x4000	/* size of f/w command buffer */
51 #define	MWL_RX_RING_COUNT	256
52 #define	MWL_TX_RING_COUNT	256
53 
54 #ifndef MWL_AGGR_SIZE
55 #define	MWL_AGGR_SIZE		3839	/* max tx agregation size */
56 #endif
57 #define	MWL_AGEINTERVAL		1	/* poke f/w every sec to age q's */
58 
59 /*
60  * Define total number of TX queues in the shared memory.
61  * This count includes the EDCA queues, Block Ack queues, and HCCA queues
62  * In addition to this, there could be a management packet queue some
63  * time in the future
64  */
65 #define	MWL_NUM_EDCA_QUEUES	4
66 #define	MWL_NUM_HCCA_QUEUES	0
67 #define	MWL_NUM_BA_QUEUES	0
68 #define	MWL_NUM_MGMT_QUEUES	0
69 #define	MWL_NUM_ACK_QUEUES	0
70 #define	MWL_NUM_TX_QUEUES \
71 	(MWL_NUM_EDCA_QUEUES + MWL_NUM_HCCA_QUEUES + MWL_NUM_BA_QUEUES + \
72 	MWL_NUM_MGMT_QUEUES + MWL_NUM_ACK_QUEUES)
73 #define	MWL_MAX_RXWCB_QUEUES	1
74 
75 #define	MWL_MAX_SUPPORTED_RATES	12
76 #define	MWL_MAX_SUPPORTED_MCS	32
77 
78 #define	PWTAGETRATETABLE20M	14 * 4
79 #define	PWTAGETRATETABLE40M	9 * 4
80 #define	PWTAGETRATETABLE20M_5G	35 * 4
81 #define	PWTAGETRATETABLE40M_5G	16 * 4
82 
83 #define	MHF_CALDATA	0x0001		/* cal data retrieved */
84 #define	MHF_FWHANG	0x0002		/* fw appears hung */
85 #define	MHF_MBSS	0x0004		/* mbss enabled */
86 
87 #define	IEEE80211_CHAN_STURBO	0x00002000 /* 11a static turbo channel only */
88 #define	IEEE80211_CHAN_HALF	0x00004000 /* Half rate channel */
89 #define	IEEE80211_CHAN_QUARTER	0x00008000 /* Quarter rate channel */
90 
91 #define	IEEE80211_CHAN_HT20	0x00010000 /* HT 20 channel */
92 #define	IEEE80211_CHAN_HT40U	0x00020000 /* HT 40 channel w/ ext above */
93 #define	IEEE80211_CHAN_HT40D	0x00040000 /* HT 40 channel w/ ext below */
94 
95 #define	IEEE80211_CHAN_FHSS \
96 	(IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_GFSK)
97 #define	IEEE80211_CHAN_A	\
98 	(IEEE80211_CHAN_5GHZ | IEEE80211_CHAN_OFDM)
99 #define	IEEE80211_CHAN_B	\
100 	(IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_CCK)
101 #define	IEEE80211_CHAN_PUREG \
102 	(IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_OFDM)
103 #define	IEEE80211_CHAN_G	\
104 	(IEEE80211_CHAN_2GHZ | IEEE80211_CHAN_DYN)
105 #define	IEEE80211_CHAN_HT40	\
106 	(IEEE80211_CHAN_HT40U | IEEE80211_CHAN_HT40D)
107 #define	IEEE80211_CHAN_HT	\
108 	(IEEE80211_CHAN_HT20 | IEEE80211_CHAN_HT40)
109 
110 #define	IEEE80211_CHAN_108A \
111 	(IEEE80211_CHAN_A | IEEE80211_CHAN_TURBO)
112 #define	IEEE80211_CHAN_108G \
113 	(IEEE80211_CHAN_PUREG | IEEE80211_CHAN_TURBO)
114 #define	IEEE80211_CHAN_ST \
115 	(IEEE80211_CHAN_108A | IEEE80211_CHAN_STURBO)
116 
117 #define	IEEE80211_MODE_STURBO_A	7
118 #define	IEEE80211_MODE_11NA	8	/* 5GHz, w/ HT */
119 #define	IEEE80211_MODE_11NG	9	/* 2GHz, w/ HT */
120 #define	IEEE80211_MODE_HALF	10	/* OFDM, 1/2x clock */
121 #define	IEEE80211_MODE_QUARTER	11	/* OFDM, 1/4x clock */
122 
123 
124 #define	IEEE80211_IS_CHAN_2GHZ_F(_c) \
125 	(((_c)->ic_flags & IEEE80211_CHAN_2GHZ) != 0)
126 #define	IEEE80211_IS_CHAN_5GHZ_F(_c) \
127 	(((_c)->ic_flags & IEEE80211_CHAN_5GHZ) != 0)
128 
129 #define	IEEE80211_IS_CHAN_FHSS(_c) \
130 	(((_c)->ic_flags & IEEE80211_CHAN_FHSS) == IEEE80211_CHAN_FHSS)
131 #define	IEEE80211_IS_CHAN_A(_c) \
132 	(((_c)->ic_flags & IEEE80211_CHAN_A) == IEEE80211_CHAN_A)
133 #define	IEEE80211_IS_CHAN_B(_c) \
134 	(((_c)->ic_flags & IEEE80211_CHAN_B) == IEEE80211_CHAN_B)
135 #define	IEEE80211_IS_CHAN_PUREG(_c) \
136 	(((_c)->ic_flags & IEEE80211_CHAN_PUREG) == IEEE80211_CHAN_PUREG)
137 #define	IEEE80211_IS_CHAN_G(_c) \
138 	(((_c)->ic_flags & IEEE80211_CHAN_G) == IEEE80211_CHAN_G)
139 #define	IEEE80211_IS_CHAN_ANYG(_c) \
140 	(IEEE80211_IS_CHAN_PUREG(_c) || IEEE80211_IS_CHAN_G(_c))
141 #define	IEEE80211_IS_CHAN_ST(_c) \
142 	(((_c)->ic_flags & IEEE80211_CHAN_ST) == IEEE80211_CHAN_ST)
143 #define	IEEE80211_IS_CHAN_108A(_c) \
144 	(((_c)->ic_flags & IEEE80211_CHAN_108A) == IEEE80211_CHAN_108A)
145 #define	IEEE80211_IS_CHAN_108G(_c) \
146 	(((_c)->ic_flags & IEEE80211_CHAN_108G) == IEEE80211_CHAN_108G)
147 
148 #define	IEEE80211_IS_CHAN_HTA(_c) \
149 	(IEEE80211_IS_CHAN_5GHZ_F(_c) && \
150 	((_c)->ic_flags & IEEE80211_CHAN_HT) != 0)
151 
152 #define	IEEE80211_IS_CHAN_HTG(_c) \
153 	(IEEE80211_IS_CHAN_2GHZ_F(_c) && \
154 	((_c)->ic_flags & IEEE80211_CHAN_HT) != 0)
155 
156 #define	IEEE80211_IS_CHAN_TURBO(_c) \
157 	(((_c)->ic_flags & IEEE80211_CHAN_TURBO) != 0)
158 
159 #define	IEEE80211_IS_CHAN_HALF(_c) \
160 	(((_c)->ic_flags & IEEE80211_CHAN_HALF) != 0)
161 
162 #define	IEEE80211_IS_CHAN_QUARTER(_c) \
163 	(((_c)->ic_flags & IEEE80211_CHAN_QUARTER) != 0)
164 
165 /* WME stream classes */
166 #define	WME_AC_BE	0		/* best effort */
167 #define	WME_AC_BK	1		/* background */
168 #define	WME_AC_VI	2		/* video */
169 #define	WME_AC_VO	3		/* voice */
170 
171 /*
172  * Transmit queue assignment.
173  */
174 enum {
175 	MWL_WME_AC_BK	= 0,		/* background access category */
176 	MWL_WME_AC_BE	= 1, 		/* best effort access category */
177 	MWL_WME_AC_VI	= 2,		/* video access category */
178 	MWL_WME_AC_VO	= 3,		/* voice access category */
179 };
180 
181 const char *mwl_wme_acnames[] = {
182 	"WME_AC_BE",
183 	"WME_AC_BK",
184 	"WME_AC_VI",
185 	"WME_AC_VO",
186 	"WME_UPSD",
187 };
188 
189 /*
190  * Set Antenna Configuration (legacy operation).
191  *
192  * The RX antenna can be selected using the the bitmask
193  * ant (bit 0 = antenna 1, bit 1 = antenna 2, etc.)
194  * (diversity?XXX)
195  */
196 typedef enum {
197 	WL_ANTENNATYPE_RX = 1,
198 	WL_ANTENNATYPE_TX = 2,
199 } MWL_HAL_ANTENNA;
200 
201 /*
202  * Set Radio Configuration.
203  *
204  * onoff != 0 turns radio on; otherwise off.
205  * if radio is enabled, the preamble is set too.
206  */
207 typedef enum {
208 	WL_LONG_PREAMBLE = 1,
209 	WL_SHORT_PREAMBLE = 3,
210 	WL_AUTO_PREAMBLE = 5,
211 } MWL_HAL_PREAMBLE;
212 
213 /*
214  * Transmit rate control.  Rate codes with bit 0x80 set are
215  * interpreted as MCS codes (this limits us to 0-127).  The
216  * transmit rate can be set to a single fixed rate or can
217  * be configured to start at an initial rate and drop based
218  * on retry counts.
219  */
220 typedef enum {
221 	RATE_AUTO	= 0,	/* rate selected by firmware */
222 	RATE_FIXED	= 2,	/* rate fixed */
223 	RATE_FIXED_DROP	= 1,	/* rate starts fixed but may drop */
224 } MWL_HAL_TXRATE_HANDLING;
225 
226 typedef enum {
227 	CSMODE_CONSERVATIVE = 0,
228 	CSMODE_AGGRESSIVE = 1,
229 	CSMODE_AUTO_ENA = 2,
230 	CSMODE_AUTO_DIS = 3,
231 } MWL_HAL_CSMODE;
232 
233 #pragma pack(1)
234 
235 /*
236  * Device revision information.
237  */
238 typedef struct {
239 	uint16_t	mh_devid;		/* PCI device ID */
240 	uint16_t	mh_subvendorid;		/* PCI subvendor ID */
241 	uint16_t	mh_macRev;		/* MAC revision */
242 	uint16_t	mh_phyRev;		/* PHY revision */
243 } MWL_DIAG_REVS;
244 
245 typedef struct {
246 	uint16_t freqLow;
247 	uint16_t freqHigh;
248 	int nchannels;
249 	struct mwl_hal_channel {
250 		uint16_t freq;		/* channel center */
251 		uint8_t ieee;		/* channel number */
252 		int8_t maxTxPow;	/* max tx power (dBm) */
253 		uint8_t targetPowers[4]; /* target powers (dBm) */
254 #define	MWL_HAL_MAXCHAN	40
255 	} channels[MWL_HAL_MAXCHAN];
256 } MWL_HAL_CHANNELINFO;
257 
258 typedef struct {
259     uint32_t	FreqBand : 6,
260 #define	MWL_FREQ_BAND_2DOT4GHZ	0x1
261 #define	MWL_FREQ_BAND_5GHZ	0x4
262 		ChnlWidth: 5,
263 #define	MWL_CH_10_MHz_WIDTH  	0x1
264 #define	MWL_CH_20_MHz_WIDTH  	0x2
265 #define	MWL_CH_40_MHz_WIDTH  	0x4
266 		ExtChnlOffset: 2,
267 #define	MWL_EXT_CH_NONE		0x0
268 #define	MWL_EXT_CH_ABOVE_CTRL_CH 0x1
269 #define	MWL_EXT_CH_BELOW_CTRL_CH 0x3
270 		    : 19;		/* reserved */
271 } MWL_HAL_CHANNEL_FLAGS;
272 
273 typedef struct {
274     uint32_t	channel;
275     MWL_HAL_CHANNEL_FLAGS channelFlags;
276 } MWL_HAL_CHANNEL;
277 
278 /*
279  * Channels are specified by frequency and attributes.
280  */
281 struct mwl_channel {
282 	uint32_t	ic_flags;	/* see below */
283 	uint16_t	ic_freq;	/* setting in Mhz */
284 	uint8_t		ic_ieee;	/* IEEE channel number */
285 	int8_t		ic_maxregpower;	/* maximum regulatory tx power in dBm */
286 	int8_t		ic_maxpower;	/* maximum tx power in .5 dBm */
287 	int8_t		ic_minpower;	/* minimum tx power in .5 dBm */
288 	uint8_t		ic_state;	/* dynamic state */
289 	uint8_t		ic_extieee;	/* HT40 extension channel number */
290 	int8_t		ic_maxantgain;	/* maximum antenna gain in .5 dBm */
291 	uint8_t		ic_pad;
292 	uint16_t	ic_devdata;	/* opaque device/driver data */
293 };
294 
295 /*
296  * Regulatory Information.
297  */
298 struct mwl_regdomain {
299 	uint16_t	regdomain;	/* SKU */
300 	uint16_t	country;	/* ISO country code */
301 	uint8_t		location;	/* I (indoor), O (outdoor), other */
302 	uint8_t		ecm;		/* Extended Channel Mode */
303 	char		isocc[2];	/* country code string */
304 	short		pad[2];
305 };
306 
307 /*
308  * Get Hardware/Firmware capabilities.
309  */
310 struct mwl_hal_hwspec {
311 	uint8_t		hwVersion;	/* version of the HW */
312 	uint8_t		hostInterface;	/* host interface */
313 	uint16_t	maxNumWCB;	/* max # of WCB FW handles */
314 	uint16_t	maxNumMCAddr;	/* max # of mcast addresse FW handles */
315 	uint16_t	maxNumTxWcb;	/* max # of tx descs per WCB */
316 	uint8_t		macAddr[6];	/* MAC address programmed in HW */
317 	uint16_t	regionCode;	/* EEPROM region code */
318 	uint16_t	numAntennas;	/* Number of antenna used */
319 	uint32_t	fwReleaseNumber; /* firmware release number */
320 	uint32_t	wcbBase0;
321 	uint32_t	rxDescRead;
322 	uint32_t	rxDescWrite;
323 	uint32_t	ulFwAwakeCookie;
324 	uint32_t	wcbBase[MWL_NUM_TX_QUEUES - MWL_NUM_ACK_QUEUES];
325 };
326 
327 /*
328  * Crypto Configuration.
329  */
330 typedef struct {
331 	uint16_t	pad;
332 	uint16_t	keyTypeId;
333 #define	KEY_TYPE_ID_WEP		0
334 #define	KEY_TYPE_ID_TKIP	1
335 #define	KEY_TYPE_ID_AES		2	/* AES-CCMP */
336 	uint32_t	keyFlags;
337 #define	KEY_FLAG_INUSE		0x00000001	/* indicate key is in use */
338 #define	KEY_FLAG_RXGROUPKEY	0x00000002	/* Group key for RX only */
339 #define	KEY_FLAG_TXGROUPKEY	0x00000004	/* Group key for TX */
340 #define	KEY_FLAG_PAIRWISE	0x00000008	/* pairwise */
341 #define	KEY_FLAG_RXONLY		0x00000010	/* only used for RX */
342 #define	KEY_FLAG_AUTHENTICATOR	0x00000020	/* Key is for Authenticator */
343 #define	KEY_FLAG_TSC_VALID	0x00000040	/* Sequence counters valid */
344 #define	KEY_FLAG_WEP_TXKEY	0x01000000	/* Tx key for WEP */
345 #define	KEY_FLAG_MICKEY_VALID	0x02000000	/* Tx/Rx MIC keys are valid */
346 	uint32_t	keyIndex; 	/* for WEP only; actual key index */
347 	uint16_t	keyLen;		/* key size in bytes */
348 	union {			/* key material, keyLen gives size */
349 		uint8_t	wep[16];	/* enough for 128 bits */
350 		uint8_t	aes[16];
351 		struct	{
352 		    /* NB: group or pairwise key is determined by keyFlags */
353 		    uint8_t	keyMaterial[16];
354 		    uint8_t	txMic[8];
355 		    uint8_t	rxMic[8];
356 		    struct {
357 			uint16_t	low;
358 			uint32_t	high;
359 		    } rsc;
360 		struct	{
361 			uint16_t	low;
362 			uint32_t	high;
363 		    } tsc;
364 		} tkip;
365 	} key;
366 } MWL_HAL_KEYVAL;
367 
368 /*
369  * Supply tx/rx dma-related settings to the firmware.
370  */
371 struct mwl_hal_txrxdma {
372 	uint32_t   maxNumWCB;		/* max # of WCB FW handles */
373 	uint32_t   maxNumTxWcb;		/* max # of tx descs per WCB */
374 	uint32_t   rxDescRead;
375 	uint32_t   rxDescWrite;
376 	uint32_t   wcbBase[MWL_NUM_TX_QUEUES - MWL_NUM_ACK_QUEUES];
377 };
378 
379 /*
380  * Inform the firmware of a new association station.
381  * The address is the MAC address of the peer station.
382  * The AID is supplied sans the 0xc000 bits.  The station
383  * ID is defined by the caller.  The peer information must
384  * be supplied.
385  *
386  * NB: All values are in host byte order; any byte swapping
387  *     is handled by the hal.
388  */
389 typedef struct {
390 	uint32_t LegacyRateBitMap;
391 	uint32_t HTRateBitMap;
392 	uint16_t CapInfo;
393 	uint16_t HTCapabilitiesInfo;
394 	uint8_t	MacHTParamInfo;
395 	uint8_t	Rev;
396 	struct {
397 	    uint8_t ControlChan;
398 	    uint8_t AddChan;
399 	    uint8_t OpMode;
400 	    uint8_t stbc;
401 	} AddHtInfo;
402 } MWL_HAL_PEERINFO;
403 
404 typedef struct {
405 	uint8_t	McastRate;	/* rate for multicast frames */
406 #define	RATE_MCS	0x80	/* rate is an MCS index */
407 	uint8_t	MgtRate;	/* rate for management frames */
408 	struct {
409 	    uint8_t TryCount;	/* try this many times */
410 	    uint8_t Rate;	/* use this tx rate */
411 	} RateSeries[4];	/* rate series */
412 } MWL_HAL_TXRATE;
413 
414 #pragma pack()
415 
416 /* driver-specific node state */
417 struct mwl_node {
418 	struct ieee80211_node	mn_node;	/* base class */
419 	struct mwl_ant_info	mn_ai;		/* antenna info */
420 	uint32_t	mn_avgrssi;	/* average rssi over all rx frames */
421 	uint16_t	mn_staid;	/* firmware station id */
422 };
423 #define	MWL_NODE(ni)		((struct mwl_node *)(ni))
424 #define	MWL_NODE_CONST(ni)	((const struct mwl_node *)(ni))
425 
426 /*
427  * DMA state for tx/rx.
428  */
429 
430 /*
431  * Software backed version of tx/rx descriptors.  We keep
432  * the software state out of the h/w descriptor structure
433  * so that may be allocated in uncached memory w/o paying
434  * performance hit.
435  */
436 struct dma_area {
437 	ddi_acc_handle_t	acc_hdl;	/* handle for memory */
438 	caddr_t			mem_va;		/* CPU VA of memory */
439 	uint32_t		nslots;		/* number of slots */
440 	uint32_t		size;		/* size per slot */
441 	size_t			alength;	/* allocated size */
442 	ddi_dma_handle_t	dma_hdl;	/* DMA handle */
443 	offset_t		offset;		/* relative to handle */
444 	ddi_dma_cookie_t	cookie;		/* associated cookie */
445 	uint32_t		ncookies;	/* must be 1 */
446 	uint32_t		token;		/* arbitrary identifier */
447 };
448 
449 struct mwl_rxbuf {
450 	struct dma_area		rxbuf_dma;	/* dma area for buf */
451 	uint32_t		bf_baddr;
452 	uint8_t			*bf_mem;
453 	void			*bf_desc;
454 	uint32_t		bf_daddr;
455 };
456 
457 struct mwl_rx_ring {
458 	struct dma_area		rxdesc_dma;
459 	uint32_t		physaddr;
460 	struct mwl_rxdesc	*desc;
461 	struct mwl_rxbuf	*buf;
462 	int			count;
463 	int			cur;
464 	int			next;
465 };
466 
467 struct mwl_txbuf {
468 	struct dma_area		txbuf_dma;
469 	uint32_t		bf_baddr;	/* physical addr of buf */
470 	uint8_t			*bf_mem;
471 	uint32_t		bf_daddr;	/* physical addr of desc */
472 	void 			*bf_desc;	/* h/w descriptor */
473 	int			bf_nseg;
474 	struct ieee80211_node	*bf_node;
475 	struct mwl_txq		*bf_txq;	/* backpointer to tx q/ring */
476 };
477 
478 struct mwl_tx_ring {
479 	struct dma_area		txdesc_dma;
480 	uint32_t		physaddr;
481 	struct mwl_txdesc	*desc;
482 	struct mwl_txbuf	*buf;
483 	int			qnum;	/* f/w q number */
484 	int			txpri;	/* f/w tx priority */
485 	int			count;
486 	int			queued;
487 	int			cur;
488 	int			next;
489 	int			stat;
490 };
491 
492 struct mwl_softc {
493 	ieee80211com_t		sc_ic;
494 	dev_info_t		*sc_dev;
495 
496 	/* ddi reg handler */
497 	ddi_acc_handle_t	sc_cfg_handle;
498 	caddr_t			sc_cfg_base;
499 
500 	/* bar0 handler */
501 	ddi_acc_handle_t	sc_mem_handle;
502 	caddr_t			sc_mem_base;
503 
504 	/* bar1 handler */
505 	ddi_acc_handle_t	sc_io_handle;
506 	caddr_t			sc_io_base;
507 
508 	uint16_t		sc_cachelsz;
509 	uint32_t		sc_dmabuf_size;
510 	uchar_t			sc_macaddr[6];
511 
512 	struct dma_area		sc_cmd_dma;
513 	uint16_t		*sc_cmd_mem;	/* f/w cmd buffer */
514 	uint32_t		sc_cmd_dmaaddr;	/* physaddr of cmd buffer */
515 
516 	int			sc_hw_flags;
517 	uint32_t		sc_flags;
518 
519 	/* SDRAM addr in the chipset */
520 	int			sc_SDRAMSIZE_Addr;
521 
522 	MWL_HAL_CHANNELINFO	sc_20M;
523 	MWL_HAL_CHANNELINFO	sc_40M;
524 	MWL_HAL_CHANNELINFO	sc_20M_5G;
525 	MWL_HAL_CHANNELINFO	sc_40M_5G;
526 
527 	struct mwl_hal_hwspec	sc_hwspecs;	/* h/w capabilities */
528 	MWL_DIAG_REVS		sc_revs;
529 
530 	int			sc_nchans;	/* # entries in ic_channels */
531 	struct mwl_channel 	sc_channels[IEEE80211_CHAN_MAX];
532 	struct mwl_channel 	*sc_cur_chan;
533 	MWL_HAL_CHANNEL		sc_curchan;
534 	struct mwl_regdomain 	sc_regdomain; /* regulatory data */
535 
536 	struct mwl_rx_ring	sc_rxring;
537 	struct mwl_tx_ring	sc_txring[MWL_NUM_TX_QUEUES];
538 	struct mwl_tx_ring	*sc_ac2q[5];	/* WME AC -> h/w q map */
539 
540 	struct mwl_hal_txrxdma	sc_hwdma;	/* h/w dma setup */
541 
542 	/* interrupt */
543 	ddi_iblock_cookie_t	sc_iblock;
544 	ddi_softint_handle_t	sc_softintr_hdl;
545 	ddi_intr_handle_t	*sc_intr_htable;
546 	uint_t			sc_intr_pri;
547 	uint32_t		sc_imask;	/* interrupt mask */
548 	uint32_t		sc_hal_imask;	/* interrupt mask copy */
549 	uint32_t		sc_rx_pend;
550 
551 	/* mutex lock */
552 	kmutex_t		sc_glock;
553 	kmutex_t		sc_rxlock;
554 	kmutex_t		sc_txlock;
555 
556 	uint16_t		sc_rxantenna;	/* rx antenna */
557 	uint16_t		sc_txantenna;	/* tx antenna */
558 
559 	timeout_id_t		sc_scan_id;
560 
561 	/* kstats */
562 	uint32_t		sc_tx_nobuf;
563 	uint32_t		sc_rx_nobuf;
564 	uint32_t		sc_tx_err;
565 	uint32_t		sc_rx_err;
566 	uint32_t		sc_tx_retries;
567 
568 	uint32_t		sc_need_sched;
569 	uint32_t		sc_rcr;
570 
571 	int			(*sc_newstate)(struct ieee80211com *,
572 				    enum ieee80211_state, int);
573 };
574 
575 #define	mwl_mem_write4(sc, off, x) \
576 	ddi_put32((sc)->sc_mem_handle, \
577 	(uint32_t *)((sc)->sc_mem_base + (off)), x)
578 
579 #define	mwl_mem_read4(sc, off) \
580 	ddi_get32((sc)->sc_mem_handle, \
581 	(uint32_t *)((sc)->sc_mem_base + (off)))
582 
583 #define	mwl_ctl_write4(sc, off, x) \
584 	ddi_put32((sc)->sc_io_handle, \
585 	(uint32_t *)((sc)->sc_io_base + (off)), x)
586 
587 #define	mwl_ctl_read4(sc, off) \
588 	ddi_get32((sc)->sc_io_handle, \
589 	(uint32_t *)((sc)->sc_io_base + (off)))
590 
591 #define	mwl_ctl_read1(sc, off) \
592 	ddi_get8((sc)->sc_io_handle, \
593 	(uint8_t *)((sc)->sc_io_base + (off)))
594 
595 #define	_CMD_SETUP(pCmd, type, cmd) do {				\
596 	pCmd = (type *)&sc->sc_cmd_mem[0];				\
597 	(void) memset(pCmd, 0, sizeof (type));				\
598 	pCmd->CmdHdr.Cmd = LE_16(cmd);					\
599 	pCmd->CmdHdr.Length = LE_16(sizeof (type));			\
600 	_NOTE(CONSTCOND)						\
601 } while (0)
602 
603 #define	_VCMD_SETUP(pCmd, type, cmd) do {				\
604 	_CMD_SETUP(pCmd, type, cmd);					\
605 	pCmd->CmdHdr.MacId = 8;						\
606 	_NOTE(CONSTCOND)						\
607 } while (0)
608 
609 #define	MWL_GLOCK(_sc)		mutex_enter(&(_sc)->sc_glock)
610 #define	MWL_GUNLOCK(_sc)	mutex_exit(&(_sc)->sc_glock)
611 
612 #define	MWL_RXLOCK(_sc)		mutex_enter(&(_sc)->sc_rxlock)
613 #define	MWL_RXUNLOCK(_sc)	mutex_exit(&(_sc)->sc_rxlock)
614 
615 #define	MWL_TXLOCK(_sc)		mutex_enter(&(_sc)->sc_txlock)
616 #define	MWL_TXUNLOCK(_sc)	mutex_exit(&(_sc)->sc_txlock)
617 
618 #define	MWL_F_RUNNING		(1 << 0)
619 #define	MWL_F_SUSPEND		(1 << 1)
620 #define	MWL_F_QUIESCE		(1 << 2)
621 
622 #define	MWL_RCR_PROMISC		(1 << 0)
623 #define	MWL_RCR_MULTI		(1 << 1)
624 
625 #define	MWL_IS_RUNNING(_sc)	(((_sc)->sc_flags & MWL_F_RUNNING))
626 #define	MWL_IS_SUSPEND(_sc)	(((_sc)->sc_flags & MWL_F_SUSPEND))
627 #define	MWL_IS_QUIESCE(_sc)	(((_sc)->sc_flags & MWL_F_QUIESCE))
628 
629 /*
630  * 802.11 regulatory domain definitions.
631  */
632 enum ISOCountryCode {
633 	CTRY_AFGHANISTAN	= 4,
634 	CTRY_ALBANIA		= 8,	/* Albania */
635 	CTRY_ALGERIA		= 12,	/* Algeria */
636 	CTRY_AMERICAN_SAMOA	= 16,
637 	CTRY_ANDORRA		= 20,
638 	CTRY_ANGOLA		= 24,
639 	CTRY_ANGUILLA		= 660,
640 	CTRY_ANTARTICA		= 10,
641 	CTRY_ANTIGUA		= 28,	/* Antigua and Barbuda */
642 	CTRY_ARGENTINA		= 32,	/* Argentina */
643 	CTRY_ARMENIA		= 51,	/* Armenia */
644 	CTRY_ARUBA		= 533,	/* Aruba */
645 	CTRY_AUSTRALIA		= 36,	/* Australia */
646 	CTRY_AUSTRIA		= 40,	/* Austria */
647 	CTRY_AZERBAIJAN		= 31,	/* Azerbaijan */
648 	CTRY_BAHAMAS		= 44,	/* Bahamas */
649 	CTRY_BAHRAIN		= 48,	/* Bahrain */
650 	CTRY_BANGLADESH		= 50,	/* Bangladesh */
651 	CTRY_BARBADOS		= 52,
652 	CTRY_BELARUS		= 112,	/* Belarus */
653 	CTRY_BELGIUM		= 56,	/* Belgium */
654 	CTRY_BELIZE		= 84,
655 	CTRY_BENIN		= 204,
656 	CTRY_BERMUDA		= 60,
657 	CTRY_BHUTAN		= 64,
658 	CTRY_BOLIVIA		= 68,	/* Bolivia */
659 	CTRY_BOSNIA_AND_HERZEGOWINA = 70,
660 	CTRY_BOTSWANA		= 72,
661 	CTRY_BOUVET_ISLAND	= 74,
662 	CTRY_BRAZIL		= 76,	/* Brazil */
663 	CTRY_BRITISH_INDIAN_OCEAN_TERRITORY = 86,
664 	CTRY_BRUNEI_DARUSSALAM	= 96,	/* Brunei Darussalam */
665 	CTRY_BULGARIA		= 100,	/* Bulgaria */
666 	CTRY_BURKINA_FASO	= 854,
667 	CTRY_BURUNDI		= 108,
668 	CTRY_CAMBODIA		= 116,
669 	CTRY_CAMEROON		= 120,
670 	CTRY_CANADA		= 124,	/* Canada */
671 	CTRY_CAPE_VERDE		= 132,
672 	CTRY_CAYMAN_ISLANDS	= 136,
673 	CTRY_CENTRAL_AFRICAN_REPUBLIC = 140,
674 	CTRY_CHAD		= 148,
675 	CTRY_CHILE		= 152,	/* Chile */
676 	CTRY_CHINA		= 156,	/* People's Republic of China */
677 	CTRY_CHRISTMAS_ISLAND	= 162,
678 	CTRY_COCOS_ISLANDS	= 166,
679 	CTRY_COLOMBIA		= 170,	/* Colombia */
680 	CTRY_COMOROS		= 174,
681 	CTRY_CONGO		= 178,
682 	CTRY_COOK_ISLANDS	= 184,
683 	CTRY_COSTA_RICA		= 188,	/* Costa Rica */
684 	CTRY_COTE_DIVOIRE	= 384,
685 	CTRY_CROATIA		= 191,	/* Croatia (local name: Hrvatska) */
686 	CTRY_CYPRUS		= 196,	/* Cyprus */
687 	CTRY_CZECH		= 203,	/* Czech Republic */
688 	CTRY_DENMARK		= 208,	/* Denmark */
689 	CTRY_DJIBOUTI		= 262,
690 	CTRY_DOMINICA		= 212,
691 	CTRY_DOMINICAN_REPUBLIC	= 214,	/* Dominican Republic */
692 	CTRY_EAST_TIMOR		= 626,
693 	CTRY_ECUADOR		= 218,	/* Ecuador */
694 	CTRY_EGYPT		= 818,	/* Egypt */
695 	CTRY_EL_SALVADOR	= 222,	/* El Salvador */
696 	CTRY_EQUATORIAL_GUINEA	= 226,
697 	CTRY_ERITREA		= 232,
698 	CTRY_ESTONIA		= 233,	/* Estonia */
699 	CTRY_ETHIOPIA		= 210,
700 	CTRY_FALKLAND_ISLANDS	= 238,	/* (Malvinas) */
701 	CTRY_FAEROE_ISLANDS	= 234,	/* Faeroe Islands */
702 	CTRY_FIJI		= 242,
703 	CTRY_FINLAND		= 246,	/* Finland */
704 	CTRY_FRANCE		= 250,	/* France */
705 	CTRY_FRANCE2		= 255,	/* France (Metropolitan) */
706 	CTRY_FRENCH_GUIANA	= 254,
707 	CTRY_FRENCH_POLYNESIA	= 258,
708 	CTRY_FRENCH_SOUTHERN_TERRITORIES	= 260,
709 	CTRY_GABON		= 266,
710 	CTRY_GAMBIA		= 270,
711 	CTRY_GEORGIA		= 268,	/* Georgia */
712 	CTRY_GERMANY		= 276,	/* Germany */
713 	CTRY_GHANA		= 288,
714 	CTRY_GIBRALTAR		= 292,
715 	CTRY_GREECE		= 300,	/* Greece */
716 	CTRY_GREENLAND		= 304,
717 	CTRY_GRENADA		= 308,
718 	CTRY_GUADELOUPE		= 312,
719 	CTRY_GUAM		= 316,
720 	CTRY_GUATEMALA		= 320,	/* Guatemala */
721 	CTRY_GUINEA		= 324,
722 	CTRY_GUINEA_BISSAU	= 624,
723 	CTRY_GUYANA		= 328,
724 	/* XXX correct remainder */
725 	CTRY_HAITI		= 332,
726 	CTRY_HONDURAS		= 340,	/* Honduras */
727 	CTRY_HONG_KONG		= 344,	/* Hong Kong S.A.R., P.R.C. */
728 	CTRY_HUNGARY		= 348,	/* Hungary */
729 	CTRY_ICELAND		= 352,	/* Iceland */
730 	CTRY_INDIA		= 356,	/* India */
731 	CTRY_INDONESIA		= 360,	/* Indonesia */
732 	CTRY_IRAN		= 364,	/* Iran */
733 	CTRY_IRAQ		= 368,	/* Iraq */
734 	CTRY_IRELAND		= 372,	/* Ireland */
735 	CTRY_ISRAEL		= 376,	/* Israel */
736 	CTRY_ITALY		= 380,	/* Italy */
737 	CTRY_JAMAICA		= 388,	/* Jamaica */
738 	CTRY_JAPAN		= 392,	/* Japan */
739 	CTRY_JORDAN		= 400,	/* Jordan */
740 	CTRY_KAZAKHSTAN		= 398,	/* Kazakhstan */
741 	CTRY_KENYA		= 404,	/* Kenya */
742 	CTRY_KOREA_NORTH	= 408,	/* North Korea */
743 	CTRY_KOREA_ROC		= 410,	/* South Korea */
744 	CTRY_KOREA_ROC2		= 411,	/* South Korea */
745 	CTRY_KUWAIT		= 414,	/* Kuwait */
746 	CTRY_LATVIA		= 428,	/* Latvia */
747 	CTRY_LEBANON		= 422,	/* Lebanon */
748 	CTRY_LIBYA		= 434,	/* Libya */
749 	CTRY_LIECHTENSTEIN	= 438,	/* Liechtenstein */
750 	CTRY_LITHUANIA		= 440,	/* Lithuania */
751 	CTRY_LUXEMBOURG		= 442,	/* Luxembourg */
752 	CTRY_MACAU		= 446,	/* Macau */
753 	CTRY_MACEDONIA		= 807,	/* Macedonia */
754 	CTRY_MALAYSIA		= 458,	/* Malaysia */
755 	CTRY_MALTA		= 470,	/* Malta */
756 	CTRY_MEXICO		= 484,	/* Mexico */
757 	CTRY_MONACO		= 492,	/* Principality of Monaco */
758 	CTRY_MOROCCO		= 504,	/* Morocco */
759 	CTRY_NEPAL		= 524,	/* Nepal */
760 	CTRY_NETHERLANDS	= 528,	/* Netherlands */
761 	CTRY_NEW_ZEALAND	= 554,	/* New Zealand */
762 	CTRY_NICARAGUA		= 558,	/* Nicaragua */
763 	CTRY_NORWAY		= 578,	/* Norway */
764 	CTRY_OMAN		= 512,	/* Oman */
765 	CTRY_PAKISTAN		= 586,	/* Islamic Republic of Pakistan */
766 	CTRY_PANAMA		= 591,	/* Panama */
767 	CTRY_PARAGUAY		= 600,	/* Paraguay */
768 	CTRY_PERU		= 604,	/* Peru */
769 	CTRY_PHILIPPINES	= 608,	/* Republic of the Philippines */
770 	CTRY_POLAND		= 616,	/* Poland */
771 	CTRY_PORTUGAL		= 620,	/* Portugal */
772 	CTRY_PUERTO_RICO	= 630,	/* Puerto Rico */
773 	CTRY_QATAR		= 634,	/* Qatar */
774 	CTRY_ROMANIA		= 642,	/* Romania */
775 	CTRY_RUSSIA		= 643,	/* Russia */
776 	CTRY_SAUDI_ARABIA	= 682,	/* Saudi Arabia */
777 	CTRY_SINGAPORE		= 702,	/* Singapore */
778 	CTRY_SLOVAKIA		= 703,	/* Slovak Republic */
779 	CTRY_SLOVENIA		= 705,	/* Slovenia */
780 	CTRY_SOUTH_AFRICA	= 710,	/* South Africa */
781 	CTRY_SPAIN		= 724,	/* Spain */
782 	CTRY_SRILANKA		= 144,	/* Sri Lanka */
783 	CTRY_SWEDEN		= 752,	/* Sweden */
784 	CTRY_SWITZERLAND	= 756,	/* Switzerland */
785 	CTRY_SYRIA		= 760,	/* Syria */
786 	CTRY_TAIWAN		= 158,	/* Taiwan */
787 	CTRY_THAILAND		= 764,	/* Thailand */
788 	CTRY_TRINIDAD_Y_TOBAGO	= 780,	/* Trinidad y Tobago */
789 	CTRY_TUNISIA		= 788,	/* Tunisia */
790 	CTRY_TURKEY		= 792,	/* Turkey */
791 	CTRY_UAE		= 784,	/* U.A.E. */
792 	CTRY_UKRAINE		= 804,	/* Ukraine */
793 	CTRY_UNITED_KINGDOM	= 826,	/* United Kingdom */
794 	CTRY_UNITED_STATES	= 840,	/* United States */
795 	CTRY_URUGUAY		= 858,	/* Uruguay */
796 	CTRY_UZBEKISTAN		= 860,	/* Uzbekistan */
797 	CTRY_VENEZUELA		= 862,	/* Venezuela */
798 	CTRY_VIET_NAM		= 704,	/* Viet Nam */
799 	CTRY_YEMEN		= 887,	/* Yemen */
800 	CTRY_ZIMBABWE		= 716,	/* Zimbabwe */
801 
802 	/* NB: from here down not listed in 3166; they come from Atheros */
803 	CTRY_DEBUG		= 0x1ff, /* debug */
804 	CTRY_DEFAULT		= 0,	 /* default */
805 
806 	CTRY_UNITED_STATES_FCC49 = 842,	/* United States (Public Safety) */
807 	CTRY_KOREA_ROC3		= 412,	/* South Korea */
808 
809 	CTRY_JAPAN1		= 393,	/* Japan (JP1) */
810 	CTRY_JAPAN2		= 394,	/* Japan (JP0) */
811 	CTRY_JAPAN3		= 395,	/* Japan (JP1-1) */
812 	CTRY_JAPAN4		= 396,	/* Japan (JE1) */
813 	CTRY_JAPAN5		= 397,	/* Japan (JE2) */
814 	CTRY_JAPAN6		= 399,	/* Japan (JP6) */
815 	CTRY_JAPAN7		= 4007,	/* Japan (J7) */
816 	CTRY_JAPAN8		= 4008,	/* Japan (J8) */
817 	CTRY_JAPAN9		= 4009,	/* Japan (J9) */
818 	CTRY_JAPAN10		= 4010,	/* Japan (J10) */
819 	CTRY_JAPAN11		= 4011,	/* Japan (J11) */
820 	CTRY_JAPAN12		= 4012,	/* Japan (J12) */
821 	CTRY_JAPAN13		= 4013,	/* Japan (J13) */
822 	CTRY_JAPAN14		= 4014,	/* Japan (J14) */
823 	CTRY_JAPAN15		= 4015,	/* Japan (J15) */
824 	CTRY_JAPAN16		= 4016,	/* Japan (J16) */
825 	CTRY_JAPAN17		= 4017,	/* Japan (J17) */
826 	CTRY_JAPAN18		= 4018,	/* Japan (J18) */
827 	CTRY_JAPAN19		= 4019,	/* Japan (J19) */
828 	CTRY_JAPAN20		= 4020,	/* Japan (J20) */
829 	CTRY_JAPAN21		= 4021,	/* Japan (J21) */
830 	CTRY_JAPAN22		= 4022,	/* Japan (J22) */
831 	CTRY_JAPAN23		= 4023,	/* Japan (J23) */
832 	CTRY_JAPAN24		= 4024,	/* Japan (J24) */
833 };
834 
835 enum RegdomainCode {
836 	SKU_FCC			= 0x10,	/* FCC, aka United States */
837 	SKU_CA			= 0x20,	/* North America, aka Canada */
838 	SKU_ETSI		= 0x30,	/* Europe */
839 	SKU_ETSI2		= 0x32,	/* Europe w/o HT40 in 5GHz */
840 	SKU_ETSI3		= 0x33,	/* Europe - channel 36 */
841 	SKU_FCC3		= 0x3a,	/* FCC w/5470 band, 11h, DFS */
842 	SKU_JAPAN		= 0x40,
843 	SKU_KOREA		= 0x45,
844 	SKU_APAC		= 0x50,	/* Asia Pacific */
845 	SKU_APAC2		= 0x51,	/* Asia Pacific w/ DFS on mid-band */
846 	SKU_APAC3		= 0x5d,	/* Asia Pacific w/o ISM band */
847 	SKU_ROW			= 0x81,	/* China/Taiwan/Rest of World */
848 	SKU_NONE		= 0xf0,	/* "Region Free" */
849 	SKU_DEBUG		= 0x1ff,
850 
851 	/* NB: from here down private */
852 	SKU_SR9			= 0x0298, /* Ubiquiti SR9 (900MHz/GSM) */
853 	SKU_XR9			= 0x0299, /* Ubiquiti XR9 (900MHz/GSM) */
854 	SKU_GZ901		= 0x029a, /* Zcomax GZ-901 (900MHz/GSM) */
855 };
856 
857 /*
858  * Set regdomain code (IEEE SKU).
859  */
860 enum {
861 	DOMAIN_CODE_FCC		= 0x10,	/* USA */
862 	DOMAIN_CODE_IC		= 0x20,	/* Canda */
863 	DOMAIN_CODE_ETSI	= 0x30,	/* Europe */
864 	DOMAIN_CODE_SPAIN	= 0x31,	/* Spain */
865 	DOMAIN_CODE_FRANCE	= 0x32,	/* France */
866 	DOMAIN_CODE_ETSI_131	= 0x130, /* ETSI w/ 1.3.1 radar type */
867 	DOMAIN_CODE_MKK		= 0x40,	/* Japan */
868 	DOMAIN_CODE_MKK2	= 0x41,	/* Japan w/ 10MHz chan spacing */
869 	DOMAIN_CODE_DGT		= 0x80,	/* Taiwan */
870 	DOMAIN_CODE_AUS		= 0x81,	/* Australia */
871 };
872 
873 
874 #ifdef __cplusplus
875 }
876 #endif
877 
878 #endif /* _MWL_VAR_H */
879