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Searched refs:ldw (Results 1 – 24 of 24) sorted by relevance

/illumos-gate/usr/src/uts/common/io/nxge/npi/
H A Dnpi_fflp.c1483 tst1.bits.ldw.dat = data->bits.ldw.dat; in npi_fflp_fcram_err_data_test()
1560 cfg.bits.ldw.vpr0 + cfg.bits.ldw.vpr1; in npi_fflp_cfg_enet_vlan_table_assoc()
1572 cfg.bits.ldw.vpr0 + cfg.bits.ldw.vpr1; in npi_fflp_cfg_enet_vlan_table_assoc()
1585 cfg.bits.ldw.vpr2 + cfg.bits.ldw.vpr3; in npi_fflp_cfg_enet_vlan_table_assoc()
1598 cfg.bits.ldw.vpr2 + cfg.bits.ldw.vpr3; in npi_fflp_cfg_enet_vlan_table_assoc()
1687 cfg.bits.ldw.parity1++; in npi_fflp_cfg_enet_vlan_table_set_pri()
1689 cfg.bits.ldw.parity0++; in npi_fflp_cfg_enet_vlan_table_set_pri()
2975 p_err.bits.ldw.m_err = 0; in npi_fflp_vlan_error_clear()
2976 p_err.bits.ldw.err = 0; in npi_fflp_vlan_error_clear()
3000 p_err.bits.ldw.mult = 0; in npi_fflp_tcam_error_clear()
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H A Dnpi_rxdma.c383 cfg.bits.ldw.en = 1; in npi_rxdma_cfg_rdc_ctl()
408 cfg.bits.ldw.en = 0; in npi_rxdma_cfg_rdc_ctl()
431 cfg.bits.ldw.rst = 1; in npi_rxdma_cfg_rdc_ctl()
1430 wred_reg.bits.ldw.win = wred_params->bits.ldw.win; in npi_rxdma_cfg_wred_param()
1431 wred_reg.bits.ldw.thre = wred_params->bits.ldw.thre; in npi_rxdma_cfg_wred_param()
1432 wred_reg.bits.ldw.win_syn = wred_params->bits.ldw.win_syn; in npi_rxdma_cfg_wred_param()
1433 wred_reg.bits.ldw.thre_sync = wred_params->bits.ldw.thre_sync; in npi_rxdma_cfg_wred_param()
1640 hdptr->bits.ldw = hl_ptr.bits.ldw.head_l << 2; in npi_rxdma_rdc_rbr_head_get()
1691 tail_addr->bits.ldw = tl_ptr.bits.ldw.tlptr_l << 3; in npi_rxdma_rdc_rcr_tail_get()
1859 cs.bits.ldw.ptrread, cs.bits.ldw.pktread)); in npi_rxdma_rdc_rcr_read_update()
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H A Dnpi_zcp.c327 val.qw0.bits.ldw.buf_size = in npi_zcp_tt_static_entry()
332 val.qw0.bits.ldw.num_buf = sflow->qw0.bits.ldw.num_buf; in npi_zcp_tt_static_entry()
336 val.qw0.bits.ldw.ulp_end = sflow->qw0.bits.ldw.ulp_end; in npi_zcp_tt_static_entry()
340 val.qw1.bits.ldw.ulp_end = sflow->qw1.bits.ldw.ulp_end; in npi_zcp_tt_static_entry()
354 val.qw1.bits.ldw.tmode = sflow->qw1.bits.ldw.tmode; in npi_zcp_tt_static_entry()
358 val.qw1.bits.ldw.skip = sflow->qw1.bits.ldw.skip; in npi_zcp_tt_static_entry()
377 val.qw2.bits.ldw.busy = sflow->qw2.bits.ldw.busy; in npi_zcp_tt_static_entry()
381 val.qw3.bits.ldw.toq = sflow->qw3.bits.ldw.toq; in npi_zcp_tt_static_entry()
482 val.qw3.bits.ldw.err_stat = in npi_zcp_tt_dynamic_entry()
487 val.qw3.bits.ldw.wr_ptr = dflow->qw3.bits.ldw.wr_ptr; in npi_zcp_tt_dynamic_entry()
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H A Dnpi_vir.c304 sr.bits.ldw.tas = 0; in npi_dev_func_sr_init()
311 sr.bits.ldw.sr)); in npi_dev_func_sr_init()
316 sr.bits.ldw)); in npi_dev_func_sr_init()
422 if (sr.bits.ldw.funcid == NPI_GET_LOCK_OWNER(sr.bits.ldw.sr)) { in npi_dev_func_sr_lock_free()
473 sr.bits.ldw.tas = 0; in npi_dev_func_sr_funcid_get()
507 sr.bits.ldw.tas = 0; in npi_dev_func_sr_sr_raw_get()
547 sr.bits.ldw.tas = 0; in npi_dev_func_sr_sr_get()
618 if (sr.bits.ldw.funcid == NPI_GET_LOCK_OWNER(sr.bits.ldw.sr)) { in npi_dev_func_sr_sr_set_only()
652 sr.bits.ldw.tas = 0; in npi_dev_func_sr_busy()
686 sr.bits.ldw.tas = 0; in npi_dev_func_sr_tas_get()
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H A Dnpi_txdma.c258 mode32.bits.ldw.mode32 = 1; in npi_txdma_mode32_set()
347 vld.bits.ldw.func, in npi_txdma_log_page_set()
932 cs.bits.ldw.rst = 1; in npi_txdma_channel_control()
947 cs.bits.ldw.rst = 1; in npi_txdma_channel_control()
981 cs.bits.ldw.mk = 1; in npi_txdma_channel_control()
991 cs.bits.ldw.mb = 1; in npi_txdma_channel_control()
1814 ring_errlog_p->logh.bits.ldw.err = logh.bits.ldw.err; in npi_txdma_ring_error_get()
1815 ring_errlog_p->logh.bits.ldw.merr = logh.bits.ldw.merr; in npi_txdma_ring_error_get()
1816 ring_errlog_p->logh.bits.ldw.errcode = logh.bits.ldw.errcode; in npi_txdma_ring_error_get()
1817 ring_errlog_p->logh.bits.ldw.err_addr = logh.bits.ldw.err_addr; in npi_txdma_ring_error_get()
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H A Dnpi_txc.c432 cntl.bits.ldw.txc_enabled = 1; in npi_txc_global_enable()
459 cntl.bits.ldw.txc_enabled = 0; in npi_txc_global_disable()
870 if ((ecc.bits.ldw.correct_error) || (ecc.bits.ldw.uncorrect_error)) { in npi_txc_ro_states_get()
887 ecc.bits.ldw.ecc_address = 0; in npi_txc_ro_states_get()
888 ecc.bits.ldw.correct_error = 0; in npi_txc_ro_states_get()
890 ecc.bits.ldw.clr_st = 1; in npi_txc_ro_states_get()
910 ctl.bits.ldw.clr_fail_state = 1; in npi_txc_ro_states_get()
962 if ((ecc.bits.ldw.correct_error) || (ecc.bits.ldw.uncorrect_error)) { in npi_txc_sf_states_get()
973 ecc.bits.ldw.ecc_address = 0; in npi_txc_sf_states_get()
974 ecc.bits.ldw.correct_error = 0; in npi_txc_sf_states_get()
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H A Dnpi_rxdma.h190 uint32_t ldw; member
192 uint32_t ldw;
H A Dnpi_zcp.h117 } while ((ram_ctl.bits.ldw.busy != 0) && (cnt > 0));\
/illumos-gate/usr/src/uts/common/io/nxge/
H A Dnxge_txc.c346 if (istatus.bits.ldw.port0_int_status) { in nxge_txc_handle_sys_errors()
353 if (istatus.bits.ldw.port1_int_status) { in nxge_txc_handle_sys_errors()
360 if (istatus.bits.ldw.port2_int_status) { in nxge_txc_handle_sys_errors()
367 if (istatus.bits.ldw.port3_int_status) { in nxge_txc_handle_sys_errors()
532 ro_ecc_ctl.bits.ldw.all_pkts = 1; in nxge_txc_inject_err()
533 ro_ecc_ctl.bits.ldw.second_line_pkt = 1; in nxge_txc_inject_err()
535 ro_ecc_ctl.bits.ldw.single_bit_err = 1; in nxge_txc_inject_err()
537 ro_ecc_ctl.bits.ldw.double_bit_err = 1; in nxge_txc_inject_err()
546 sf_ecc_ctl.bits.ldw.all_pkts = 1; in nxge_txc_inject_err()
547 sf_ecc_ctl.bits.ldw.second_line_pkt = 1; in nxge_txc_inject_err()
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H A Dnxge_zcp.c334 zcps.bits.ldw.rrfifo_urun = 1; in nxge_zcp_inject_err()
338 zcps.bits.ldw.stat_tbl_perr = 1; in nxge_zcp_inject_err()
340 zcps.bits.ldw.dyn_tbl_perr = 1; in nxge_zcp_inject_err()
342 zcps.bits.ldw.buf_tbl_perr = 1; in nxge_zcp_inject_err()
346 zcps.bits.ldw.cfifo_ecc0 = 1; in nxge_zcp_inject_err()
349 zcps.bits.ldw.cfifo_ecc1 = 1; in nxge_zcp_inject_err()
352 zcps.bits.ldw.cfifo_ecc2 = 1; in nxge_zcp_inject_err()
355 zcps.bits.ldw.cfifo_ecc3 = 1; in nxge_zcp_inject_err()
363 zcps.bits.ldw.rrfifo_orun = 1; in nxge_zcp_inject_err()
365 zcps.bits.ldw.buf_overflow = 1; in nxge_zcp_inject_err()
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H A Dnxge_txdma.c1180 if (!rs && cs.bits.ldw.mk) { in nxge_tx_intr()
2441 tx_cs_p->bits.ldw.rst = 1; in nxge_map_txdma_channel_cfg_ring()
2468 mboxh_p->bits.ldw.mbaddr, mboxl_p->bits.ldw.mbaddr)); in nxge_map_txdma_channel_cfg_ring()
3174 if ((cs.bits.ldw.pkt_size_err) || (cs.bits.ldw.pref_buf_par_err) || in nxge_tx_err_evnts()
3175 (cs.bits.ldw.nack_pref) || (cs.bits.ldw.nack_pkt_rd) || in nxge_tx_err_evnts()
3176 (cs.bits.ldw.conf_part_err) || (cs.bits.ldw.pkt_prt_err)) { in nxge_tx_err_evnts()
3182 if (cs.bits.ldw.mbox_err) { in nxge_tx_err_evnts()
3223 if (cs.bits.ldw.nack_pref) { in nxge_tx_err_evnts()
3232 if (cs.bits.ldw.nack_pkt_rd) { in nxge_tx_err_evnts()
3658 tdi.bits.ldw.mbox_err = 1; in nxge_txdma_inject_err()
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H A Dnxge_fm.c801 bits.ldw.ecc_address, in nxge_fm_ereport()
804 bits.ldw.ro_ecc_data0, in nxge_fm_ereport()
807 bits.ldw.ro_ecc_data1, in nxge_fm_ereport()
810 bits.ldw.ro_ecc_data2, in nxge_fm_ereport()
813 bits.ldw.ro_ecc_data3, in nxge_fm_ereport()
816 bits.ldw.ro_ecc_data4, in nxge_fm_ereport()
848 bits.ldw.ecc_address, in nxge_fm_ereport()
851 bits.ldw.sf_ecc_data0, in nxge_fm_ereport()
854 bits.ldw.sf_ecc_data1, in nxge_fm_ereport()
857 bits.ldw.sf_ecc_data2, in nxge_fm_ereport()
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H A Dnxge_rxdma.c1824 mgm.bits.ldw.arm = 1; in nxge_rx_intr()
1888 mgm.bits.ldw.arm = 0; in nxge_rx_intr()
1906 mgm.bits.ldw.arm = 1; in nxge_rx_intr()
2800 cs.bits.ldw.pktread = 0; in nxge_disable_poll()
2801 cs.bits.ldw.ptrread = 0; in nxge_disable_poll()
2829 mgm.bits.ldw.arm = 1; in nxge_disable_poll()
3425 rcfgb_p->bits.ldw.vld0 = 1; in nxge_map_rxdma_channel_cfg_ring()
3427 rcfgb_p->bits.ldw.vld1 = 1; in nxge_map_rxdma_channel_cfg_ring()
3429 rcfgb_p->bits.ldw.vld2 = 1; in nxge_map_rxdma_channel_cfg_ring()
3631 cfgb_p->bits.ldw.entout = 1; in nxge_map_rxdma_channel_cfg_ring()
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H A Dnxge_fzc.c355 red.bits.ldw.win = RXDMA_RED_WINDOW_DEFAULT; in nxge_init_fzc_rdc()
356 red.bits.ldw.thre = in nxge_init_fzc_rdc()
359 red.bits.ldw.thre_sync = in nxge_init_fzc_rdc()
364 red.bits.ldw.thre_sync, in nxge_init_fzc_rdc()
365 red.bits.ldw.thre_sync)); in nxge_init_fzc_rdc()
549 cfg.valid = rbrp->page_valid.bits.ldw.page0; in nxge_init_fzc_rxdma_channel_pages()
563 cfg.valid = rbrp->page_valid.bits.ldw.page1; in nxge_init_fzc_rxdma_channel_pages()
575 rbrp->page_hdl.bits.ldw.handle); in nxge_init_fzc_rxdma_channel_pages()
600 red.bits.ldw.win = RXDMA_RED_WINDOW_DEFAULT; in nxge_init_fzc_rxdma_channel_red()
607 red.bits.ldw.thre_sync, in nxge_init_fzc_rxdma_channel_red()
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H A Dnxge_fflp.c2153 if (vlan_err.bits.ldw.m_err || vlan_err.bits.ldw.err) { in nxge_fflp_handle_sys_errors()
2157 portn, vlan_err.bits.ldw.addr, in nxge_fflp_handle_sys_errors()
2158 vlan_err.bits.ldw.data)); in nxge_fflp_handle_sys_errors()
2161 if (vlan_err.bits.ldw.m_err) { in nxge_fflp_handle_sys_errors()
2172 if (tcam_err.bits.ldw.err) { in nxge_fflp_handle_sys_errors()
2178 tcam_err.bits.ldw.syndrome)); in nxge_fflp_handle_sys_errors()
2185 tcam_err.bits.ldw.syndrome)); in nxge_fflp_handle_sys_errors()
2189 if (tcam_err.bits.ldw.mult) { in nxge_fflp_handle_sys_errors()
2228 if (fcram1_err.bits.ldw.ecc_err) { in nxge_fflp_handle_sys_errors()
2244 fcram2_err.bits.ldw.h1, in nxge_fflp_handle_sys_errors()
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H A Dnxge_hw.c432 if (estat.bits.ldw.smx) { in nxge_syserr_intr()
436 } else if (estat.bits.ldw.mac) { in nxge_syserr_intr()
445 } else if (estat.bits.ldw.ipp) { in nxge_syserr_intr()
449 } else if (estat.bits.ldw.zcp) { in nxge_syserr_intr()
454 } else if (estat.bits.ldw.tdmc) { in nxge_syserr_intr()
462 } else if (estat.bits.ldw.rdmc) { in nxge_syserr_intr()
467 } else if (estat.bits.ldw.txc) { in nxge_syserr_intr()
471 } else if ((nxgep->niu_type != N2_NIU) && estat.bits.ldw.peu) { in nxge_syserr_intr()
475 } else if (estat.bits.ldw.meta1) { in nxge_syserr_intr()
479 } else if (estat.bits.ldw.meta2) { in nxge_syserr_intr()
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H A Dnxge_intr.c1094 mgm.bits.ldw.arm = 1; in nxge_hio_ldgimgn()
1095 mgm.bits.ldw.timer = group->ldg_timer; in nxge_hio_ldgimgn()
1097 mgm.bits.ldw.arm = 0; in nxge_hio_ldgimgn()
1098 mgm.bits.ldw.timer = 0; in nxge_hio_ldgimgn()
H A Dnxge_send.c746 sop_tx_desc_p->bits.ldw.sad = dma_ioaddr & 0xffffffff; in nxge_start()
755 tmp_desc_p->bits.ldw.sad = dma_ioaddr & 0xffffffff; in nxge_start()
989 kick.bits.ldw.wrap = in nxge_start()
991 kick.bits.ldw.tail = in nxge_start()
1034 kick.bits.ldw.wrap = tx_ring_p->wr_index_wrap; in nxge_start()
1035 kick.bits.ldw.tail = (uint16_t)tx_ring_p->wr_index; in nxge_start()
/illumos-gate/usr/src/uts/common/sys/nxge/
H A Dnxge_hw.h104 } ldw; member
132 } ldw; member
181 } ldw; member
230 } ldw; member
291 } ldw; member
329 } ldw; member
362 } ldw; member
389 } ldw; member
428 } ldw; member
481 } ldw; member
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H A Dnxge_txc_hw.h55 } ldw; member
76 } ldw; member
115 } ldw; member
145 } ldw; member
180 } ldw; member
208 } ldw; member
233 } ldw; member
260 } ldw; member
300 } ldw; member
327 } ldw; member
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H A Dnxge_zcp_hw.h95 } ldw; member
140 } ldw; member
203 } ldw; member
247 } ldw; member
268 } ldw; member
322 } ldw; member
353 } ldw; member
630 } ldw; member
668 } ldw; member
687 } ldw; member
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H A Dnxge_txdma_hw.h85 } ldw; member
136 } ldw; member
218 } ldw; member
259 } ldw; member
288 } ldw; member
357 } ldw; member
457 } ldw; member
497 } ldw; member
524 } ldw; member
549 } ldw; member
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H A Dnxge_rxdma_hw.h58 } ldw; member
97 } ldw; member
118 } ldw; member
151 } ldw; member
185 } ldw; member
218 } ldw; member
278 } ldw; member
343 } ldw; member
388 } ldw; member
428 } ldw; member
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H A Dnxge_fflp_hw.h97 } ldw; member
127 } ldw; member
164 } ldw; member
264 } ldw; member
324 } ldw; member
367 } ldw; member
445 } ldw; member
477 } ldw; member
516 } ldw; member
543 } ldw; member
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