1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at
9  * http://www.opensource.org/licenses/cddl1.txt.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2004-2011 Emulex. All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _EMLXS_MENLO_H
28 #define	_EMLXS_MENLO_H
29 
30 #ifdef	__cplusplus
31 extern "C" {
32 #endif
33 
34 #ifdef MENLO_SUPPORT
35 
36 /*
37  * COMMANDS
38  */
39 
40 typedef struct menlo_init_cmd
41 {
42 	uint32_t code;		/* Command code = MENLO_CMD_INITIALIZE */
43 	uint32_t bb_credit;	/* Menlo FC BB Credit */
44 	uint32_t frame_size;	/* Menlo FC receive frame size */
45 
46 } menlo_init_cmd_t;
47 
48 
49 typedef struct menlo_fw_download_cmd
50 {
51 	uint32_t code;		/* Command code = MENLO_CMD_FW_DOWNLOAD */
52 	uint32_t length;	/* Firmware image length in bytes */
53 				/* (4 byte aligned) */
54 	uint32_t type;		/* Firmware image type */
55 
56 #define	MENLO_IMAGE_TYPE_OP			1
57 #define	MENLO_IMAGE_TYPE_DIAG			2
58 
59 /* Followed by length bytes of firmware image */
60 /* Firmware image will be in Little Endian format */
61 
62 } menlo_fw_download_cmd_t;
63 
64 
65 typedef struct menlo_memory_cmd
66 {
67 	uint32_t code; 		/* Command code */
68 	uint32_t address;	/* Menlo memory address */
69 	uint32_t length;	/* Number of words */
70 
71 } menlo_memory_cmd_t;
72 
73 
74 typedef struct menlo_fte_insert_cmd
75 {
76 	uint32_t code;		/* Command code = MENLO_CMD_FTE_INSERT */
77 	uint32_t mask;		/* mask = True or False */
78 
79 #define	MENLO_SRC_MASK_FALSE	0
80 #define	MENLO_SRC_MASK_TRUE		1
81 
82 	uint32_t fcid;		/* FCID of remote port */
83 	uint8_t wwpn[8];	/* WWPN of remote port */
84 
85 } menlo_fte_insert_cmd_t;
86 
87 
88 typedef struct menlo_fte_delete_cmd
89 {
90 	uint32_t code;		/* Command code = MENLO_CMD_FTE_DELETE */
91 	uint32_t fcid;		/* FCID of remote port */
92 	uint8_t wwpn[8];	/* WWPN of remote port */
93 
94 } menlo_fte_delete_cmd_t;
95 
96 
97 typedef struct menlo_get_cmd
98 {
99 	uint32_t code;		/* Command code */
100 	uint32_t context;	/* Context */
101 
102 /* MENLO_CMD_GET_PORT_STATS */
103 #define	MENLO_PORT_ETH0		0
104 #define	MENLO_PORT_ETH1		1
105 #define	MENLO_PORT_NSL0		2
106 #define	MENLO_PORT_NSL1		3
107 #define	MENLO_PORT_FC0		4
108 #define	MENLO_PORT_FC1		5
109 
110 /* MENLO_CMD_GET_LIF_STATS */
111 #define	MENLO_LIF_ETH0	0
112 #define	MENLO_LIF_ETH1	1
113 #define	MENLO_LIF_FC0	2
114 #define	MENLO_LIF_FC1	3
115 
116 /* MENLO_CMD_GET_LB_MODE */
117 #define	MENLO_NSL_PORT_ID_0			0
118 #define	MENLO_NSL_PORT_ID_1			1
119 
120 	uint32_t length;	/* Max response length */
121 
122 } menlo_get_cmd_t;
123 
124 
125 typedef struct menlo_set_cmd
126 {
127 	uint32_t code; 		/* Command code = MENLO_CMD_SET_PAUSE */
128 	uint32_t value1;	/* value1 */
129 	uint32_t value2;	/* value2 */
130 
131 /* MENLO_CMD_SET_PAUSE values */
132 #define	MENLO_PAUSE_TYPE_SP				1
133 #define	MENLO_PAUSE_TYPE_PPP			2
134 
135 /* PPP Priority bits	:  [ ][ ][ ][ ][X][ ][ ][ ] */
136 /*		COS	:   7  6  5  4  3  2  1  0  */
137 #define	MENLO_PPP_COS0				0x01
138 #define	MENLO_PPP_COS1				0x02
139 #define	MENLO_PPP_COS2				0x04
140 #define	MENLO_PPP_COS3				0x08
141 #define	MENLO_PPP_COS4				0x10
142 #define	MENLO_PPP_COS5				0x20
143 #define	MENLO_PPP_COS6				0x40
144 #define	MENLO_PPP_COS7				0x80
145 
146 /* MENLO_CMD_SET_FCOE_COS values */
147 #define	MENLO_FCOE_COS				3
148 
149 /* MENLO_CMD_SET_UIF_PORT_TYPE values */
150 #define	MENLO_PORT_TYPE_ACCESS			1
151 #define	MENLO_PORT_TYPE_TRUNK			2
152 
153 /* MENLO_CMD_SET_MODE values */
154 #define	MENLO_MAINTENANCE_MODE_DISABLE		0
155 #define	MENLO_MAINTENANCE_MODE_ENABLE		1
156 
157 } menlo_set_cmd_t;
158 
159 
160 typedef struct menlo_loopback_cmd
161 {
162 	uint32_t code; 		/* Command code = MENLO_CMD_LOOPBACK */
163 	uint32_t context;	/* context = NSL port 0 or 1 */
164 
165 #define	MENLO_NSL_PORT_ID_0			0
166 #define	MENLO_NSL_PORT_ID_1			1
167 
168 	uint32_t type;		/* type  = loopback mode enable or disable */
169 
170 #define	MENLO_LOOPBACK_DISABLE		0
171 #define	MENLO_LOOPBACK_ENABLE		1
172 
173 } menlo_loopback_cmd_t;
174 
175 
176 typedef struct menlo_reset_cmd
177 {
178 	uint32_t code; 		/* Command code = MENLO_CMD_RESET */
179 	uint32_t firmware;
180 
181 #define	MENLO_FW_OPERATIONAL		0
182 #define	MENLO_FW_GOLDEN				1
183 
184 } menlo_reset_cmd_t;
185 
186 typedef struct menlo_fru_data_cmd
187 {
188 	uint32_t code;		/* Response code */
189 	uint8_t mac0[8];	/* MAC address of port 0 */
190 	uint8_t mac1[8];	/* MAC address of port 1 */
191 	uint32_t flags;
192 
193 /* Valid flags */
194 #define	MENLO_FLAG_SINGLE_CHANNEL	0x00000001
195 #define	MENLO_FLAG_DUAL_CHANNEL		0x00000002
196 
197 } menlo_fru_data_cmd_t;
198 
199 
200 typedef struct menlo_diag_cmd
201 {
202 	uint32_t code;		/* Response code */
203 	uint32_t loop_count;	/* loop_count = 0 indicates loop forever */
204 				/* loop_count > 0 indicates number of test */
205 				/* iterations */
206 				/* NOTE : one test iteration takes */
207 				/* approximately 2-3 seconds */
208 	uint32_t test_bitmap;   /* Each bit represents a separate test to be */
209 				/* performed */
210 				/* test_bitmap = 0 will result in a */
211 				/* MENLO_ERR_INVALID_FLAG error */
212 } menlo_diag_cmd_t;
213 
214 
215 /* Hornet 2 */
216 
217 #define	MAX_SUPPORTED_VLANS	4
218 
219 typedef struct fip_params
220 {
221 	uint8_t sw_name[8]; /* Switch name */
222 	uint8_t fabric_name[8]; /* Fabric name */
223 	uint8_t sup_addr_mode;  /* Support addressing modes */
224 
225 /* FCoE Addressing Mode */
226 #define	SPMA_ADDR_MODE	1
227 #define	FPMA_ADDR_MODE	2
228 
229 	uint8_t	 pref_addr_mode; /* Preferred addressing modes */
230 	uint16_t fcf_disc_tov;   /* Discovery tmo period (multiple 500ms) */
231 	uint16_t vlan_id[MAX_SUPPORTED_VLANS]; /* VLAN list */
232 
233 } fip_params_t;
234 
235 typedef struct non_fip_params
236 {
237 	uint32_t fc_map;  /* Configured FC_MAP */
238 
239 } non_fip_params_t;
240 
241 typedef union menlo_fcoe_params
242 {
243 	fip_params_t fip;		/* FIP specific parameters */
244 	non_fip_params_t non_fip;	/* Non-FIP specific parameters */
245 } menlo_fcoe_params_t;
246 
247 typedef struct menlo_set_fcoe_params_cmd
248 {
249 	uint32_t code; /* Command code=MENLO_CMD_SET_FCOE_PARAMS */
250 	uint32_t fcoe_mode; /* FIP or Non-FIP */
251 
252 /* FCoE Operation Mode */
253 #define	FCOE_MODE_NON_FIP	0
254 #define	FCOE_MODE_FIP		1
255 
256 	uint32_t lport_id; /* Logical port identification */
257 	menlo_fcoe_params_t params; /* Specific FCoE parameters */
258 
259 } menlo_set_fcoe_params_cmd_t;
260 
261 
262 typedef	struct set_facl_cmd
263 {
264 	uint32_t code;  /* Command code = MENLO_CMD_SET_FACL */
265 	uint32_t lport_id; /* Logical port identification */
266 	uint32_t num_acls; /* Number of ACL entries */
267 	uint32_t facl_list; /* List of returned Fabric ACL, facl_t */
268 } set_facl_cmd_t;
269 
270 typedef	struct facl
271 {
272 	uint8_t fabric_name[8]; /* Fabric name */
273 	uint8_t sw_name[8];  /* Switch name */
274 	uint32_t acc_ctrl;  /* PERMIT or DENY */
275 } facl_t;
276 
277 typedef	struct fcf_id
278 {
279 	uint8_t sw_name[8];  /* Switch name */
280 	uint8_t fabric_name[8];	 /* Fabric name */
281 
282 } fcf_id_t;
283 
284 typedef	struct create_vl_cmd
285 {
286 	uint32_t code;  /* Command code = MENLO_CMD_CREATE_VL */
287 	uint32_t lport_id; /* Logical port identification */
288 	fcf_id_t fcf;  /* Specific FCF */
289 
290 } create_vl_cmd_t;
291 
292 typedef struct delete_vl_cmd
293 {
294 	uint32_t code;  /* Command code = MENLO_CMD_CREATE_VL */
295 	uint32_t vl_handle; /* Handle of created VL */
296 
297 } delete_vl_cmd_t;
298 
299 #define	MAX_GROUPS 8 /* Max supported by hardware */
300 
301 typedef struct menlo_pg_info
302 {
303 	uint32_t num_pg;    /* Number of PGs specified */
304 	uint8_t pg_ids[MAX_GROUPS]; /* PG membership bitmaps */
305 	uint8_t pg_bw[MAX_GROUPS]; /* BW for each PG in 10% gran. */
306 
307 } menlo_pg_info_t;
308 
309 typedef struct menlo_set_pg_info_cmd
310 {
311 	uint32_t  code;  /* Command code = MENLO_CMD_SET_PG */
312 	menlo_pg_info_t pg_info; /* PG information */
313 
314 } menlo_set_pg_info_cmd_t;
315 
316 
317 typedef struct menlo_set_host_eth_pfc_flag
318 {
319 	uint32_t code; /* Command code=MENLO_CMD_SET_HOST_ETH_PFC_FLAG */
320 	uint32_t host_pfc_enable; /* 1 = PFC on Host if enabled */
321 
322 /* Host PFC Flag Definitions */
323 #define	MENLO_HOST_PFC_DISABLE	0x0
324 #define	MENLO_HOST_PFC_ENABLE	0x1
325 
326 } menlo_set_host_eth_pfc_flag_t;
327 
328 
329 
330 typedef union menlo_cmd
331 {
332 	uint32_t			word[5];
333 	uint32_t			code; 		/* Command code */
334 
335 /* Command codes */
336 #define	MENLO_CMD_INITIALIZE		0x00000001
337 #define	MENLO_CMD_FW_DOWNLOAD		0x00000002
338 #define	MENLO_CMD_READ_MEMORY		0x00000003
339 #define	MENLO_CMD_WRITE_MEMORY		0x00000004
340 #define	MENLO_CMD_FTE_INSERT		0x00000005
341 #define	MENLO_CMD_FTE_DELETE		0x00000006
342 
343 #define	MENLO_CMD_GET_INIT 		0x00000007
344 #define	MENLO_CMD_GET_CONFIG		0x00000008
345 #define	MENLO_CMD_GET_PORT_STATS	0x00000009
346 #define	MENLO_CMD_GET_LIF_STATS		0x0000000A
347 #define	MENLO_CMD_GET_ASIC_STATS	0x0000000B
348 #define	MENLO_CMD_GET_LOG_CONFIG	0x0000000C
349 #define	MENLO_CMD_GET_LOG_DATA		0x0000000D
350 #define	MENLO_CMD_GET_PANIC_LOG		0x0000000E
351 #define	MENLO_CMD_GET_LB_MODE		0x0000000F
352 
353 #define	MENLO_CMD_SET_PAUSE		0x00000010
354 #define	MENLO_CMD_SET_FCOE_COS		0x00000011
355 #define	MENLO_CMD_SET_UIF_PORT_TYPE	0x00000012
356 
357 #define	MENLO_CMD_DIAGNOSTICS		0x00000013
358 #define	MENLO_CMD_LOOPBACK		0x00000014
359 #define	MENLO_CMD_GET_FTABLE		0x00000015
360 #define	MENLO_CMD_GET_SFP_DATA		0x00000016
361 #define	MENLO_CMD_SET_FRU_DATA		0x00000017
362 #define	MENLO_CMD_GET_FRU_DATA		0x00000018
363 #define	MENLO_CMD_SET_FCOE_FORMAT	0x00000019
364 #define	MENLO_CMD_GET_DIAG_LOG		0x00000020
365 #define	MENLO_CMD_PANIC			0x00000021
366 #define	MENLO_CMD_SET_FCOE_PARAMS	0x00000022
367 #define	MENLO_CMD_GET_FCOE_PARAMS	0x00000023
368 #define	MENLO_CMD_GET_FCF_LIST		0x00000024
369 #define	MENLO_CMD_SET_FACL		0x00000025
370 #define	MENLO_CMD_GET_FACL		0x00000026
371 #define	MENLO_CMD_CREATE_VL		0x00000027
372 #define	MENLO_CMD_DELETE_VL		0x00000028
373 #define	MENLO_CMD_SET_PG		0x00000029
374 #define	MENLO_CMD_GET_PG		0x0000002A
375 #define	MENLO_CMD_SET_HOST_ETH_PFC_FLAG	0x0000002B
376 #define	MENLO_CMD_GET_HOST_ETH_PFC_FLAG	0x0000002C
377 #define	MENLO_CMD_GET_DCBX_MODE		0x0000002D
378 
379 
380 /* Zephyr specific Menlo commands */
381 #define	MENLO_CMD_RESET			0x80000001
382 #define	MENLO_CMD_SET_MODE		0x80000002
383 
384 	menlo_init_cmd_t		init;
385 	menlo_fw_download_cmd_t		fw;
386 	menlo_memory_cmd_t		mem;
387 	menlo_fte_insert_cmd_t		fte_insert;
388 	menlo_fte_delete_cmd_t		fte_delete;
389 	menlo_get_cmd_t			get;
390 	menlo_set_cmd_t			set;
391 	menlo_loopback_cmd_t		lb;
392 	menlo_reset_cmd_t		reset;
393 	menlo_fru_data_cmd_t		fru;
394 	menlo_diag_cmd_t		diag;
395 	menlo_set_host_eth_pfc_flag_t	pfc;
396 } menlo_cmd_t;
397 
398 
399 /*
400  * RESPONSES
401  */
402 
403 typedef struct menlo_init_rsp
404 {
405 	uint32_t code;
406 	uint32_t bb_credit;	/* Menlo FC BB Credit */
407 	uint32_t frame_size;	/* Menlo FC receive frame size */
408 	uint32_t fw_version;	/* Menlo firmware version   */
409 	uint32_t reset_status;	/* Reason for previous reset */
410 
411 #define	MENLO_RESET_STATUS_NORMAL		0
412 #define	MENLO_RESET_STATUS_PANIC		1
413 
414 	uint32_t maint_status;	/* Menlo Maintenance Mode status at link up */
415 
416 #define	MENLO_MAINTENANCE_MODE_DISABLE	0
417 #define	MENLO_MAINTENANCE_MODE_ENABLE	1
418 
419 	uint32_t fw_type;
420 
421 #define	MENLO_FW_TYPE_OPERATIONAL	0xABCD0001
422 #define	MENLO_FW_TYPE_GOLDEN		0xABCD0002
423 #define	MENLO_FW_TYPE_DIAG		0xABCD0003
424 
425 	uint32_t fru_data_valid;  /* 0=invalid, 1=valid */
426 } menlo_init_rsp_t;
427 
428 
429 #define	MENLO_MAX_FC_PORTS		2
430 #define	MENLO_MAX_UIF_PORTS		2
431 
432 typedef struct menlo_get_config_rsp
433 {
434 	uint32_t code;
435 
436 	uint32_t pause_type[MENLO_MAX_UIF_PORTS];
437 	uint32_t priority[MENLO_MAX_UIF_PORTS];
438 	uint32_t fcoe_cos[MENLO_MAX_FC_PORTS];
439 	uint32_t uif_port_type[MENLO_MAX_UIF_PORTS];
440 
441 	uint32_t log_cfg_size;		/* Size of log config region. */
442 					/* Needed for */
443 					/* MENLO_CMD_GET_LOG_CONFIG */
444 	uint32_t panic_log_size;	/* Size of panic log region. */
445 					/* Needed for MENLO_CMD_GET_PANIC_LOG */
446 
447 	uint32_t dcx_present[MENLO_MAX_UIF_PORTS];
448 
449 	uint32_t current_pause_type[MENLO_MAX_UIF_PORTS];
450 	uint32_t current_priority[MENLO_MAX_UIF_PORTS];
451 	uint32_t current_fcoe_cos[MENLO_MAX_FC_PORTS];
452 	uint32_t current_uif_port_type[MENLO_MAX_UIF_PORTS];
453 
454 	uint32_t fcoe_format;		/* Bit field - single bit will be set */
455 					/* (See below) */
456 	uint32_t current_fcoe_format;	/* Bit field - single bit will be set */
457 					/*  (See below) */
458 	uint32_t supported_fcoe_format;	/* Bit field - multiple bits may be */
459 					/* set (See below) */
460 
461 #define	FCOE_FRAME_FORMAT_P0		0x00010000 /* Pre-T11 format */
462 #define	FCOE_FRAME_FORMAT_T0		0x00000001 /* T11 format Rev 0 */
463 #define	FCOE_FRAME_FORMAT_T1		0x00000002
464 #define	FCOE_FRAME_FORMAT_T2		0x00000004
465 #define	FCOE_FRAME_FORMAT_T3		0x00000008
466 #define	FCOE_FRAME_FORMAT_T4		0x00000010
467 #define	FCOE_FRAME_FORMAT_T5		0x00000020
468 #define	FCOE_FRAME_FORMAT_T6		0x00000040
469 #define	FCOE_FRAME_FORMAT_T7		0x00000080
470 #define	FCOE_FRAME_FORMAT_T8		0x00000100
471 #define	FCOE_FRAME_FORMAT_T9		0x00000200
472 #define	FCOE_FRAME_FORMAT_T10		0x00000400
473 #define	FCOE_FRAME_FORMAT_T11		0x00000800
474 #define	FCOE_FRAME_FORMAT_T12		0x00001000
475 #define	FCOE_FRAME_FORMAT_T13		0x00002000
476 #define	FCOE_FRAME_FORMAT_T14		0x00004000
477 #define	FCOE_FRAME_FORMAT_T15		0x00008000
478 } menlo_get_config_rsp_t;
479 
480 
481 typedef struct menlo_fc_stats_rsp
482 {
483 	uint32_t code;
484 
485 	uint64_t rx_class_2_frames;
486 	uint64_t rx_class_3_frames;
487 	uint64_t rx_class_F_frames;
488 	uint64_t rx_class_other_frames;
489 
490 	uint64_t tx_class_2_frames;
491 	uint64_t tx_class_3_frames;
492 	uint64_t tx_class_F_frames;
493 	uint64_t tx_class_other_frames;
494 
495 	uint64_t rx_class_2_words;
496 	uint64_t rx_class_3_words;
497 	uint64_t rx_class_F_words;
498 	uint64_t rx_class_other_words;
499 
500 	uint64_t tx_class_2_words;
501 	uint64_t tx_class_3_words;
502 	uint64_t tx_class_F_words;
503 	uint64_t tx_class_other_words;
504 
505 	uint64_t rx_class_2_frames_bad;
506 	uint64_t rx_class_3_frames_bad;
507 	uint64_t rx_class_F_frames_bad;
508 	uint64_t rx_class_other_frames_bad;
509 
510 	uint64_t tx_class_2_frames_bad;
511 	uint64_t tx_class_3_frames_bad;
512 	uint64_t tx_class_F_frames_bad;
513 	uint64_t tx_class_other_frames_bad;
514 } menlo_fc_stats_rsp_t;
515 
516 
517 typedef struct menlo_network_stats_rsp
518 {
519 	uint32_t code;
520 
521 	uint64_t tx_pkt_lt64;
522 	uint64_t tx_pkt_64;
523 	uint64_t tx_pkt_65;
524 	uint64_t tx_pkt_128;
525 	uint64_t tx_pkt_256;
526 	uint64_t tx_pkt_512;
527 	uint64_t tx_pkt_1024;
528 	uint64_t tx_pkt_1519;
529 	uint64_t tx_pkt_2048;
530 	uint64_t tx_pkt_4096;
531 	uint64_t tx_pkt_8192;
532 	uint64_t tx_pkt_gt9216;
533 	uint64_t tx_pkt_total;
534 	uint64_t tx_octet_sok;
535 	uint64_t tx_pkt_ok;
536 	uint64_t tx_ucast;
537 	uint64_t tx_mcast;
538 	uint64_t tx_bcast;
539 	uint64_t tx_vlan;
540 	uint64_t tx_pause;
541 	uint64_t tx_priority_pause;
542 	uint64_t tx_frame_error;
543 
544 	uint64_t rx_pkt_lt64;
545 	uint64_t rx_pkt_64;
546 	uint64_t rx_pkt_65;
547 	uint64_t rx_pkt_128;
548 	uint64_t rx_pkt_256;
549 	uint64_t rx_pkt_512;
550 	uint64_t rx_pkt_1024;
551 	uint64_t rx_pkt_1519;
552 	uint64_t rx_pkt_2048;
553 	uint64_t rx_pkt_4096;
554 	uint64_t rx_pkt_8192;
555 	uint64_t rx_pkt_gt9216;
556 	uint64_t rx_pkt_total;
557 	uint64_t rx_octet_sok;
558 	uint64_t rx_pkt_ok;
559 	uint64_t rx_ucast;
560 	uint64_t rx_mcast;
561 	uint64_t rx_bcast;
562 	uint64_t rx_vlan;
563 	uint64_t rx_oversize;
564 	uint64_t rx_toolong;
565 	uint64_t rx_discard;
566 	uint64_t rx_undersize;
567 	uint64_t rx_fragment;
568 	uint64_t rx_crc_err;
569 	uint64_t rx_inrange_err;
570 	uint64_t rx_jabber;
571 	uint64_t rx_pause;
572 	uint64_t rx_priority_pause;
573 } menlo_network_stats_rsp_t;
574 
575 
576 typedef struct menlo_lif_stats_rsp
577 {
578 	uint32_t code;
579 
580 	uint64_t eg_pkt_count;
581 	uint64_t ig_pkt_count;
582 
583 	uint64_t eg_byte_count;
584 	uint64_t ig_byte_count;
585 
586 	uint64_t eg_error_count;
587 	uint64_t ig_error_count;
588 
589 	uint64_t eg_drop_count;
590 	uint64_t ig_drop_count;
591 } menlo_lif_stats_rsp_t;
592 
593 
594 typedef struct menlo_asic_stats_rsp
595 {
596 	uint32_t code;
597 
598 	uint64_t eq_cputx0_cecount;
599 	uint64_t eq_cputx0_dropacl;
600 	uint64_t eq_cputx0_dropovr;
601 	uint64_t eq_cputx0_droprunt;
602 	uint64_t eq_cputx0_poperr;
603 	uint64_t eq_cputx0_pusherr;
604 	uint64_t eq_cputx0_truncovr;
605 	uint64_t eq_cputx0_uecount;
606 
607 	uint64_t eq_cputx1_cecount;
608 	uint64_t eq_cputx1_dropacl;
609 	uint64_t eq_cputx1_dropovr;
610 	uint64_t eq_cputx1_droprunt;
611 	uint64_t eq_cputx1_poperr;
612 	uint64_t eq_cputx1_pusherr;
613 	uint64_t eq_cputx1_truncovr;
614 	uint64_t eq_cputx1_uecount;
615 
616 	uint64_t eq_eth0_dropovr;
617 	uint64_t eq_eth0_droprunt;
618 	uint64_t eq_eth0_truncovr;
619 
620 	uint64_t eq_eth0a_cecount;
621 	uint64_t eq_eth0a_dropacl;
622 	uint64_t eq_eth0a_poperr;
623 	uint64_t eq_eth0a_pusherr;
624 	uint64_t eq_eth0a_uecount;
625 
626 	uint64_t eq_eth0b_cecount;
627 	uint64_t eq_eth0b_dropacl;
628 	uint64_t eq_eth0b_poperr;
629 	uint64_t eq_eth0b_pusherr;
630 	uint64_t eq_eth0b_uecount;
631 
632 	uint64_t eq_eth1_dropovr;
633 	uint64_t eq_eth1_droprunt;
634 	uint64_t eq_eth1_truncovr;
635 
636 	uint64_t eq_eth1a_cecount;
637 	uint64_t eq_eth1a_dropacl;
638 	uint64_t eq_eth1a_poperr;
639 	uint64_t eq_eth1a_pusherr;
640 	uint64_t eq_eth1a_uecount;
641 
642 	uint64_t eq_eth1b_cecount;
643 	uint64_t eq_eth1b_dropacl;
644 	uint64_t eq_eth1b_poperr;
645 	uint64_t eq_eth1b_pusherr;
646 	uint64_t eq_eth1b_uecount;
647 
648 	uint64_t eq_fc0_cecount;
649 	uint64_t eq_fc0_dropacl;
650 	uint64_t eq_fc0_dropovr;
651 	uint64_t eq_fc0_droprunt;
652 	uint64_t eq_fc0_poperr;
653 	uint64_t eq_fc0_pusherr;
654 	uint64_t eq_fc0_truncovr;
655 	uint64_t eq_fc0_uecount;
656 
657 	uint64_t eq_fc1_cecount;
658 	uint64_t eq_fc1_dropacl;
659 	uint64_t eq_fc1_dropovr;
660 	uint64_t eq_fc1_droprunt;
661 	uint64_t eq_fc1_poperr;
662 	uint64_t eq_fc1_pusherr;
663 	uint64_t eq_fc1_truncovr;
664 	uint64_t eq_fc1_uecount;
665 
666 	uint64_t eq_fl_cecount;
667 	uint64_t eq_fl_uecount;
668 
669 	uint64_t eq_pkt_buf_cecount;
670 	uint64_t eq_pkt_buf_uecount;
671 
672 	uint64_t iq_cpurx0_cecount;
673 	uint64_t iq_cpurx0_n0_dropovr;
674 	uint64_t iq_cpurx0_n0_truncovr;
675 	uint64_t iq_cpurx0_n1_dropovr;
676 	uint64_t iq_cpurx0_n1_truncovr;
677 	uint64_t iq_cpurx0_poperr;
678 	uint64_t iq_cpurx0_pusherr;
679 	uint64_t iq_cpurx0_uecount;
680 
681 	uint64_t iq_cpurx1_cecount;
682 	uint64_t iq_cpurx1_n0_dropovr;
683 	uint64_t iq_cpurx1_n0_truncovr;
684 	uint64_t iq_cpurx1_n1_dropovr;
685 	uint64_t iq_cpurx1_n1_truncovr;
686 	uint64_t iq_cpurx1_poperr;
687 	uint64_t iq_cpurx1_pusherr;
688 	uint64_t iq_cpurx1_uecount;
689 
690 	uint64_t iq_cputx_cecount;
691 	uint64_t iq_cputx_dropovr;
692 	uint64_t iq_cputx_droprunt;
693 	uint64_t iq_cputx_poperr;
694 	uint64_t iq_cputx_pusherr;
695 	uint64_t iq_cputx_truncovr;
696 	uint64_t iq_cputx_uecount;
697 
698 	uint64_t iq_eth0a_cecount;
699 	uint64_t iq_eth0a_n0_dropovr;
700 	uint64_t iq_eth0a_n0_truncovr;
701 	uint64_t iq_eth0a_n1_dropovr;
702 	uint64_t iq_eth0a_n1_truncovr;
703 	uint64_t iq_eth0a_poperr;
704 	uint64_t iq_eth0a_pusherr;
705 	uint64_t iq_eth0a_uecount;
706 
707 	uint64_t iq_eth0b_cecount;
708 	uint64_t iq_eth0b_n0_dropovr;
709 	uint64_t iq_eth0b_n0_truncovr;
710 	uint64_t iq_eth0b_n1_dropovr;
711 	uint64_t iq_eth0b_n1_truncovr;
712 	uint64_t iq_eth0b_poperr;
713 	uint64_t iq_eth0b_pusherr;
714 	uint64_t iq_eth0b_uecount;
715 
716 	uint64_t iq_eth1a_cecount;
717 	uint64_t iq_eth1a_n0_dropovr;
718 	uint64_t iq_eth1a_n0_truncovr;
719 	uint64_t iq_eth1a_n1_dropovr;
720 	uint64_t iq_eth1a_n1_truncovr;
721 	uint64_t iq_eth1a_poperr;
722 	uint64_t iq_eth1a_pusherr;
723 	uint64_t iq_eth1a_uecount;
724 
725 	uint64_t iq_eth1b_cecount;
726 	uint64_t iq_eth1b_n0_dropovr;
727 	uint64_t iq_eth1b_n0_truncovr;
728 	uint64_t iq_eth1b_n1_dropovr;
729 	uint64_t iq_eth1b_n1_truncovr;
730 	uint64_t iq_eth1b_poperr;
731 	uint64_t iq_eth1b_pusherr;
732 	uint64_t iq_eth1b_uecount;
733 
734 	uint64_t iq_fc0_cecount;
735 	uint64_t iq_fc0_n0_dropovr;
736 	uint64_t iq_fc0_n0_truncovr;
737 	uint64_t iq_fc0_n1_dropovr;
738 	uint64_t iq_fc0_n1_truncovr;
739 	uint64_t iq_fc0_poperr;
740 	uint64_t iq_fc0_pusherr;
741 	uint64_t iq_fc0_uecount;
742 
743 	uint64_t iq_fc1_cecount;
744 	uint64_t iq_fc1_n0_dropovr;
745 	uint64_t iq_fc1_n0_truncovr;
746 	uint64_t iq_fc1_n1_dropovr;
747 	uint64_t iq_fc1_n1_truncovr;
748 	uint64_t iq_fc1_poperr;
749 	uint64_t iq_fc1_pusherr;
750 	uint64_t iq_fc1_uecount;
751 
752 	uint64_t iq_fl_cecount;
753 	uint64_t iq_fl_uecount;
754 
755 	uint64_t iq_n0_cecount;
756 	uint64_t iq_n0_dropacl;
757 	uint64_t iq_n0_dropovr;
758 	uint64_t iq_n0_droprunt;
759 	uint64_t iq_n0_poperr;
760 	uint64_t iq_n0_pusherr;
761 	uint64_t iq_n0_truncovr;
762 	uint64_t iq_n0_uecount;
763 
764 	uint64_t iq_n1_cecount;
765 	uint64_t iq_n1_dropacl;
766 	uint64_t iq_n1_dropovr;
767 	uint64_t iq_n1_droprunt;
768 	uint64_t iq_n1_poperr;
769 	uint64_t iq_n1_pusherr;
770 	uint64_t iq_n1_truncovr;
771 	uint64_t iq_n1_uecount;
772 
773 	uint64_t iq_pkt_buf_cecount;
774 	uint64_t iq_pkt_buf_uecount;
775 
776 	uint64_t iq_rc_cecount;
777 	uint64_t iq_rc_uecount;
778 
779 	uint64_t misc_mmem_cecount;
780 	uint64_t misc_mmem_uecount;
781 
782 	uint64_t net_eg0_learn_req_drop;
783 	uint64_t net_eg0_pkt_drop_cmd;
784 	uint64_t net_eg0_pkt_drop_lifcfg_invalid;
785 	uint64_t net_eg0_pkt_drop_lifmap_no_hit;
786 	uint64_t net_eg0_pkt_drop_src_bind;
787 
788 	uint64_t net_eg1_learn_req_drop;
789 	uint64_t net_eg1_pkt_drop_cmd;
790 	uint64_t net_eg1_pkt_drop_lifcfg_invalid;
791 	uint64_t net_eg1_pkt_drop_lifmap_no_hit;
792 	uint64_t net_eg1_pkt_drop_src_bind;
793 
794 	uint64_t net_ig0_fwd_lookup_no_hit;
795 	uint64_t net_ig0_pkt_drop_fc_multicast;
796 	uint64_t net_ig0_pkt_drop_invalid_fc_lif;
797 	uint64_t net_ig0_pkt_null_pif;
798 
799 	uint64_t net_ig1_fwd_lookup_no_hit;
800 	uint64_t net_ig1_pkt_drop_fc_multicast;
801 	uint64_t net_ig1_pkt_drop_invalid_fc_lif;
802 	uint64_t net_ig1_pkt_null_pif;
803 
804 	uint64_t host10gbe_port0_rx_pause_cfc;
805 	uint64_t host10gbe_port0_rx_pause_pfc;
806 	uint64_t host10gbe_port0_tx_pause_cfc;
807 	uint64_t host10gbe_port0_tx_pause_pfc;
808 
809 	uint64_t host10gbe_port1_rx_pause_cfc;
810 	uint64_t host10gbe_port1_rx_pause_pfc;
811 	uint64_t host10gbe_port1_tx_pause_cfc;
812 	uint64_t host10gbe_port1_tx_pause_pfc;
813 
814 	uint64_t dce_port0_rx_pause_cfc;
815 	uint64_t dce_port0_rx_pause_pfc;
816 	uint64_t dce_port0_tx_pause_cfc;
817 	uint64_t dce_port0_tx_pause_pfc;
818 
819 	uint64_t dce_port1_rx_pause_cfc;
820 	uint64_t dce_port1_rx_pause_pfc;
821 	uint64_t dce_port1_tx_pause_cfc;
822 	uint64_t dce_port1_tx_pause_pfc;
823 } menlo_asic_stats_rsp_t;
824 
825 
826 #define	MENLO_LOG_NAME_SIZE 		20
827 
828 typedef struct menlo_log
829 {
830 #ifdef EMLXS_BIG_ENDIAN
831 	uint16_t num_entries;
832 	uint16_t id;
833 
834 	uint16_t rsvd;
835 	uint16_t entry_size;
836 #endif /* EMLXS_BIG_ENDIAN */
837 
838 #ifdef EMLXS_LITTLE_ENDIAN
839 	uint16_t id;
840 	uint16_t num_entries;
841 
842 	uint16_t entry_size;
843 	uint16_t rsvd;
844 #endif /* EMLXS_LITTLE_ENDIAN */
845 
846 	char name[MENLO_LOG_NAME_SIZE];
847 } menlo_log_t;
848 
849 
850 typedef struct menlo_log_config_rsp
851 {
852 	uint32_t code;
853 
854 #ifdef EMLXS_BIG_ENDIAN
855 	uint16_t rsvd;
856 	uint16_t num_logs; 	/* Number of logs in log array  */
857 #endif /* EMLXS_BIG_ENDIAN */
858 
859 #ifdef EMLXS_LITTLE_ENDIAN
860 	uint16_t num_logs; 	/* Number of logs in log array  */
861 	uint16_t rsvd;
862 #endif /* EMLXS_LITTLE_ENDIAN */
863 
864 	uint32_t data;		/* First word of array: */
865 				/* menlo_log_t log[num_logs]  */
866 } menlo_log_config_rsp_t;
867 
868 
869 typedef struct menlo_log_data_rsp
870 {
871 	uint32_t code;
872 
873 #ifdef EMLXS_BIG_ENDIAN
874 	uint16_t rsvd;
875 	uint16_t head;		/* Index of oldest log entry in circular */
876 				/* data array */
877 #endif /* EMLXS_BIG_ENDIAN */
878 
879 #ifdef EMLXS_LITTLE_ENDIAN
880 	uint16_t head;		/* Index of oldest log entry in circular */
881 				/* data array */
882 	uint16_t rsvd;
883 #endif /* EMLXS_LITTLE_ENDIAN */
884 
885 	uint32_t data;		/* char array[num_entries][entry_size]  */
886 } menlo_log_data_rsp_t;
887 
888 
889 #define	MENLO_NUM_GP_REGS				32
890 
891 typedef struct menlo_panic_log_data_rsp
892 {
893 	uint32_t code;
894 	uint32_t rsvd_flag; 	/* N/A to mgmt utility */
895 	uint32_t type;		/* Panic type (See beleow) */
896 
897 #define	MENLO_PANIC_TYPE_SOLICITED		0xdead0001
898 #define	MENLO_PANIC_TYPE_EXCEPTION		0xdead0002
899 
900 	uint32_t regs_epc;
901 	uint32_t regs_cp0_cause;
902 	uint32_t regs_cp0_status;
903 	uint32_t regs_gp[MENLO_NUM_GP_REGS];
904 
905 #ifdef EMLXS_BIG_ENDIAN
906 	uint16_t num_entries; 	/* Number of entries in data array  */
907 	uint16_t log_present; 	/* Number of entries in data array  */
908 
909 	uint16_t head;		/* Index of oldest log entry in circular */
910 				/* data buffer */
911 	uint16_t entry_size;	/* Size of each entry */
912 #endif /* EMLXS_BIG_ENDIAN */
913 
914 #ifdef EMLXS_LITTLE_ENDIAN
915 	uint16_t log_present; 	/* Number of entries in data array  */
916 	uint16_t num_entries; 	/* Number of entries in data array  */
917 
918 	uint16_t entry_size;	/* Size of each entry */
919 	uint16_t head;		/* Index of oldest log entry in circular */
920 				/* data buffer */
921 #endif /* EMLXS_LITTLE_ENDIAN */
922 
923 	uint32_t data;		/* char array[num_entries][entry_size]  */
924 } menlo_panic_log_data_rsp_t;
925 
926 
927 typedef struct menlo_lb_mode_rsp
928 {
929 	uint32_t code;
930 	uint32_t mode;		/* Menlo loopback mode */
931 } menlo_lb_mode_rsp_t;
932 
933 
934 #define	MENLO_MAX_FTABLE_ENTRIES	256
935 
936 typedef struct menlo_fte
937 {
938 #ifdef EMLXS_BIG_ENDIAN
939     uint8_t type_mask;
940     uint8_t type;
941     uint16_t flags;
942 
943     uint16_t tag_mask;
944     uint16_t tag;		/* Ehternet VLAN tag */
945 #endif /* EMLXS_BIG_ENDIAN */
946 
947 #ifdef EMLXS_LITTLE_ENDIAN
948     uint16_t flags;
949     uint8_t type;
950     uint8_t type_mask;
951 
952     uint16_t tag;		/* Ehternet VLAN tag */
953     uint16_t tag_mask;
954 #endif /* EMLXS_LITTLE_ENDIAN */
955 
956 #define	MENLO_FTABLE_ENTRY_VALID	0x8000	/* flags field */
957 
958     uint8_t mac_addr[8]; 	/* mac addr */
959     uint8_t mac_addr_mask[8];	/* mac addr mask */
960     uint8_t fc_wwpn[8]; 	/* wwpn */
961 
962     uint32_t lif_bitmap;	/* forwarding vector */
963     uint32_t rsvd;
964 } menlo_fte_t;
965 
966 typedef struct menlo_ftable_rsp
967 {
968 	uint32_t code;	/* Response code */
969 
970 	menlo_fte_t  entry[MENLO_MAX_FTABLE_ENTRIES];
971 } menlo_ftable_rsp_t;
972 
973 
974 #define	MENLO_SFP_PAGE_SIZE			256
975 
976 typedef struct menlo_sfp_rsp
977 {
978 	uint32_t code;	/* Response code */
979 	uint8_t page_a0[MENLO_SFP_PAGE_SIZE];
980 	uint8_t page_a2[MENLO_SFP_PAGE_SIZE];
981 } menlo_sfp_rsp_t;
982 
983 
984 typedef struct menlo_fru_data_rsp
985 {
986 	uint32_t code;		/* Response code */
987 	uint8_t  mac0[8];	/* MAC address of port 0 */
988 	uint8_t  mac1[8];    	/* MAC address of port 1 */
989 	uint32_t flags;
990 } menlo_fru_data_rsp_t;
991 
992 
993 typedef  struct menlo_diag_log_data_rsp
994 {
995 	uint32_t code;		/* Response code */
996 	uint32_t data_length;   /* Length of the diagnostic log */
997 				/* buffer (bytes) */
998 	uint32_t data;		/* menlo_diag_log_t log of size */
999 				/* data_length bytes */
1000 } menlo_diag_log_data_rsp_t;
1001 
1002 
1003 typedef struct menlo_diag_log
1004 {
1005 	uint32_t num_tests;		/* Number of entries in data array  */
1006 	uint32_t status_length;		/* Size (words) of the */
1007 					/* menlo_diag_log_entry_t.data array */
1008 	uint32_t requested_loop_cnt;	/* Number of test iterations */
1009 					/* requested */
1010 	uint32_t completed_loop_cnt;	/* Number of test iterations actually */
1011 					/* completed */
1012 	uint32_t test_summary;		/* Overal test status */
1013 
1014 #define	DIAG_TEST_STATUS_SUCCESS	0xD0000001
1015 #define	DIAG_TEST_STATUS_FAIL		0xD0000002
1016 #define	DIAG_TEST_STATUS_ABORT		0xD0000003
1017 
1018 	uint32_t data;			/* menlo_diag_log_entry_t */
1019 					/* entry[num_tests] */
1020 } menlo_diag_log_t;
1021 
1022 typedef struct menlo_diag_log_entry
1023 {
1024 	uint32_t status;		/* Test status See */
1025 					/* DIAG_TEST_STATUS_XXXXX above */
1026 	uint32_t data;			/* uint32_t array[status_length] */
1027 } menlo_diag_log_entry_t;
1028 
1029 
1030 /* Hornet 2 */
1031 
1032 typedef struct menlo_get_fcoe_params_rsp
1033 {
1034 	uint32_t code;	 /* Response code */
1035 
1036 	uint32_t fcoe_mode; /* FIP or Non-FIP */
1037 
1038 /* FCoE Operation Mode */
1039 #define	FCOE_MODE_NON_FIP	0
1040 #define	FCOE_MODE_FIP		1
1041 
1042 	menlo_fcoe_params_t params; /* Specific FCoE parameters */
1043 
1044 } menlo_get_fcoe_params_rsp_t;
1045 
1046 typedef struct fcf_info
1047 {
1048 	uint32_t handle; /* Handle of the subject FCF */
1049 	uint8_t mac[6]; /* FCF MAC */
1050 	uint16_t vlan_id; /* vlan_id */
1051 	uint8_t sw_name[8]; /* Switch name */
1052 	uint8_t fabric_name[8]; /* Fabric name */
1053 	uint32_t fc_map; /* FC map (not applicable for SPMA) */
1054 	uint32_t lka_period; /* Periodic LKA */
1055 
1056 	uint16_t state; /* FCF state */
1057 
1058 	uint16_t ctrl_flags; /* FIP header flags */
1059 	uint16_t sup_addr_mode; /* FCoE addressing mode capability */
1060 
1061 /* FCoE Addressing Mode */
1062 #define	SPMA_ADDR_MODE		1
1063 #define	FPMA_ADDR_MODE		2
1064 
1065 	uint16_t priority; /* Priority of FCF */
1066 
1067 } fcf_info_t;
1068 
1069 typedef struct menlo_get_fcf_list_rsp
1070 {
1071 	uint32_t code;	 /* Response code */
1072 
1073 	uint32_t returned_fcfs; /* Number of returned FCFs */
1074 	uint32_t total_fcfs; /* Total number of discovered FCFs */
1075 	uint32_t active_fcfs; /* Number of active FCFs */
1076 	uint32_t fcf_list; /* List of returned FCFs' information, fcf_info_t */
1077 
1078 } menlo_get_fcf_list_rsp_t;
1079 
1080 typedef struct menlo_get_facl_rsp
1081 {
1082 	uint32_t code;	/* Response code */
1083 
1084 	uint32_t returned_facls; /* Number of returned ACLs */
1085 	uint32_t total_facls; /* Total number of configured ACLs */
1086 	uint32_t facl_list; /* List of returned ACL entry, facl_t */
1087 
1088 } menlo_get_facl_rsp_t;
1089 
1090 typedef struct create_vl_rsp
1091 {
1092 	uint32_t code;	/* Response code */
1093 
1094 	uint32_t vl_handle; /* Handle of created VL */
1095 } create_vl_rsp_t;
1096 
1097 typedef struct menlo_get_pg_info_rsp
1098 {
1099 	uint32_t code; /* Response code */
1100 
1101 	uint32_t max_supported_pg; /* Max PG supported by hardware */
1102 	uint32_t dcbx_feature_syncd; /* indicate DCBX feature syncd with peer */
1103 	menlo_pg_info_t curr_pg_info; /* Current PG settings */
1104 	menlo_pg_info_t def_pg_info; /* Default PG settings */
1105 	uint32_t max_bg_bw[MAX_GROUPS]; /* Max bandwidth allowed per group */
1106 
1107 } menlo_get_pg_info_rsp_t;
1108 
1109 typedef struct menlo_get_host_eth_pfc_flag_rsp
1110 {
1111 	uint32_t code; /* Response code */
1112 
1113 	uint32_t host_pfc_enable; /* 1 = PFC on Host i/f enabled */
1114 
1115 /* Host PFC Flag Definitions */
1116 #define	MENLO_HOST_PFC_DISABLE	0x0
1117 #define	MENLO_HOST_PFC_ENABLE	0x1
1118 
1119 } menlo_get_host_eth_pfc_flag_rsp_t;
1120 
1121 typedef struct menlo_get_dcbx_mode_rsp
1122 {
1123 	uint32_t code; /* Response code */
1124 
1125 	uint32_t mode; /* Mode value. See below */
1126 
1127 #define	MENLO_DCBX_MODE_PRE_CEE		0x80000000
1128 #define	MENLO_DCBX_MODE_CEE_VER_01	0x00000001
1129 #define	MENLO_DCBX_MODE_CEE_VER_02	0x00000002
1130 #define	MENLO_DCBX_MODE_CEE_VER_03	0x00000003
1131 #define	MENLO_DCBX_MODE_CEE_VER_04	0x00000004
1132 
1133 } menlo_get_dcbx_mode_rsp_t;
1134 
1135 
1136 
1137 typedef union menlo_rsp
1138 {
1139 	uint32_t			word[32];
1140 	uint32_t			code;
1141 
1142 /* Response codes */
1143 #define	MENLO_RSP_SUCCESS  		0x00000000
1144 #define	MENLO_ERR_FAILED  		0x00000001
1145 #define	MENLO_ERR_INVALID_CMD		0x00000002
1146 #define	MENLO_ERR_INVALID_CREDIT	0x00000003
1147 #define	MENLO_ERR_INVALID_SIZE   	0x00000004
1148 #define	MENLO_ERR_INVALID_ADDRESS	0x00000005
1149 #define	MENLO_ERR_INVALID_CONTEXT	0x00000006
1150 #define	MENLO_ERR_INVALID_LENGTH	0x00000007
1151 #define	MENLO_ERR_INVALID_TYPE		0x00000008
1152 #define	MENLO_ERR_INVALID_DATA		0x00000009
1153 #define	MENLO_ERR_INVALID_VALUE1	0x0000000A
1154 #define	MENLO_ERR_INVALID_VALUE2	0x0000000B
1155 #define	MENLO_ERR_INVALID_MASK		0x0000000C
1156 #define	MENLO_ERR_CHECKSUM		0x0000000D
1157 #define	MENLO_ERR_UNKNOWN_FCID		0x0000000E
1158 #define	MENLO_ERR_UNKNOWN_WWN		0x0000000F
1159 #define	MENLO_ERR_BUSY			0x00000010
1160 #define	MENLO_ERR_INVALID_FLAG		0x00000011
1161 #define	MENLO_ERR_SFP_ABSENT		0x00000012
1162 
1163 	menlo_init_rsp_t		init;
1164 	menlo_get_config_rsp_t		config;
1165 	menlo_fc_stats_rsp_t		fc_stats;
1166 	menlo_network_stats_rsp_t	net_stats;
1167 	menlo_lif_stats_rsp_t		lif_stats;
1168 	menlo_log_config_rsp_t		log_cfg;
1169 	menlo_log_data_rsp_t		log;
1170 	menlo_panic_log_data_rsp_t	panic_log;
1171 	menlo_lb_mode_rsp_t		lb_mode;
1172 	menlo_asic_stats_rsp_t		asic_stats;
1173 	menlo_ftable_rsp_t		ftable;
1174 	menlo_sfp_rsp_t			sfp;
1175 	menlo_fru_data_rsp_t		fru;
1176 	menlo_diag_log_data_rsp_t	diag_log;
1177 } menlo_rsp_t;
1178 
1179 
1180 /*
1181  * FIRMWARE IMAGE
1182  */
1183 
1184 typedef struct menlo_image_hdr
1185 {
1186 	uint32_t rsvd1;
1187 	uint32_t rsvd2;
1188 	uint32_t version;
1189 	uint32_t file_length;		/* Length of entire file */
1190 	uint32_t image_length;		/* length of the image without */
1191 					/* padding */
1192 	uint32_t rsvd3;
1193 	uint32_t rsvd4;
1194 	uint32_t checksum_offset;	/* Byte offset to image checksum */
1195 } menlo_image_hdr_t;
1196 
1197 
1198 /* The version header structure needs to be a multiple of 4 bytes */
1199 typedef struct menlo_version_hdr
1200 {
1201 	uint32_t padded;    /* 1 = Image padded, 0 = Image not padded */
1202 
1203 	uint32_t type;
1204 
1205 /* Type */
1206 #define	MENLO_IMAGE_TYPE_FIRMWARE 	1
1207 #define	MENLO_IMAGE_TYPE_DIAGNOSTICS 	2
1208 
1209 	uint32_t version;   /* fw or diag version */
1210 	uint32_t checksum;  /* 32bit XOR checksum -- needs to be at the end */
1211 } menlo_version_hdr_t;
1212 
1213 
1214 #endif	/* MENLO_SUPPORT */
1215 
1216 #ifdef	__cplusplus
1217 }
1218 #endif
1219 
1220 #endif	/* _EMLXS_MENLO_H */
1221