1 /*
2  * Copyright 2014-2017 Cavium, Inc.
3  * The contents of this file are subject to the terms of the Common Development
4  * and Distribution License, v.1,  (the "License").
5  *
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the License at available
9  * at http://opensource.org/licenses/CDDL-1.0
10  *
11  * See the License for the specific language governing permissions and
12  * limitations under the License.
13  */
14 
15 #ifndef _CP_HSI_H
16 #define _CP_HSI_H
17 
18 // Offset of xxx_hsi in 32 bit words from beginning of scratchpad
19 #define CP_HSI_OFFSET 0x4
20 
21 typedef struct _fio_dbg_b_t {
22     u8_t    cpu_src;
23     u8_t    is_read;
24     u16_t   fio_addr;
25     u32_t   fio_data;
26 }fio_dbg_b_t;
27 
28 typedef struct _fio_dbg_l_t {
29     u16_t   fio_addr;
30     u8_t    is_read;
31     u8_t    cpu_src;
32     u32_t   fio_data;
33 }fio_dbg_l_t;
34 
35 #if defined(LITTLE_ENDIAN)
36     typedef fio_dbg_l_t fio_dbg_t;
37 #elif defined(BIG_ENDIAN)
38     typedef fio_dbg_b_t fio_dbg_t;
39 #endif
40 
41 /*
42  * Runtime Configurable Parameters
43  */
44 typedef struct _cp_hsi_t {
45     fw_version_t  version;
46     u32_t fw_doorbell;
47 	    #define  KWQ_READY     (1<<0)
48         #define  KWQ1_READY    (1<<1)
49         #define  KWQ2_READY    (1<<2)
50         #define  KWQ3_READY    (1<<3)
51     u32_t iscsi_sq_size;				// Number of elements in queue. Its k lsb bits must be 0.
52     u32_t cp_cpq_kwq[2];
53     u32_t iscsi_xinan_unit;				// Xinan only: number of VCIDs for an iscsi connection
54     u32_t pg_ctx_map;                   /* Xinan only: pg ctx start and end */
55     u64_t volatile idle_count;
56     u32_t iscsi_sq_wqes_per_page;		// Number of WQEs per page
57     u32_t iscsi_sq_num_pages;			// Number of pages ( = entries in SQ page table)
58     u32_t cp_gen_bd_max;
59     u32_t iscsi_teton_l4_cmd_offset;   	// Teton Only: offset of L4 ccell command array
60     u32_t iscsi_teton_l5_offset;       	// Teton Only: offset of L5 section
61     u32_t iscsi_teton_l5_cmd_offset;   	// Teton Only: offset of L5 ccell command array
62     u32_t iscsi_task_offset;     		// offset of the task array
63     u32_t iscsi_r2tq_offset;     		// offset of R2TQ section
64     u32_t iscsi_max_num_of_tasks;     	// maximal number of pending tasks
65     u32_t iscsi_max_num_of_ccells;    	// maximal number of ccells
66     u32_t iscsi_dbg_ctx_addr_h;
67 	u32_t iscsi_dbg_ctx_addr_l;
68 	u32_t iscsi_dbg_ctx_cid;
69     u32_t iscsi_ctx_map;                /* Xinan only: iscsi ctx start and end */
70     u32_t num_tcp_nagle_allow;          /* threshold of num of TOE conn that we allow
71                                            for stricter tcp nagle alogrithm. */
72     u32_t timer_scan_freq;              /* Xinan only: control timer scan frequency */
73 	u32_t iscsi_max_conn;				/* Read only parameter for the host to read */
74     u32_t num_kwqe_limit;               /* restrict number kwqes to be process per dma */
75     u32_t idle_ts_period;               /* time slice period for each tasks during idle loop */
76     u32_t toe_ofld_retx_cnt;            /* Number of TOE connections that is oflded with retx */
77     fio_dbg_t   fio_dbg_info;           /* for debugging fio access */
78     u32_t l2_cid_cnt;                   /* Track erroneous cpq entry */
79     u32_t unused;
80 }cp_hsi_t;
81 
82 
83 // This macro can be used for little or big endian 32-bit system
84 #define CP_HSI_OFFSETOFF(m)  (OFFSETOF(cp_hsi_t,m) + 0x10)
85 #define CP_HSI_SIZEOF(m)     (sizeof (((cp_hsi_t *)0)->m))
86 
87 // Calling the following macro will actually get optimized during compile
88 // time. Its sole purpose is to ensure HSI variables cannot be modified/moved
89 // unnoticed  scratch[10240]  0x1a0000  (RW/Reset: undefined)
90 #define TEST_CP_HSI(){                                                    \
91 if (0){                                                                   \
92  1/(CP_HSI_OFFSETOFF(version)                        == (CP_HSI_OFFSET * sizeof(u32_t) + 0x000) && \
93     CP_HSI_OFFSETOFF(fw_doorbell)                    == (CP_HSI_OFFSET * sizeof(u32_t) + 0x010) && \
94     CP_HSI_OFFSETOFF(iscsi_sq_size)                  == (CP_HSI_OFFSET * sizeof(u32_t) + 0x014) && \
95     CP_HSI_OFFSETOFF(cp_cpq_kwq[0])                  == (CP_HSI_OFFSET * sizeof(u32_t) + 0x018) && \
96     CP_HSI_OFFSETOFF(cp_cpq_kwq[1])                  == (CP_HSI_OFFSET * sizeof(u32_t) + 0x01c) && \
97     CP_HSI_OFFSETOFF(iscsi_xinan_unit)               == (CP_HSI_OFFSET * sizeof(u32_t) + 0x020) && \
98     CP_HSI_OFFSETOFF(pg_ctx_map)                     == (CP_HSI_OFFSET * sizeof(u32_t) + 0x024) && \
99     CP_HSI_OFFSETOFF(idle_count)                     == (CP_HSI_OFFSET * sizeof(u32_t) + 0x028) && \
100     CP_HSI_OFFSETOFF(iscsi_sq_wqes_per_page)         == (CP_HSI_OFFSET * sizeof(u32_t) + 0x030) && \
101     CP_HSI_OFFSETOFF(iscsi_sq_num_pages)             == (CP_HSI_OFFSET * sizeof(u32_t) + 0x034) && \
102     CP_HSI_OFFSETOFF(cp_gen_bd_max)                  == (CP_HSI_OFFSET * sizeof(u32_t) + 0x038) && \
103     CP_HSI_OFFSETOFF(iscsi_teton_l4_cmd_offset)      == (CP_HSI_OFFSET * sizeof(u32_t) + 0x03c) && \
104     CP_HSI_OFFSETOFF(iscsi_teton_l5_offset)          == (CP_HSI_OFFSET * sizeof(u32_t) + 0x040) && \
105     CP_HSI_OFFSETOFF(iscsi_teton_l5_cmd_offset)      == (CP_HSI_OFFSET * sizeof(u32_t) + 0x044) && \
106     CP_HSI_OFFSETOFF(iscsi_task_offset)              == (CP_HSI_OFFSET * sizeof(u32_t) + 0x048) && \
107     CP_HSI_OFFSETOFF(iscsi_r2tq_offset)              == (CP_HSI_OFFSET * sizeof(u32_t) + 0x04c) && \
108     CP_HSI_OFFSETOFF(iscsi_max_num_of_tasks)         == (CP_HSI_OFFSET * sizeof(u32_t) + 0x050) && \
109     CP_HSI_OFFSETOFF(iscsi_max_num_of_ccells)        == (CP_HSI_OFFSET * sizeof(u32_t) + 0x054) && \
110     CP_HSI_OFFSETOFF(iscsi_dbg_ctx_addr_h)           == (CP_HSI_OFFSET * sizeof(u32_t) + 0x058) && \
111     CP_HSI_OFFSETOFF(iscsi_dbg_ctx_addr_l)           == (CP_HSI_OFFSET * sizeof(u32_t) + 0x05c) && \
112     CP_HSI_OFFSETOFF(iscsi_dbg_ctx_cid)              == (CP_HSI_OFFSET * sizeof(u32_t) + 0x060) && \
113     CP_HSI_OFFSETOFF(iscsi_ctx_map)                  == (CP_HSI_OFFSET * sizeof(u32_t) + 0x064) && \
114     CP_HSI_OFFSETOFF(num_tcp_nagle_allow)            == (CP_HSI_OFFSET * sizeof(u32_t) + 0x068) && \
115     CP_HSI_OFFSETOFF(timer_scan_freq)                == (CP_HSI_OFFSET * sizeof(u32_t) + 0x06c) && \
116 	CP_HSI_OFFSETOFF(iscsi_max_conn)                 == (CP_HSI_OFFSET * sizeof(u32_t) + 0x070) && \
117 	CP_HSI_OFFSETOFF(num_kwqe_limit)                 == (CP_HSI_OFFSET * sizeof(u32_t) + 0x074) && \
118 	CP_HSI_OFFSETOFF(idle_ts_period)                 == (CP_HSI_OFFSET * sizeof(u32_t) + 0x078) && \
119 	CP_HSI_OFFSETOFF(toe_ofld_retx_cnt)              == (CP_HSI_OFFSET * sizeof(u32_t) + 0x07c) && \
120     CP_HSI_OFFSETOFF(fio_dbg_info)                   == (CP_HSI_OFFSET * sizeof(u32_t) + 0x080) && \
121     CP_HSI_OFFSETOFF(l2_cid_cnt)                     == (CP_HSI_OFFSET * sizeof(u32_t) + 0x088) && \
122     CP_HSI_OFFSETOFF(unused)                         == (CP_HSI_OFFSET * sizeof(u32_t) + 0x08C) && \
123     CP_HSI_OFFSETOFF(unused)+CP_HSI_SIZEOF(unused) == (CP_HSI_OFFSET * sizeof(u32_t) + sizeof(cp_hsi_t)));}}
124 
125 #endif
126