1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_NXGE_NXGE_ZCP_HW_H
27 #define	_SYS_NXGE_NXGE_ZCP_HW_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 #include <nxge_defs.h>
34 
35 /*
36  * Neptune Zerocopy Hardware definitions
37  * Updated to reflect PRM-0.8.
38  */
39 
40 #define	ZCP_CONFIG_REG		(FZC_ZCP + 0x00000)
41 #define	ZCP_INT_STAT_REG	(FZC_ZCP + 0x00008)
42 #define	ZCP_INT_STAT_TEST_REG	(FZC_ZCP + 0x00108)
43 #define	ZCP_INT_MASK_REG	(FZC_ZCP + 0x00010)
44 
45 #define	ZCP_BAM4_RE_CTL_REG 	(FZC_ZCP + 0x00018)
46 #define	ZCP_BAM8_RE_CTL_REG 	(FZC_ZCP + 0x00020)
47 #define	ZCP_BAM16_RE_CTL_REG 	(FZC_ZCP + 0x00028)
48 #define	ZCP_BAM32_RE_CTL_REG 	(FZC_ZCP + 0x00030)
49 
50 #define	ZCP_DST4_RE_CTL_REG 	(FZC_ZCP + 0x00038)
51 #define	ZCP_DST8_RE_CTL_REG 	(FZC_ZCP + 0x00040)
52 #define	ZCP_DST16_RE_CTL_REG 	(FZC_ZCP + 0x00048)
53 #define	ZCP_DST32_RE_CTL_REG 	(FZC_ZCP + 0x00050)
54 
55 #define	ZCP_RAM_DATA_REG	(FZC_ZCP + 0x00058)
56 #define	ZCP_RAM_DATA0_REG	(FZC_ZCP + 0x00058)
57 #define	ZCP_RAM_DATA1_REG	(FZC_ZCP + 0x00060)
58 #define	ZCP_RAM_DATA2_REG	(FZC_ZCP + 0x00068)
59 #define	ZCP_RAM_DATA3_REG	(FZC_ZCP + 0x00070)
60 #define	ZCP_RAM_DATA4_REG	(FZC_ZCP + 0x00078)
61 #define	ZCP_RAM_BE_REG		(FZC_ZCP + 0x00080)
62 #define	ZCP_RAM_ACC_REG		(FZC_ZCP + 0x00088)
63 
64 #define	ZCP_TRAINING_VECTOR_REG	(FZC_ZCP + 0x000C0)
65 #define	ZCP_STATE_MACHINE_REG	(FZC_ZCP + 0x000C8)
66 #define	ZCP_CHK_BIT_DATA_REG	(FZC_ZCP + 0x00090)
67 #define	ZCP_RESET_CFIFO_REG	(FZC_ZCP + 0x00098)
68 #define	ZCP_RESET_CFIFO_MASK	0x0F
69 
70 #define	ZCP_CFIFIO_RESET_WAIT		10
71 #define	ZCP_P0_P1_CFIFO_DEPTH		2048
72 #define	ZCP_P2_P3_CFIFO_DEPTH		1024
73 #define	ZCP_NIU_CFIFO_DEPTH		1024
74 
75 typedef union _zcp_reset_cfifo {
76 	uint64_t value;
77 	struct {
78 #if defined(_BIG_ENDIAN)
79 		uint32_t hdw;
80 #endif
81 		struct {
82 #if defined(_BIT_FIELDS_HTOL)
83 			uint32_t rsrvd:28;
84 			uint32_t reset_cfifo3:1;
85 			uint32_t reset_cfifo2:1;
86 			uint32_t reset_cfifo1:1;
87 			uint32_t reset_cfifo0:1;
88 #elif defined(_BIT_FIELDS_LTOH)
89 			uint32_t reset_cfifo0:1;
90 			uint32_t reset_cfifo1:1;
91 			uint32_t reset_cfifo2:1;
92 			uint32_t reset_cfifo3:1;
93 			uint32_t rsrvd:28;
94 #endif
95 		} ldw;
96 #if !defined(_BIG_ENDIAN)
97 		uint32_t hdw;
98 #endif
99 	} bits;
100 } zcp_reset_cfifo_t, *p_zcp_reset_cfifo_t;
101 
102 #define	ZCP_CFIFO_ECC_PORT0_REG	(FZC_ZCP + 0x000A0)
103 #define	ZCP_CFIFO_ECC_PORT1_REG	(FZC_ZCP + 0x000A8)
104 #define	ZCP_CFIFO_ECC_PORT2_REG	(FZC_ZCP + 0x000B0)
105 #define	ZCP_CFIFO_ECC_PORT3_REG	(FZC_ZCP + 0x000B8)
106 
107 /* NOTE: Same as RX_LOG_PAGE_HDL */
108 #define	ZCP_PAGE_HDL_REG	(FZC_DMC + 0x20038)
109 
110 /* Data Structures */
111 
112 typedef union zcp_config_reg_u {
113 	uint64_t value;
114 	struct {
115 #if defined(_BIG_ENDIAN)
116 		uint32_t hdw;
117 #endif
118 		struct {
119 #if defined(_BIT_FIELDS_HTOL)
120 			uint32_t rsvd:7;
121 			uint32_t mode_32_bit:1;
122 			uint32_t debug_sel:8;
123 			uint32_t rdma_th:11;
124 			uint32_t ecc_chk_dis:1;
125 			uint32_t par_chk_dis:1;
126 			uint32_t dis_buf_rn:1;
127 			uint32_t dis_buf_rq_if:1;
128 			uint32_t zc_enable:1;
129 #elif defined(_BIT_FIELDS_LTOH)
130 			uint32_t zc_enable:1;
131 			uint32_t dis_buf_rq_if:1;
132 			uint32_t dis_buf_rn:1;
133 			uint32_t par_chk_dis:1;
134 			uint32_t ecc_chk_dis:1;
135 			uint32_t rdma_th:11;
136 			uint32_t debug_sel:8;
137 			uint32_t mode_32_bit:1;
138 			uint32_t rsvd:7;
139 #endif
140 		} ldw;
141 #if !defined(_BIG_ENDIAN)
142 		uint32_t hdw;
143 #endif
144 	} bits;
145 } zcp_config_reg_t, *zcp_config_reg_pt;
146 
147 #define	ZCP_DEBUG_SEL_BITS	0xFF
148 #define	ZCP_DEBUG_SEL_SHIFT	16
149 #define	ZCP_DEBUG_SEL_MASK	(ZCP_DEBUG_SEL_BITS << ZCP_DEBUG_SEL_SHIFT)
150 #define	RDMA_TH_BITS		0x7FF
151 #define	RDMA_TH_SHIFT		5
152 #define	RDMA_TH_MASK		(RDMA_TH_BITS << RDMA_TH_SHIFT)
153 #define	ECC_CHK_DIS		(1 << 4)
154 #define	PAR_CHK_DIS		(1 << 3)
155 #define	DIS_BUFF_RN		(1 << 2)
156 #define	DIS_BUFF_RQ_IF		(1 << 1)
157 #define	ZC_ENABLE		(1 << 0)
158 
159 typedef union zcp_int_stat_reg_u {
160 	uint64_t value;
161 	struct {
162 #if defined(_BIG_ENDIAN)
163 		uint32_t hdw;
164 #endif
165 		struct {
166 #if defined(_BIT_FIELDS_HTOL)
167 			uint32_t rsvd:16;
168 			uint32_t rrfifo_urun:1;
169 			uint32_t rrfifo_orun:1;
170 			uint32_t rsvd1:1;
171 			uint32_t rspfifo_uc_err:1;
172 			uint32_t buf_overflow:1;
173 			uint32_t stat_tbl_perr:1;
174 			uint32_t dyn_tbl_perr:1;
175 			uint32_t buf_tbl_perr:1;
176 			uint32_t tt_tbl_perr:1;
177 			uint32_t rsp_tt_index_err:1;
178 			uint32_t slv_tt_index_err:1;
179 			uint32_t zcp_tt_index_err:1;
180 			uint32_t cfifo_ecc3:1;
181 			uint32_t cfifo_ecc2:1;
182 			uint32_t cfifo_ecc1:1;
183 			uint32_t cfifo_ecc0:1;
184 #elif defined(_BIT_FIELDS_LTOH)
185 			uint32_t cfifo_ecc0:1;
186 			uint32_t cfifo_ecc1:1;
187 			uint32_t cfifo_ecc2:1;
188 			uint32_t cfifo_ecc3:1;
189 			uint32_t zcp_tt_index_err:1;
190 			uint32_t slv_tt_index_err:1;
191 			uint32_t rsp_tt_index_err:1;
192 			uint32_t tt_tbl_perr:1;
193 			uint32_t buf_tbl_perr:1;
194 			uint32_t dyn_tbl_perr:1;
195 			uint32_t stat_tbl_perr:1;
196 			uint32_t buf_overflow:1;
197 			uint32_t rspfifo_uc_err:1;
198 			uint32_t rsvd1:1;
199 			uint32_t rrfifo_orun:1;
200 			uint32_t rrfifo_urun:1;
201 			uint32_t rsvd:16;
202 #endif
203 		} ldw;
204 #if !defined(_BIG_ENDIAN)
205 		uint32_t hdw;
206 #endif
207 	} bits;
208 } zcp_int_stat_reg_t, *zcp_int_stat_reg_pt, zcp_int_mask_reg_t,
209 	*zcp_int_mask_reg_pt;
210 
211 #define	RRFIFO_UNDERRUN		(1 << 15)
212 #define	RRFIFO_OVERRUN		(1 << 14)
213 #define	RSPFIFO_UNCORR_ERR	(1 << 12)
214 #define	BUFFER_OVERFLOW		(1 << 11)
215 #define	STAT_TBL_PERR		(1 << 10)
216 #define	BUF_DYN_TBL_PERR	(1 << 9)
217 #define	BUF_TBL_PERR		(1 << 8)
218 #define	TT_PROGRAM_ERR		(1 << 7)
219 #define	RSP_TT_INDEX_ERR	(1 << 6)
220 #define	SLV_TT_INDEX_ERR	(1 << 5)
221 #define	ZCP_TT_INDEX_ERR	(1 << 4)
222 #define	CFIFO_ECC3		(1 << 3)
223 #define	CFIFO_ECC0		(1 << 0)
224 #define	CFIFO_ECC2		(1 << 2)
225 #define	CFIFO_ECC1		(1 << 1)
226 
227 typedef union zcp_bam_region_reg_u {
228 	uint64_t value;
229 	struct {
230 #if defined(_BIG_ENDIAN)
231 		uint32_t hdw;
232 #endif
233 		struct {
234 #if defined(_BIT_FIELDS_HTOL)
235 			uint32_t loj:1;
236 			uint32_t range_chk_en:1;
237 			uint32_t last_zcfid:10;
238 			uint32_t first_zcfid:10;
239 			uint32_t offset:10;
240 #elif defined(_BIT_FIELDS_LTOH)
241 			uint32_t offset:10;
242 			uint32_t first_zcfid:10;
243 			uint32_t last_zcfid:10;
244 			uint32_t range_chk_en:1;
245 			uint32_t loj:1;
246 #endif
247 		} ldw;
248 #if !defined(_BIG_ENDIAN)
249 		uint32_t hdw;
250 #endif
251 	} bits;
252 } zcp_bam_region_reg_t, *zcp_bam_region_reg_pt;
253 
254 typedef union zcp_dst_region_reg_u {
255 	uint64_t value;
256 	struct {
257 #if defined(_BIG_ENDIAN)
258 		uint32_t hdw;
259 #endif
260 		struct {
261 #if defined(_BIT_FIELDS_HTOL)
262 			uint32_t rsvd:22;
263 			uint32_t ds_offset:10;
264 #elif defined(_BIT_FIELDS_LTOH)
265 			uint32_t rsvd:22;
266 			uint32_t ds_offset:10;
267 #endif
268 		} ldw;
269 #if !defined(_BIG_ENDIAN)
270 		uint32_t hdw;
271 #endif
272 	} bits;
273 } zcp_dst_region_reg_t, *zcp_dst_region_reg_pt;
274 
275 typedef	enum tbuf_size_e {
276 	TBUF_4K		= 0,
277 	TBUF_8K,
278 	TBUF_16K,
279 	TBUF_32K,
280 	TBUF_64K,
281 	TBUF_128K,
282 	TBUF_256K,
283 	TBUF_512K,
284 	TBUF_1M,
285 	TBUF_2M,
286 	TBUF_4M,
287 	TBUF_8M
288 } tbuf_size_t;
289 
290 typedef	enum tbuf_num_e {
291 	TBUF_NUM_4	= 0,
292 	TBUF_NUM_8,
293 	TBUF_NUM_16,
294 	TBUF_NUM_32
295 } tbuf_num_t;
296 
297 typedef	enum tmode_e {
298 	TMODE_BASIC		= 0,
299 	TMODE_AUTO_UNMAP	= 1,
300 	TMODE_AUTO_ADV		= 3
301 } tmode_t;
302 
303 typedef	struct tte_sflow_attr_s {
304 	union {
305 		uint64_t value;
306 		struct {
307 #if defined(_BIG_ENDIAN)
308 			uint32_t hdw;
309 #endif
310 			struct {
311 #if defined(_BIT_FIELDS_HTOL)
312 				uint32_t ulp_end:18;
313 				uint32_t num_buf:2;
314 				uint32_t buf_size:4;
315 				uint32_t rdc_tbl_offset:8;
316 #elif defined(_BIT_FIELDS_LTOH)
317 				uint32_t rdc_tbl_offset:8;
318 				uint32_t buf_size:4;
319 				uint32_t num_buf:2;
320 				uint32_t ulp_end:18;
321 #endif
322 			} ldw;
323 #if !defined(_BIG_ENDIAN)
324 			uint32_t hdw;
325 #endif
326 		} bits;
327 	} qw0;
328 
329 	union {
330 		uint64_t value;
331 		struct {
332 #if defined(_BIG_ENDIAN)
333 			uint32_t hdw;
334 #endif
335 			struct {
336 #if defined(_BIT_FIELDS_HTOL)
337 				uint32_t ring_base:12;
338 				uint32_t skip:1;
339 				uint32_t rsvd:1;
340 				uint32_t tmode:2;
341 				uint32_t unmap_all_en:1;
342 				uint32_t ulp_end_en:1;
343 				uint32_t ulp_end:14;
344 #elif defined(_BIT_FIELDS_LTOH)
345 				uint32_t ulp_end:14;
346 				uint32_t ulp_end_en:1;
347 				uint32_t unmap_all_en:1;
348 				uint32_t tmode:2;
349 				uint32_t rsvd:1;
350 				uint32_t skip:1;
351 				uint32_t ring_base:12;
352 #endif
353 			} ldw;
354 #if !defined(_BIG_ENDIAN)
355 		uint32_t hdw;
356 #endif
357 		} bits;
358 	} qw1;
359 
360 	union {
361 		uint64_t value;
362 		struct {
363 #if defined(_BIG_ENDIAN)
364 			uint32_t hdw;
365 #endif
366 			struct {
367 #if defined(_BIT_FIELDS_HTOL)
368 				uint32_t busy:1;
369 				uint32_t ring_size:4;
370 				uint32_t ring_base:27;
371 #elif defined(_BIT_FIELDS_LTOH)
372 				uint32_t ring_base:27;
373 				uint32_t ring_size:4;
374 				uint32_t busy:1;
375 #endif
376 			} ldw;
377 #if !defined(_BIG_ENDIAN)
378 			uint32_t hdw;
379 #endif
380 		} bits;
381 	} qw2;
382 
383 	union {
384 		uint64_t value;
385 		struct {
386 #if defined(_BIG_ENDIAN)
387 			uint32_t hdw;
388 #endif
389 			struct {
390 #if defined(_BIT_FIELDS_HTOL)
391 				uint32_t rsvd:16;
392 				uint32_t toq:16;
393 #elif defined(_BIT_FIELDS_LTOH)
394 				uint32_t toq:16;
395 				uint32_t rsvd:16;
396 #endif
397 			} ldw;
398 #if !defined(_BIG_ENDIAN)
399 			uint32_t hdw;
400 #endif
401 		} bits;
402 	} qw3;
403 
404 	union {
405 		uint64_t value;
406 		struct {
407 #if defined(_BIG_ENDIAN)
408 			uint32_t hdw;
409 #endif
410 			struct {
411 #if defined(_BIT_FIELDS_HTOL)
412 				uint32_t rsvd:28;
413 				uint32_t dat4:4;
414 #elif defined(_BIT_FIELDS_LTOH)
415 				uint32_t dat4:4;
416 				uint32_t rsvd:28;
417 #endif
418 			} ldw;
419 #if !defined(_BIG_ENDIAN)
420 			uint32_t hdw;
421 #endif
422 		} bits;
423 	} qw4;
424 
425 } tte_sflow_attr_t, *tte_sflow_attr_pt;
426 
427 #define	TTE_RDC_TBL_SFLOW_BITS_EN	0x0001
428 #define	TTE_BUF_SIZE_BITS_EN		0x0002
429 #define	TTE_NUM_BUF_BITS_EN		0x0002
430 #define	TTE_ULP_END_BITS_EN		0x003E
431 #define	TTE_ULP_END_EN_BITS_EN		0x0020
432 #define	TTE_UNMAP_ALL_BITS_EN		0x0020
433 #define	TTE_TMODE_BITS_EN		0x0040
434 #define	TTE_SKIP_BITS_EN		0x0040
435 #define	TTE_RING_BASE_ADDR_BITS_EN	0x0FC0
436 #define	TTE_RING_SIZE_BITS_EN		0x0800
437 #define	TTE_BUSY_BITS_EN		0x0800
438 #define	TTE_TOQ_BITS_EN			0x3000
439 
440 #define	TTE_MAPPED_IN_BITS_EN		0x0000F
441 #define	TTE_ANCHOR_SEQ_BITS_EN		0x000F0
442 #define	TTE_ANCHOR_OFFSET_BITS_EN	0x00700
443 #define	TTE_ANCHOR_BUFFER_BITS_EN	0x00800
444 #define	TTE_ANCHOR_BUF_FLAG_BITS_EN	0x00800
445 #define	TTE_UNMAP_ON_LEFT_BITS_EN	0x00800
446 #define	TTE_ULP_END_REACHED_BITS_EN	0x00800
447 #define	TTE_ERR_STAT_BITS_EN		0x01000
448 #define	TTE_WR_PTR_BITS_EN		0x01000
449 #define	TTE_HOQ_BITS_EN			0x0E000
450 #define	TTE_PREFETCH_ON_BITS_EN		0x08000
451 
452 typedef	enum tring_size_e {
453 	TRING_SIZE_8		= 0,
454 	TRING_SIZE_16,
455 	TRING_SIZE_32,
456 	TRING_SIZE_64,
457 	TRING_SIZE_128,
458 	TRING_SIZE_256,
459 	TRING_SIZE_512,
460 	TRING_SIZE_1K,
461 	TRING_SIZE_2K,
462 	TRING_SIZE_4K,
463 	TRING_SIZE_8K,
464 	TRING_SIZE_16K,
465 	TRING_SIZE_32K
466 } tring_size_t;
467 
468 typedef struct tte_dflow_attr_s {
469 	union {
470 		uint64_t value;
471 		struct {
472 #if defined(_BIG_ENDIAN)
473 			uint32_t hdw;
474 #endif
475 			struct {
476 #if defined(_BIT_FIELDS_HTOL)
477 				uint32_t mapped_in;
478 #elif defined(_BIT_FIELDS_LTOH)
479 				uint32_t mapped_in;
480 #endif
481 			} ldw;
482 #if !defined(_BIG_ENDIAN)
483 			uint32_t hdw;
484 #endif
485 		} bits;
486 	} qw0;
487 
488 	union {
489 		uint64_t value;
490 		struct {
491 #if defined(_BIG_ENDIAN)
492 			uint32_t hdw;
493 #endif
494 			struct {
495 #if defined(_BIT_FIELDS_HTOL)
496 				uint32_t anchor_seq;
497 #elif defined(_BIT_FIELDS_LTOH)
498 				uint32_t anchor_seq;
499 #endif
500 			} ldw;
501 #if !defined(_BIG_ENDIAN)
502 			uint32_t hdw;
503 #endif
504 		} bits;
505 	} qw1;
506 
507 	union {
508 		uint64_t value;
509 		struct {
510 #if defined(_BIG_ENDIAN)
511 			uint32_t hdw;
512 #endif
513 			struct {
514 #if defined(_BIT_FIELDS_HTOL)
515 				uint32_t ulp_end_reached;
516 				uint32_t unmap_on_left;
517 				uint32_t anchor_buf_flag;
518 				uint32_t anchor_buf:5;
519 				uint32_t anchor_offset:24;
520 #elif defined(_BIT_FIELDS_LTOH)
521 				uint32_t anchor_offset:24;
522 				uint32_t anchor_buf:5;
523 				uint32_t anchor_buf_flag;
524 				uint32_t unmap_on_left;
525 				uint32_t ulp_end_reached;
526 #endif
527 			} ldw;
528 #if !defined(_BIG_ENDIAN)
529 		uint32_t hdw;
530 #endif
531 		} bits;
532 	} qw2;
533 
534 	union {
535 		uint64_t value;
536 		struct {
537 #if defined(_BIG_ENDIAN)
538 			uint32_t hdw;
539 #endif
540 			struct {
541 #if defined(_BIT_FIELDS_HTOL)
542 				uint32_t rsvd1:1;
543 				uint32_t prefetch_on:1;
544 				uint32_t hoq:16;
545 				uint32_t rsvd:6;
546 				uint32_t wr_ptr:6;
547 				uint32_t err_stat:2;
548 #elif defined(_BIT_FIELDS_LTOH)
549 				uint32_t err_stat:2;
550 				uint32_t wr_ptr:6;
551 				uint32_t rsvd:6;
552 				uint32_t hoq:16;
553 				uint32_t prefetch_on:1;
554 				uint32_t rsvd1:1;
555 #endif
556 			} ldw;
557 #if !defined(_BIG_ENDIAN)
558 			uint32_t hdw;
559 #endif
560 		} bits;
561 	} qw3;
562 
563 	union {
564 		uint64_t value;
565 		struct {
566 #if defined(_BIG_ENDIAN)
567 			uint32_t hdw;
568 #endif
569 			struct {
570 #if defined(_BIT_FIELDS_HTOL)
571 				uint32_t rsvd:28;
572 				uint32_t dat4:4;
573 #elif defined(_BIT_FIELDS_LTOH)
574 				uint32_t dat4:4;
575 				uint32_t rsvd:28;
576 #endif
577 			} ldw;
578 #if !defined(_BIG_ENDIAN)
579 			uint32_t hdw;
580 #endif
581 		} bits;
582 	} qw4;
583 
584 } tte_dflow_attr_t, *tte_dflow_attr_pt;
585 
586 #define	MAX_BAM_BANKS	8
587 
588 typedef	struct zcp_ram_unit_s {
589 	uint32_t	w0;
590 	uint32_t	w1;
591 	uint32_t	w2;
592 	uint32_t	w3;
593 	uint32_t	w4;
594 } zcp_ram_unit_t;
595 
596 typedef	enum dmaw_type_e {
597 	DMAW_NO_CROSS_BUF	= 0,
598 	DMAW_IP_CROSS_BUF_2,
599 	DMAW_IP_CROSS_BUF_3,
600 	DMAW_IP_CROSS_BUF_4
601 } dmaw_type_t;
602 
603 typedef union zcp_ram_data_u {
604 	tte_sflow_attr_t sentry;
605 	tte_dflow_attr_t dentry;
606 } zcp_ram_data_t, *zcp_ram_data_pt;
607 
608 typedef union zcp_ram_access_u {
609 	uint64_t value;
610 	struct {
611 #if defined(_BIG_ENDIAN)
612 		uint32_t hdw;
613 #endif
614 		struct {
615 #if defined(_BIT_FIELDS_HTOL)
616 			uint32_t busy:1;
617 			uint32_t rdwr:1;
618 			uint32_t rsvd:1;
619 			uint32_t zcfid:12;
620 			uint32_t ram_sel:5;
621 			uint32_t cfifo:12;
622 #elif defined(_BIT_FIELDS_LTOH)
623 			uint32_t cfifo:12;
624 			uint32_t ram_sel:5;
625 			uint32_t zcfid:12;
626 			uint32_t rsvd:1;
627 			uint32_t rdwr:1;
628 			uint32_t busy:1;
629 #endif
630 		} ldw;
631 #if !defined(_BIG_ENDIAN)
632 		uint32_t hdw;
633 #endif
634 	} bits;
635 } zcp_ram_access_t, *zcp_ram_access_pt;
636 
637 #define	ZCP_RAM_WR		0
638 #define	ZCP_RAM_RD		1
639 #define	ZCP_RAM_SEL_BAM0	0
640 #define	ZCP_RAM_SEL_BAM1	0x1
641 #define	ZCP_RAM_SEL_BAM2	0x2
642 #define	ZCP_RAM_SEL_BAM3	0x3
643 #define	ZCP_RAM_SEL_BAM4	0x4
644 #define	ZCP_RAM_SEL_BAM5	0x5
645 #define	ZCP_RAM_SEL_BAM6	0x6
646 #define	ZCP_RAM_SEL_BAM7	0x7
647 #define	ZCP_RAM_SEL_TT_STATIC	0x8
648 #define	ZCP_RAM_SEL_TT_DYNAMIC	0x9
649 #define	ZCP_RAM_SEL_CFIFO0	0x10
650 #define	ZCP_RAM_SEL_CFIFO1	0x11
651 #define	ZCP_RAM_SEL_CFIFO2	0x12
652 #define	ZCP_RAM_SEL_CFIFO3	0x13
653 
654 typedef union zcp_ram_benable_u {
655 	uint64_t value;
656 	struct {
657 #if defined(_BIG_ENDIAN)
658 		uint32_t hdw;
659 #endif
660 		struct {
661 #if defined(_BIT_FIELDS_HTOL)
662 			uint32_t rsvd:15;
663 			uint32_t be:17;
664 #elif defined(_BIT_FIELDS_LTOH)
665 			uint32_t be:17;
666 			uint32_t rsvd:15;
667 #endif
668 		} ldw;
669 #if !defined(_BIG_ENDIAN)
670 		uint32_t hdw;
671 #endif
672 	} bits;
673 } zcp_ram_benable_t, *zcp_ram_benable_pt;
674 
675 typedef union zcp_training_vector_u {
676 	uint64_t value;
677 	struct {
678 #if defined(_BIG_ENDIAN)
679 		uint32_t hdw;
680 #endif
681 		struct {
682 #if defined(_BIT_FIELDS_HTOL)
683 			uint32_t train_vec;
684 #elif defined(_BIT_FIELDS_LTOH)
685 			uint32_t train_vec;
686 #endif
687 		} ldw;
688 #if !defined(_BIG_ENDIAN)
689 		uint32_t hdw;
690 #endif
691 	} bits;
692 } zcp_training_vector_t, *zcp_training_vector_pt;
693 
694 typedef union zcp_state_machine_u {
695 	uint64_t value;
696 	struct {
697 #if defined(_BIG_ENDIAN)
698 		uint32_t hdw;
699 #endif
700 		struct {
701 #if defined(_BIT_FIELDS_HTOL)
702 			uint32_t state;
703 #elif defined(_BIT_FIELDS_LTOH)
704 			uint32_t state;
705 #endif
706 		} ldw;
707 #if !defined(_BIG_ENDIAN)
708 		uint32_t hdw;
709 #endif
710 	} bits;
711 } zcp_state_machine_t, *zcp_state_machine_pt;
712 
713 typedef	struct zcp_hdr_s {
714 	uint16_t	zflowid;
715 	uint16_t	tcp_hdr_len;
716 	uint16_t	tcp_payld_len;
717 	uint16_t	head_of_que;
718 	uint32_t	first_b_offset;
719 	boolean_t	reach_buf_end;
720 	dmaw_type_t	dmaw_type;
721 	uint8_t		win_buf_offset;
722 } zcp_hdr_t;
723 
724 typedef	union _zcp_ecc_ctrl {
725 	uint64_t value;
726 
727 	struct {
728 #if defined(_BIG_ENDIAN)
729 		uint32_t	w1;
730 #endif
731 		struct {
732 #if defined(_BIT_FIELDS_HTOL)
733 		uint32_t dis_dbl	: 1;
734 		uint32_t res3		: 13;
735 		uint32_t cor_dbl	: 1;
736 		uint32_t cor_sng	: 1;
737 		uint32_t res2		: 5;
738 		uint32_t cor_all	: 1;
739 		uint32_t res1		: 7;
740 		uint32_t cor_lst	: 1;
741 		uint32_t cor_snd	: 1;
742 		uint32_t cor_fst	: 1;
743 #elif defined(_BIT_FIELDS_LTOH)
744 		uint32_t cor_fst	: 1;
745 		uint32_t cor_snd	: 1;
746 		uint32_t cor_lst	: 1;
747 		uint32_t res1		: 7;
748 		uint32_t cor_all	: 1;
749 		uint32_t res2		: 5;
750 		uint32_t cor_sng	: 1;
751 		uint32_t cor_dbl	: 1;
752 		uint32_t res3		: 13;
753 		uint32_t dis_dbl	: 1;
754 #else
755 #error	one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
756 #endif
757 	} w0;
758 
759 #if !defined(_BIG_ENDIAN)
760 		uint32_t	w1;
761 #endif
762 	} bits;
763 } zcp_ecc_ctrl_t;
764 
765 #ifdef	__cplusplus
766 }
767 #endif
768 
769 #endif	/* _SYS_NXGE_NXGE_ZCP_HW_H */
770