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Searched refs:REG_WRITE (Results 1 – 10 of 10) sorted by relevance

/illumos-gate/usr/src/uts/common/io/arn/
H A Darn_hw.c1279 REG_WRITE(ah, AR_PCU_MISC, in ath9k_hw_init_user_settings()
1479 REG_WRITE(ah, reg, val); in ath9k_hw_process_ini()
1506 REG_WRITE(ah, reg, val); in ath9k_hw_process_ini()
1730 REG_WRITE(ah, AR_RC, 0); in ath9k_hw_set_reset()
2522 REG_WRITE(ah, AR_ISR, ~0); in ath9k_hw_reset()
2559 REG_WRITE(ah, AR_STA_ID1, in ath9k_hw_reset()
2564 REG_WRITE(ah, AR_OBS, 8); in ath9k_hw_reset()
3401 REG_WRITE(ah, AR_SLEEP1, in ath9k_hw_set_sta_beacon_timers()
3410 REG_WRITE(ah, AR_SLEEP2, in ath9k_hw_set_sta_beacon_timers()
3966 REG_WRITE(ah, AR_RXCFG, in ath9k_hw_setrxfilter()
[all …]
H A Darn_ani.c612 REG_WRITE(ah, AR_PHY_ERR_1, in ath9k_hw_ani_monitor()
623 REG_WRITE(ah, AR_PHY_ERR_2, in ath9k_hw_ani_monitor()
683 REG_WRITE(ah, AR_FILT_OFDM, 0); in ath9k_enable_mib_counters()
684 REG_WRITE(ah, AR_FILT_CCK, 0); in ath9k_enable_mib_counters()
685 REG_WRITE(ah, AR_MIBC, in ath9k_enable_mib_counters()
704 REG_WRITE(ah, AR_FILT_OFDM, 0); in ath9k_hw_disable_mib_counters()
705 REG_WRITE(ah, AR_FILT_CCK, 0); in ath9k_hw_disable_mib_counters()
761 REG_WRITE(ah, AR_FILT_OFDM, 0); in ath9k_hw_procmibevent()
762 REG_WRITE(ah, AR_FILT_CCK, 0); in ath9k_hw_procmibevent()
888 REG_WRITE(ah, AR_PHY_ERR_1, 0); in ath9k_hw_ani_detach()
[all …]
H A Darn_mac.c42 REG_WRITE(ah, AR_IMR_S0, in ath9k_hw_set_txq_interrupts()
45 REG_WRITE(ah, AR_IMR_S1, in ath9k_hw_set_txq_interrupts()
60 REG_WRITE(ah, AR_MACMISC, in ath9k_hw_dmaRegDump()
187 REG_WRITE(ah, AR_TXCFG, in ath9k_hw_updatetxtriglevel()
251 REG_WRITE(ah, AR_Q_TXD, 0); in ath9k_hw_stoptxdma()
834 REG_WRITE(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
841 REG_WRITE(ah, AR_QMISC(q), in ath9k_hw_resettxqueue()
858 REG_WRITE(ah, AR_QMISC(q), in ath9k_hw_resettxqueue()
865 REG_WRITE(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
870 REG_WRITE(ah, AR_DMISC(q), in ath9k_hw_resettxqueue()
[all …]
H A Darn_calib.c694 REG_WRITE(ah, ar5416_cca_regs[i], val); in ath9k_hw_loadnf()
716 REG_WRITE(ah, ar5416_cca_regs[i], val); in ath9k_hw_loadnf()
885 REG_WRITE(ah, 0x7834, regVal); in ath9k_hw_9285_pa_cal()
888 REG_WRITE(ah, 0x9808, regVal); in ath9k_hw_9285_pa_cal()
905 REG_WRITE(ah, AR9285_AN_TOP2, 0xca0358a0); in ath9k_hw_9285_pa_cal()
913 REG_WRITE(ah, 0x7834, regVal); in ath9k_hw_9285_pa_cal()
919 REG_WRITE(ah, 0x7834, regVal); in ath9k_hw_9285_pa_cal()
939 REG_WRITE(ah, 0x7834, regVal); in ath9k_hw_9285_pa_cal()
942 REG_WRITE(ah, 0x9808, regVal); in ath9k_hw_9285_pa_cal()
961 REG_WRITE(ah, AR_PHY_AGC_CONTROL, in ath9k_hw_init_cal()
[all …]
H A Darn_phy.c72 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ath9k_hw_set_channel()
75 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ath9k_hw_set_channel()
102 REG_WRITE(ah, AR_PHY(0x37), reg32); in ath9k_hw_set_channel()
137 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ath9k_hw_ar9280_set_channel()
140 REG_WRITE(ah, AR_PHY_CCK_TX_CTRL, in ath9k_hw_ar9280_set_channel()
173 REG_WRITE(ah, AR_PHY_SYNTH_CONTROL, reg32); in ath9k_hw_ar9280_set_channel()
431 REG_WRITE(ah, AR_PHY_BASE + 0xD8, bank6SelMask); in ath9k_hw_decrease_chain_power()
445 REG_WRITE(ah, AR_PHY_BASE + 0xD8, 0x00000053); in ath9k_hw_decrease_chain_power()
447 REG_WRITE(ah, PHY_SWITCH_CHAIN_0, in ath9k_hw_decrease_chain_power()
H A Darn_eeprom.c69 REG_WRITE(ah, reg, regVal); in ath9k_hw_analog_shift_rmw()
1108 REG_WRITE(ah, in ath9k_hw_set_def_power_cal_table()
1927 REG_WRITE(ah, AR_PHY_POWER_TX_SUB, in ath9k_hw_def_set_txpower()
2270 REG_WRITE(ah, in ath9k_hw_eeprom_set_def_board_values()
2280 REG_WRITE(ah, in ath9k_hw_eeprom_set_def_board_values()
2303 REG_WRITE(ah, in ath9k_hw_eeprom_set_def_board_values()
2311 REG_WRITE(ah, in ath9k_hw_eeprom_set_def_board_values()
2386 REG_WRITE(ah, AR_PHY_RF_CTL4, in ath9k_hw_eeprom_set_def_board_values()
2494 REG_WRITE(ah, 0x99ac, regVal); in ath9k_hw_eeprom_set_4k_board_values()
2499 REG_WRITE(ah, 0xa208, regVal); in ath9k_hw_eeprom_set_4k_board_values()
[all …]
H A Darn_ath9k.h612 #define REG_WRITE(_ah, _reg, _val) arn_iowrite32((_ah), (_reg), (_val)) macro
621 REG_WRITE(_a, _r, (REG_READ(_a, _r) & ~(_clr)) | (_set))
623 REG_WRITE(_a, _r, \
626 REG_WRITE(_a, _r, REG_READ(_a, _r) | _f)
628 REG_WRITE(_a, _r, REG_READ(_a, _r) & ~_f)
H A Darn_phy.h529 REG_WRITE(ah, INI_RA((iniarray), r, 0), (regData)[r]); \
H A Darn_hw.h988 REG_WRITE(ah, INI_RA((iniarray), (r), 0), \
/illumos-gate/usr/src/uts/common/io/qede/579xx/hsi/hw/
H A Dmisc_bits.h256 REG_WRITE(path, _reg_ ## _CLEAR, _bits_); \
257 REG_WRITE(path, _reg_ ## _SET, _bits_); \