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Searched refs:PN_L3_LINESIZE (Results 1 – 4 of 4) sorted by relevance

/illumos-gate/usr/src/uts/sun4u/io/
H A Dgptwo_cpu.c851 "l3-cache-line-size", PN_L3_LINESIZE) != DDI_SUCCESS) { in set_cpu_us4_props()
H A Dmem_cache.c577 (PN_L3_SET_SIZE/PN_L3_LINESIZE)) in mem_cache_ioctl_ops()
/illumos-gate/usr/src/uts/sun4u/sys/
H A Dcheetahregs.h653 #define PN_L3_LINESIZE 64 macro
/illumos-gate/usr/src/uts/sun4u/cpu/
H A Dus3_cheetahplus.c153 ecache_alignsize = PN_L3_LINESIZE; in cpu_fix_allpanther()