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Searched refs:MI_NO_WRITE_FLUSH (Results 1 – 3 of 3) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Dintel_ringbuffer.c68 cmd |= MI_NO_WRITE_FLUSH; in gen2_render_ring_flush()
121 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; in gen4_render_ring_flush()
123 cmd &= ~MI_NO_WRITE_FLUSH; in gen4_render_ring_flush()
H A Di915_dma.c533 OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP); in i915_dispatch_batchbuffer()
H A Di915_reg.h281 #define MI_NO_WRITE_FLUSH (1 << 2) macro