1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (C) 2003-2005 Chelsio Communications.  All rights reserved.
24  */
25 
26 /*
27  * FPGA specific definitions
28  */
29 
30 #ifndef __CHELSIO_FPGA_DEFS_H__
31 #define __CHELSIO_FPGA_DEFS_H__
32 
33 #define FPGA_PCIX_ADDR_VERSION               0xA08
34 #define FPGA_PCIX_ADDR_STAT                  0xA0C
35 
36 /* FPGA master interrupt Cause/Enable bits */
37 #define FPGA_PCIX_INTERRUPT_SGE_ERROR        0x1
38 #define FPGA_PCIX_INTERRUPT_SGE_DATA         0x2
39 #define FPGA_PCIX_INTERRUPT_TP               0x4
40 #define FPGA_PCIX_INTERRUPT_MC3              0x8
41 #define FPGA_PCIX_INTERRUPT_GMAC             0x10
42 #define FPGA_PCIX_INTERRUPT_PCIX             0x20
43 
44 /* TP interrupt register addresses */
45 #define FPGA_TP_ADDR_INTERRUPT_ENABLE        0xA10
46 #define FPGA_TP_ADDR_INTERRUPT_CAUSE         0xA14
47 #define FPGA_TP_ADDR_VERSION                 0xA18
48 
49 /* TP interrupt Cause/Enable bits */
50 #define FPGA_TP_INTERRUPT_MC4                0x1
51 #define FPGA_TP_INTERRUPT_MC5                0x2
52 
53 /*
54  * PM interrupt register addresses
55  */
56 #define FPGA_MC3_REG_INTRENABLE              0xA20
57 #define FPGA_MC3_REG_INTRCAUSE               0xA24
58 #define FPGA_MC3_REG_VERSION                 0xA28
59 
60 /*
61  * GMAC interrupt register addresses
62  */
63 #define FPGA_GMAC_ADDR_INTERRUPT_ENABLE      0xA30
64 #define FPGA_GMAC_ADDR_INTERRUPT_CAUSE       0xA34
65 #define FPGA_GMAC_ADDR_VERSION               0xA38
66 
67 /* GMAC Cause/Enable bits */
68 #define FPGA_GMAC_INTERRUPT_PORT0            0x1
69 #define FPGA_GMAC_INTERRUPT_PORT1            0x2
70 #define FPGA_GMAC_INTERRUPT_PORT2            0x4
71 #define FPGA_GMAC_INTERRUPT_PORT3            0x8
72 
73 /* MI0 registers */
74 #define A_MI0_CLK 0xb00
75 
76 #define S_MI0_CLK_DIV    0
77 #define M_MI0_CLK_DIV    0xff
78 #define V_MI0_CLK_DIV(x) ((x) << S_MI0_CLK_DIV)
79 #define G_MI0_CLK_DIV(x) (((x) >> S_MI0_CLK_DIV) & M_MI0_CLK_DIV)
80 
81 #define S_MI0_CLK_CNT    8
82 #define M_MI0_CLK_CNT    0xff
83 #define V_MI0_CLK_CNT(x) ((x) << S_MI0_CLK_CNT)
84 #define G_MI0_CLK_CNT(x) (((x) >> S_MI0_CLK_CNT) & M_MI0_CLK_CNT)
85 
86 #define A_MI0_CSR 0xb04
87 
88 #define S_MI0_CSR_POLL    0
89 #define V_MI0_CSR_POLL(x) ((x) << S_MI0_CSR_POLL)
90 #define F_MI0_CSR_POLL    V_MI0_CSR_POLL(1U)
91 
92 #define S_MI0_PREAMBLE    1
93 #define V_MI0_PREAMBLE(x) ((x) << S_MI0_PREAMBLE)
94 #define F_MI0_PREAMBLE    V_MI0_PREAMBLE(1U)
95 
96 #define S_MI0_INTR_ENABLE    2
97 #define V_MI0_INTR_ENABLE(x) ((x) << S_MI0_INTR_ENABLE)
98 #define F_MI0_INTR_ENABLE    V_MI0_INTR_ENABLE(1U)
99 
100 #define S_MI0_BUSY    3
101 #define V_MI0_BUSY(x) ((x) << S_MI0_BUSY)
102 #define F_MI0_BUSY    V_MI0_BUSY(1U)
103 
104 #define S_MI0_MDIO    4
105 #define V_MI0_MDIO(x) ((x) << S_MI0_MDIO)
106 #define F_MI0_MDIO    V_MI0_MDIO(1U)
107 
108 #define A_MI0_ADDR 0xb08
109 
110 #define S_MI0_PHY_REG_ADDR    0
111 #define M_MI0_PHY_REG_ADDR    0x1f
112 #define V_MI0_PHY_REG_ADDR(x) ((x) << S_MI0_PHY_REG_ADDR)
113 #define G_MI0_PHY_REG_ADDR(x) (((x) >> S_MI0_PHY_REG_ADDR) & M_MI0_PHY_REG_ADDR)
114 
115 #define S_MI0_PHY_ADDR    5
116 #define M_MI0_PHY_ADDR    0x1f
117 #define V_MI0_PHY_ADDR(x) ((x) << S_MI0_PHY_ADDR)
118 #define G_MI0_PHY_ADDR(x) (((x) >> S_MI0_PHY_ADDR) & M_MI0_PHY_ADDR)
119 
120 #define A_MI0_DATA_EXT 0xb0c
121 #define A_MI0_DATA_INT 0xb10
122 
123 /* GMAC registers */
124 #define A_GMAC_MACID_LO 0x28
125 #define A_GMAC_MACID_HI 0x2c
126 #define A_GMAC_CSR 0x30
127 
128 #define S_INTERFACE    0
129 #define M_INTERFACE    0x3
130 #define V_INTERFACE(x) ((x) << S_INTERFACE)
131 #define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE)
132 
133 #define S_MAC_TX_ENABLE    2
134 #define V_MAC_TX_ENABLE(x) ((x) << S_MAC_TX_ENABLE)
135 #define F_MAC_TX_ENABLE    V_MAC_TX_ENABLE(1U)
136 
137 #define S_MAC_RX_ENABLE    3
138 #define V_MAC_RX_ENABLE(x) ((x) << S_MAC_RX_ENABLE)
139 #define F_MAC_RX_ENABLE    V_MAC_RX_ENABLE(1U)
140 
141 #define S_MAC_LB_ENABLE    4
142 #define V_MAC_LB_ENABLE(x) ((x) << S_MAC_LB_ENABLE)
143 #define F_MAC_LB_ENABLE    V_MAC_LB_ENABLE(1U)
144 
145 #define S_MAC_SPEED    5
146 #define M_MAC_SPEED    0x3
147 #define V_MAC_SPEED(x) ((x) << S_MAC_SPEED)
148 #define G_MAC_SPEED(x) (((x) >> S_MAC_SPEED) & M_MAC_SPEED)
149 
150 #define S_MAC_HD_FC_ENABLE    7
151 #define V_MAC_HD_FC_ENABLE(x) ((x) << S_MAC_HD_FC_ENABLE)
152 #define F_MAC_HD_FC_ENABLE    V_MAC_HD_FC_ENABLE(1U)
153 
154 #define S_MAC_HALF_DUPLEX    8
155 #define V_MAC_HALF_DUPLEX(x) ((x) << S_MAC_HALF_DUPLEX)
156 #define F_MAC_HALF_DUPLEX    V_MAC_HALF_DUPLEX(1U)
157 
158 #define S_MAC_PROMISC    9
159 #define V_MAC_PROMISC(x) ((x) << S_MAC_PROMISC)
160 #define F_MAC_PROMISC    V_MAC_PROMISC(1U)
161 
162 #define S_MAC_MC_ENABLE    10
163 #define V_MAC_MC_ENABLE(x) ((x) << S_MAC_MC_ENABLE)
164 #define F_MAC_MC_ENABLE    V_MAC_MC_ENABLE(1U)
165 
166 #define S_MAC_RESET    11
167 #define V_MAC_RESET(x) ((x) << S_MAC_RESET)
168 #define F_MAC_RESET    V_MAC_RESET(1U)
169 
170 #define S_MAC_RX_PAUSE_ENABLE    12
171 #define V_MAC_RX_PAUSE_ENABLE(x) ((x) << S_MAC_RX_PAUSE_ENABLE)
172 #define F_MAC_RX_PAUSE_ENABLE    V_MAC_RX_PAUSE_ENABLE(1U)
173 
174 #define S_MAC_TX_PAUSE_ENABLE    13
175 #define V_MAC_TX_PAUSE_ENABLE(x) ((x) << S_MAC_TX_PAUSE_ENABLE)
176 #define F_MAC_TX_PAUSE_ENABLE    V_MAC_TX_PAUSE_ENABLE(1U)
177 
178 #define S_MAC_LWM_ENABLE    14
179 #define V_MAC_LWM_ENABLE(x) ((x) << S_MAC_LWM_ENABLE)
180 #define F_MAC_LWM_ENABLE    V_MAC_LWM_ENABLE(1U)
181 
182 #define S_MAC_MAGIC_PKT_ENABLE    15
183 #define V_MAC_MAGIC_PKT_ENABLE(x) ((x) << S_MAC_MAGIC_PKT_ENABLE)
184 #define F_MAC_MAGIC_PKT_ENABLE    V_MAC_MAGIC_PKT_ENABLE(1U)
185 
186 #define S_MAC_ISL_ENABLE    16
187 #define V_MAC_ISL_ENABLE(x) ((x) << S_MAC_ISL_ENABLE)
188 #define F_MAC_ISL_ENABLE    V_MAC_ISL_ENABLE(1U)
189 
190 #define S_MAC_JUMBO_ENABLE    17
191 #define V_MAC_JUMBO_ENABLE(x) ((x) << S_MAC_JUMBO_ENABLE)
192 #define F_MAC_JUMBO_ENABLE    V_MAC_JUMBO_ENABLE(1U)
193 
194 #define S_MAC_RX_PAD_ENABLE    18
195 #define V_MAC_RX_PAD_ENABLE(x) ((x) << S_MAC_RX_PAD_ENABLE)
196 #define F_MAC_RX_PAD_ENABLE    V_MAC_RX_PAD_ENABLE(1U)
197 
198 #define S_MAC_RX_CRC_ENABLE    19
199 #define V_MAC_RX_CRC_ENABLE(x) ((x) << S_MAC_RX_CRC_ENABLE)
200 #define F_MAC_RX_CRC_ENABLE    V_MAC_RX_CRC_ENABLE(1U)
201 
202 #define A_GMAC_IFS 0x34
203 
204 #define S_MAC_IFS2    0
205 #define M_MAC_IFS2    0x3f
206 #define V_MAC_IFS2(x) ((x) << S_MAC_IFS2)
207 #define G_MAC_IFS2(x) (((x) >> S_MAC_IFS2) & M_MAC_IFS2)
208 
209 #define S_MAC_IFS1    8
210 #define M_MAC_IFS1    0x7f
211 #define V_MAC_IFS1(x) ((x) << S_MAC_IFS1)
212 #define G_MAC_IFS1(x) (((x) >> S_MAC_IFS1) & M_MAC_IFS1)
213 
214 #define A_GMAC_JUMBO_FRAME_LEN 0x38
215 #define A_GMAC_LNK_DLY 0x3c
216 #define A_GMAC_PAUSETIME 0x40
217 #define A_GMAC_MCAST_LO 0x44
218 #define A_GMAC_MCAST_HI 0x48
219 #define A_GMAC_MCAST_MASK_LO 0x4c
220 #define A_GMAC_MCAST_MASK_HI 0x50
221 #define A_GMAC_RMT_CNT 0x54
222 #define A_GMAC_RMT_DATA 0x58
223 #define A_GMAC_BACKOFF_SEED 0x5c
224 #define A_GMAC_TXF_THRES 0x60
225 
226 #define S_TXF_READ_THRESHOLD    0
227 #define M_TXF_READ_THRESHOLD    0xff
228 #define V_TXF_READ_THRESHOLD(x) ((x) << S_TXF_READ_THRESHOLD)
229 #define G_TXF_READ_THRESHOLD(x) (((x) >> S_TXF_READ_THRESHOLD) & M_TXF_READ_THRESHOLD)
230 
231 #define S_TXF_WRITE_THRESHOLD    16
232 #define M_TXF_WRITE_THRESHOLD    0xff
233 #define V_TXF_WRITE_THRESHOLD(x) ((x) << S_TXF_WRITE_THRESHOLD)
234 #define G_TXF_WRITE_THRESHOLD(x) (((x) >> S_TXF_WRITE_THRESHOLD) & M_TXF_WRITE_THRESHOLD)
235 
236 #define MAC_REG_BASE 0x600
237 #define MAC_REG_ADDR(idx, reg) (MAC_REG_BASE + (idx) * 128 + (reg))
238 
239 #define MAC_REG_IDLO(idx)              MAC_REG_ADDR(idx, A_GMAC_MACID_LO)
240 #define MAC_REG_IDHI(idx)              MAC_REG_ADDR(idx, A_GMAC_MACID_HI)
241 #define MAC_REG_CSR(idx)               MAC_REG_ADDR(idx, A_GMAC_CSR)
242 #define MAC_REG_IFS(idx)               MAC_REG_ADDR(idx, A_GMAC_IFS)
243 #define MAC_REG_LARGEFRAMELENGTH(idx) MAC_REG_ADDR(idx, A_GMAC_JUMBO_FRAME_LEN)
244 #define MAC_REG_LINKDLY(idx)           MAC_REG_ADDR(idx, A_GMAC_LNK_DLY)
245 #define MAC_REG_PAUSETIME(idx)         MAC_REG_ADDR(idx, A_GMAC_PAUSETIME)
246 #define MAC_REG_CASTLO(idx)            MAC_REG_ADDR(idx, A_GMAC_MCAST_LO)
247 #define MAC_REG_MCASTHI(idx)           MAC_REG_ADDR(idx, A_GMAC_MCAST_HI)
248 #define MAC_REG_CASTMASKLO(idx)        MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_LO)
249 #define MAC_REG_MCASTMASKHI(idx)       MAC_REG_ADDR(idx, A_GMAC_MCAST_MASK_HI)
250 #define MAC_REG_RMCNT(idx)             MAC_REG_ADDR(idx, A_GMAC_RMT_CNT)
251 #define MAC_REG_RMDATA(idx)            MAC_REG_ADDR(idx, A_GMAC_RMT_DATA)
252 #define MAC_REG_GMRANDBACKOFFSEED(idx) MAC_REG_ADDR(idx, A_GMAC_BACKOFF_SEED)
253 #define MAC_REG_TXFTHRESHOLDS(idx)     MAC_REG_ADDR(idx, A_GMAC_TXF_THRES)
254 
255 #endif
256