xref: /illumos-gate/usr/src/contrib/bhyve/x86/apicreg.h (revision d0b3c59b)
1 /*-
2  * Copyright (c) 1996, by Peter Wemm and Steve Passe
3  * All rights reserved.
4  *
5  * Redistribution and use in source and binary forms, with or without
6  * modification, are permitted provided that the following conditions
7  * are met:
8  * 1. Redistributions of source code must retain the above copyright
9  *    notice, this list of conditions and the following disclaimer.
10  * 2. The name of the developer may NOT be used to endorse or promote products
11  *    derived from this software without specific prior written permission.
12  *
13  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
14  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
15  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
16  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
17  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
18  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
19  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
20  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
21  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23  * SUCH DAMAGE.
24  *
25  * $FreeBSD: head/sys/x86/include/apicreg.h 259140 2013-12-09 21:08:52Z jhb $
26  */
27 
28 #ifndef _X86_APICREG_H_
29 #define _X86_APICREG_H_
30 
31 /*
32  * Local && I/O APIC definitions.
33  */
34 
35 /*
36  * Pentium P54C+ Built-in APIC
37  * (Advanced programmable Interrupt Controller)
38  *
39  * Base Address of Built-in APIC in memory location
40  * is 0xfee00000.
41  *
42  * Map of APIC Registers:
43  *
44  * Offset (hex)    Description                     Read/Write state
45  * 000             Reserved
46  * 010             Reserved
47  * 020 ID          Local APIC ID                   R/W
48  * 030 VER         Local APIC Version              R
49  * 040             Reserved
50  * 050             Reserved
51  * 060             Reserved
52  * 070             Reserved
53  * 080             Task Priority Register          R/W
54  * 090             Arbitration Priority Register   R
55  * 0A0             Processor Priority Register     R
56  * 0B0             EOI Register                    W
57  * 0C0 RRR         Remote read                     R
58  * 0D0             Logical Destination             R/W
59  * 0E0             Destination Format Register     0..27 R;  28..31 R/W
60  * 0F0 SVR         Spurious Interrupt Vector Reg.  0..3  R;  4..9   R/W
61  * 100             ISR  000-031                    R
62  * 110             ISR  032-063                    R
63  * 120             ISR  064-095                    R
64  * 130             ISR  095-128                    R
65  * 140             ISR  128-159                    R
66  * 150             ISR  160-191                    R
67  * 160             ISR  192-223                    R
68  * 170             ISR  224-255                    R
69  * 180             TMR  000-031                    R
70  * 190             TMR  032-063                    R
71  * 1A0             TMR  064-095                    R
72  * 1B0             TMR  095-128                    R
73  * 1C0             TMR  128-159                    R
74  * 1D0             TMR  160-191                    R
75  * 1E0             TMR  192-223                    R
76  * 1F0             TMR  224-255                    R
77  * 200             IRR  000-031                    R
78  * 210             IRR  032-063                    R
79  * 220             IRR  064-095                    R
80  * 230             IRR  095-128                    R
81  * 240             IRR  128-159                    R
82  * 250             IRR  160-191                    R
83  * 260             IRR  192-223                    R
84  * 270             IRR  224-255                    R
85  * 280             Error Status Register           R
86  * 290             Reserved
87  * 2A0             Reserved
88  * 2B0             Reserved
89  * 2C0             Reserved
90  * 2D0             Reserved
91  * 2E0             Reserved
92  * 2F0             Local Vector Table (CMCI)       R/W
93  * 300 ICR_LOW     Interrupt Command Reg. (0-31)   R/W
94  * 310 ICR_HI      Interrupt Command Reg. (32-63)  R/W
95  * 320             Local Vector Table (Timer)      R/W
96  * 330             Local Vector Table (Thermal)    R/W (PIV+)
97  * 340             Local Vector Table (Performance) R/W (P6+)
98  * 350 LVT1        Local Vector Table (LINT0)      R/W
99  * 360 LVT2        Local Vector Table (LINT1)      R/W
100  * 370 LVT3        Local Vector Table (ERROR)      R/W
101  * 380             Initial Count Reg. for Timer    R/W
102  * 390             Current Count of Timer          R
103  * 3A0             Reserved
104  * 3B0             Reserved
105  * 3C0             Reserved
106  * 3D0             Reserved
107  * 3E0             Timer Divide Configuration Reg. R/W
108  * 3F0             Reserved
109  */
110 
111 
112 /******************************************************************************
113  * global defines, etc.
114  */
115 
116 
117 /******************************************************************************
118  * LOCAL APIC structure
119  */
120 
121 #ifndef LOCORE
122 #include <sys/types.h>
123 
124 #define PAD3	int : 32; int : 32; int : 32
125 #define PAD4	int : 32; int : 32; int : 32; int : 32
126 
127 struct LAPIC {
128 	/* reserved */		PAD4;
129 	/* reserved */		PAD4;
130 	u_int32_t id;		PAD3;
131 	u_int32_t version;	PAD3;
132 	/* reserved */		PAD4;
133 	/* reserved */		PAD4;
134 	/* reserved */		PAD4;
135 	/* reserved */		PAD4;
136 	u_int32_t tpr;		PAD3;
137 	u_int32_t apr;		PAD3;
138 	u_int32_t ppr;		PAD3;
139 	u_int32_t eoi;		PAD3;
140 	/* reserved */		PAD4;
141 	u_int32_t ldr;		PAD3;
142 	u_int32_t dfr;		PAD3;
143 	u_int32_t svr;		PAD3;
144 	u_int32_t isr0;		PAD3;
145 	u_int32_t isr1;		PAD3;
146 	u_int32_t isr2;		PAD3;
147 	u_int32_t isr3;		PAD3;
148 	u_int32_t isr4;		PAD3;
149 	u_int32_t isr5;		PAD3;
150 	u_int32_t isr6;		PAD3;
151 	u_int32_t isr7;		PAD3;
152 	u_int32_t tmr0;		PAD3;
153 	u_int32_t tmr1;		PAD3;
154 	u_int32_t tmr2;		PAD3;
155 	u_int32_t tmr3;		PAD3;
156 	u_int32_t tmr4;		PAD3;
157 	u_int32_t tmr5;		PAD3;
158 	u_int32_t tmr6;		PAD3;
159 	u_int32_t tmr7;		PAD3;
160 	u_int32_t irr0;		PAD3;
161 	u_int32_t irr1;		PAD3;
162 	u_int32_t irr2;		PAD3;
163 	u_int32_t irr3;		PAD3;
164 	u_int32_t irr4;		PAD3;
165 	u_int32_t irr5;		PAD3;
166 	u_int32_t irr6;		PAD3;
167 	u_int32_t irr7;		PAD3;
168 	u_int32_t esr;		PAD3;
169 	/* reserved */		PAD4;
170 	/* reserved */		PAD4;
171 	/* reserved */		PAD4;
172 	/* reserved */		PAD4;
173 	/* reserved */		PAD4;
174 	/* reserved */		PAD4;
175 	u_int32_t lvt_cmci;	PAD3;
176 	u_int32_t icr_lo;	PAD3;
177 	u_int32_t icr_hi;	PAD3;
178 	u_int32_t lvt_timer;	PAD3;
179 	u_int32_t lvt_thermal;	PAD3;
180 	u_int32_t lvt_pcint;	PAD3;
181 	u_int32_t lvt_lint0;	PAD3;
182 	u_int32_t lvt_lint1;	PAD3;
183 	u_int32_t lvt_error;	PAD3;
184 	u_int32_t icr_timer;	PAD3;
185 	u_int32_t ccr_timer;	PAD3;
186 	/* reserved */		PAD4;
187 	/* reserved */		PAD4;
188 	/* reserved */		PAD4;
189 	/* reserved */		PAD4;
190 	u_int32_t dcr_timer;	PAD3;
191 	/* reserved */		PAD4;
192 };
193 
194 typedef struct LAPIC lapic_t;
195 
196 /******************************************************************************
197  * I/O APIC structure
198  */
199 
200 struct IOAPIC {
201 	u_int32_t ioregsel;	PAD3;
202 	u_int32_t iowin;	PAD3;
203 };
204 
205 typedef struct IOAPIC ioapic_t;
206 
207 #undef PAD4
208 #undef PAD3
209 
210 #endif  /* !LOCORE */
211 
212 
213 /******************************************************************************
214  * various code 'logical' values
215  */
216 
217 /******************************************************************************
218  * LOCAL APIC defines
219  */
220 
221 /* default physical locations of LOCAL (CPU) APICs */
222 #define DEFAULT_APIC_BASE	0xfee00000
223 
224 /* constants relating to APIC ID registers */
225 #define APIC_ID_MASK		0xff000000
226 #define	APIC_ID_SHIFT		24
227 #define	APIC_ID_CLUSTER		0xf0
228 #define	APIC_ID_CLUSTER_ID	0x0f
229 #define	APIC_MAX_CLUSTER	0xe
230 #define	APIC_MAX_INTRACLUSTER_ID 3
231 #define	APIC_ID_CLUSTER_SHIFT	4
232 
233 /* fields in VER */
234 #define APIC_VER_VERSION	0x000000ff
235 #define APIC_VER_MAXLVT		0x00ff0000
236 #define MAXLVTSHIFT		16
237 #define APIC_VER_EOI_SUPPRESSION 0x01000000
238 
239 /* fields in LDR */
240 #define	APIC_LDR_RESERVED	0x00ffffff
241 
242 /* fields in DFR */
243 #define	APIC_DFR_RESERVED	0x0fffffff
244 #define	APIC_DFR_MODEL_MASK	0xf0000000
245 #define	APIC_DFR_MODEL_FLAT	0xf0000000
246 #define	APIC_DFR_MODEL_CLUSTER	0x00000000
247 
248 /* fields in SVR */
249 #define APIC_SVR_VECTOR		0x000000ff
250 #define APIC_SVR_VEC_PROG	0x000000f0
251 #define APIC_SVR_VEC_FIX	0x0000000f
252 #define APIC_SVR_ENABLE		0x00000100
253 # define APIC_SVR_SWDIS		0x00000000
254 # define APIC_SVR_SWEN		0x00000100
255 #define APIC_SVR_FOCUS		0x00000200
256 # define APIC_SVR_FEN		0x00000000
257 # define APIC_SVR_FDIS		0x00000200
258 #define APIC_SVR_EOI_SUPPRESSION 0x00001000
259 
260 /* fields in TPR */
261 #define APIC_TPR_PRIO		0x000000ff
262 # define APIC_TPR_INT		0x000000f0
263 # define APIC_TPR_SUB		0x0000000f
264 
265 /* fields in ESR */
266 #define	APIC_ESR_SEND_CS_ERROR		0x00000001
267 #define	APIC_ESR_RECEIVE_CS_ERROR	0x00000002
268 #define	APIC_ESR_SEND_ACCEPT		0x00000004
269 #define	APIC_ESR_RECEIVE_ACCEPT		0x00000008
270 #define	APIC_ESR_SEND_ILLEGAL_VECTOR	0x00000020
271 #define	APIC_ESR_RECEIVE_ILLEGAL_VECTOR	0x00000040
272 #define	APIC_ESR_ILLEGAL_REGISTER	0x00000080
273 
274 /* fields in ICR_LOW */
275 #define APIC_VECTOR_MASK	0x000000ff
276 
277 #define APIC_DELMODE_MASK	0x00000700
278 # define APIC_DELMODE_FIXED	0x00000000
279 # define APIC_DELMODE_LOWPRIO	0x00000100
280 # define APIC_DELMODE_SMI	0x00000200
281 # define APIC_DELMODE_RR	0x00000300
282 # define APIC_DELMODE_NMI	0x00000400
283 # define APIC_DELMODE_INIT	0x00000500
284 # define APIC_DELMODE_STARTUP	0x00000600
285 # define APIC_DELMODE_RESV	0x00000700
286 
287 #define APIC_DESTMODE_MASK	0x00000800
288 # define APIC_DESTMODE_PHY	0x00000000
289 # define APIC_DESTMODE_LOG	0x00000800
290 
291 #define APIC_DELSTAT_MASK	0x00001000
292 # define APIC_DELSTAT_IDLE	0x00000000
293 # define APIC_DELSTAT_PEND	0x00001000
294 
295 #define APIC_RESV1_MASK		0x00002000
296 
297 #define APIC_LEVEL_MASK		0x00004000
298 # define APIC_LEVEL_DEASSERT	0x00000000
299 # define APIC_LEVEL_ASSERT	0x00004000
300 
301 #define APIC_TRIGMOD_MASK	0x00008000
302 # define APIC_TRIGMOD_EDGE	0x00000000
303 # define APIC_TRIGMOD_LEVEL	0x00008000
304 
305 #define APIC_RRSTAT_MASK	0x00030000
306 # define APIC_RRSTAT_INVALID	0x00000000
307 # define APIC_RRSTAT_INPROG	0x00010000
308 # define APIC_RRSTAT_VALID	0x00020000
309 # define APIC_RRSTAT_RESV	0x00030000
310 
311 #define APIC_DEST_MASK		0x000c0000
312 # define APIC_DEST_DESTFLD	0x00000000
313 # define APIC_DEST_SELF		0x00040000
314 # define APIC_DEST_ALLISELF	0x00080000
315 # define APIC_DEST_ALLESELF	0x000c0000
316 
317 #define APIC_RESV2_MASK		0xfff00000
318 
319 #define	APIC_ICRLO_RESV_MASK	(APIC_RESV1_MASK | APIC_RESV2_MASK)
320 
321 /* fields in LVT1/2 */
322 #define APIC_LVT_VECTOR		0x000000ff
323 #define APIC_LVT_DM		0x00000700
324 # define APIC_LVT_DM_FIXED	0x00000000
325 # define APIC_LVT_DM_SMI	0x00000200
326 # define APIC_LVT_DM_NMI	0x00000400
327 # define APIC_LVT_DM_INIT	0x00000500
328 # define APIC_LVT_DM_EXTINT	0x00000700
329 #define APIC_LVT_DS		0x00001000
330 #define APIC_LVT_IIPP		0x00002000
331 #define APIC_LVT_IIPP_INTALO	0x00002000
332 #define APIC_LVT_IIPP_INTAHI	0x00000000
333 #define APIC_LVT_RIRR		0x00004000
334 #define APIC_LVT_TM		0x00008000
335 #define APIC_LVT_M		0x00010000
336 
337 
338 /* fields in LVT Timer */
339 #define APIC_LVTT_VECTOR	0x000000ff
340 #define APIC_LVTT_DS		0x00001000
341 #define APIC_LVTT_M		0x00010000
342 #define APIC_LVTT_TM		0x00020000
343 # define APIC_LVTT_TM_ONE_SHOT	0x00000000
344 # define APIC_LVTT_TM_PERIODIC	0x00020000
345 
346 
347 /* APIC timer current count */
348 #define	APIC_TIMER_MAX_COUNT	0xffffffff
349 
350 /* fields in TDCR */
351 #define APIC_TDCR_2		0x00
352 #define APIC_TDCR_4		0x01
353 #define APIC_TDCR_8		0x02
354 #define APIC_TDCR_16		0x03
355 #define APIC_TDCR_32		0x08
356 #define APIC_TDCR_64		0x09
357 #define APIC_TDCR_128		0x0a
358 #define APIC_TDCR_1		0x0b
359 
360 /* LVT table indices */
361 #define	APIC_LVT_LINT0		0
362 #define	APIC_LVT_LINT1		1
363 #define	APIC_LVT_TIMER		2
364 #define	APIC_LVT_ERROR		3
365 #define	APIC_LVT_PMC		4
366 #define	APIC_LVT_THERMAL	5
367 #define	APIC_LVT_CMCI		6
368 #define	APIC_LVT_MAX		APIC_LVT_CMCI
369 
370 /******************************************************************************
371  * I/O APIC defines
372  */
373 
374 /* default physical locations of an IO APIC */
375 #define DEFAULT_IO_APIC_BASE	0xfec00000
376 
377 /* window register offset */
378 #define IOAPIC_WINDOW		0x10
379 #define IOAPIC_EOIR		0x40
380 
381 /* indexes into IO APIC */
382 #define IOAPIC_ID		0x00
383 #define IOAPIC_VER		0x01
384 #define IOAPIC_ARB		0x02
385 #define IOAPIC_REDTBL		0x10
386 #define IOAPIC_REDTBL0		IOAPIC_REDTBL
387 #define IOAPIC_REDTBL1		(IOAPIC_REDTBL+0x02)
388 #define IOAPIC_REDTBL2		(IOAPIC_REDTBL+0x04)
389 #define IOAPIC_REDTBL3		(IOAPIC_REDTBL+0x06)
390 #define IOAPIC_REDTBL4		(IOAPIC_REDTBL+0x08)
391 #define IOAPIC_REDTBL5		(IOAPIC_REDTBL+0x0a)
392 #define IOAPIC_REDTBL6		(IOAPIC_REDTBL+0x0c)
393 #define IOAPIC_REDTBL7		(IOAPIC_REDTBL+0x0e)
394 #define IOAPIC_REDTBL8		(IOAPIC_REDTBL+0x10)
395 #define IOAPIC_REDTBL9		(IOAPIC_REDTBL+0x12)
396 #define IOAPIC_REDTBL10		(IOAPIC_REDTBL+0x14)
397 #define IOAPIC_REDTBL11		(IOAPIC_REDTBL+0x16)
398 #define IOAPIC_REDTBL12		(IOAPIC_REDTBL+0x18)
399 #define IOAPIC_REDTBL13		(IOAPIC_REDTBL+0x1a)
400 #define IOAPIC_REDTBL14		(IOAPIC_REDTBL+0x1c)
401 #define IOAPIC_REDTBL15		(IOAPIC_REDTBL+0x1e)
402 #define IOAPIC_REDTBL16		(IOAPIC_REDTBL+0x20)
403 #define IOAPIC_REDTBL17		(IOAPIC_REDTBL+0x22)
404 #define IOAPIC_REDTBL18		(IOAPIC_REDTBL+0x24)
405 #define IOAPIC_REDTBL19		(IOAPIC_REDTBL+0x26)
406 #define IOAPIC_REDTBL20		(IOAPIC_REDTBL+0x28)
407 #define IOAPIC_REDTBL21		(IOAPIC_REDTBL+0x2a)
408 #define IOAPIC_REDTBL22		(IOAPIC_REDTBL+0x2c)
409 #define IOAPIC_REDTBL23		(IOAPIC_REDTBL+0x2e)
410 
411 /* fields in VER */
412 #define IOART_VER_VERSION	0x000000ff
413 #define IOART_VER_MAXREDIR	0x00ff0000
414 #define MAXREDIRSHIFT		16
415 
416 /*
417  * fields in the IO APIC's redirection table entries
418  */
419 #define IOART_DEST	APIC_ID_MASK	/* broadcast addr: all APICs */
420 
421 #define IOART_RESV	0x00fe0000	/* reserved */
422 
423 #define IOART_INTMASK	0x00010000	/* R/W: INTerrupt mask */
424 # define IOART_INTMCLR	0x00000000	/*       clear, allow INTs */
425 # define IOART_INTMSET	0x00010000	/*       set, inhibit INTs */
426 
427 #define IOART_TRGRMOD	0x00008000	/* R/W: trigger mode */
428 # define IOART_TRGREDG	0x00000000	/*       edge */
429 # define IOART_TRGRLVL	0x00008000	/*       level */
430 
431 #define IOART_REM_IRR	0x00004000	/* RO: remote IRR */
432 
433 #define IOART_INTPOL	0x00002000	/* R/W: INT input pin polarity */
434 # define IOART_INTAHI	0x00000000	/*      active high */
435 # define IOART_INTALO	0x00002000	/*      active low */
436 
437 #define IOART_DELIVS	0x00001000	/* RO: delivery status */
438 
439 #define IOART_DESTMOD	0x00000800	/* R/W: destination mode */
440 # define IOART_DESTPHY	0x00000000	/*      physical */
441 # define IOART_DESTLOG	0x00000800	/*      logical */
442 
443 #define IOART_DELMOD	0x00000700	/* R/W: delivery mode */
444 # define IOART_DELFIXED	0x00000000	/*       fixed */
445 # define IOART_DELLOPRI	0x00000100	/*       lowest priority */
446 # define IOART_DELSMI	0x00000200	/*       System Management INT */
447 # define IOART_DELRSV1	0x00000300	/*       reserved */
448 # define IOART_DELNMI	0x00000400	/*       NMI signal */
449 # define IOART_DELINIT	0x00000500	/*       INIT signal */
450 # define IOART_DELRSV2	0x00000600	/*       reserved */
451 # define IOART_DELEXINT	0x00000700	/*       External INTerrupt */
452 
453 #define IOART_INTVEC	0x000000ff	/* R/W: INTerrupt vector field */
454 
455 #endif /* _X86_APICREG_H_ */
456