xref: /illumos-gate/usr/src/uts/common/io/chxge/com/regs.h (revision 2d6eb4a5)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /* This file is automatically generated --- do not edit */
23 
24 /* SGE registers */
25 #define A_SG_CONTROL 0x0
26 
27 #define S_CMDQ0_ENABLE    0
28 #define V_CMDQ0_ENABLE(x) ((x) << S_CMDQ0_ENABLE)
29 #define F_CMDQ0_ENABLE    V_CMDQ0_ENABLE(1U)
30 
31 #define S_CMDQ1_ENABLE    1
32 #define V_CMDQ1_ENABLE(x) ((x) << S_CMDQ1_ENABLE)
33 #define F_CMDQ1_ENABLE    V_CMDQ1_ENABLE(1U)
34 
35 #define S_FL0_ENABLE    2
36 #define V_FL0_ENABLE(x) ((x) << S_FL0_ENABLE)
37 #define F_FL0_ENABLE    V_FL0_ENABLE(1U)
38 
39 #define S_FL1_ENABLE    3
40 #define V_FL1_ENABLE(x) ((x) << S_FL1_ENABLE)
41 #define F_FL1_ENABLE    V_FL1_ENABLE(1U)
42 
43 #define S_CPL_ENABLE    4
44 #define V_CPL_ENABLE(x) ((x) << S_CPL_ENABLE)
45 #define F_CPL_ENABLE    V_CPL_ENABLE(1U)
46 
47 #define S_RESPONSE_QUEUE_ENABLE    5
48 #define V_RESPONSE_QUEUE_ENABLE(x) ((x) << S_RESPONSE_QUEUE_ENABLE)
49 #define F_RESPONSE_QUEUE_ENABLE    V_RESPONSE_QUEUE_ENABLE(1U)
50 
51 #define S_CMDQ_PRIORITY    6
52 #define M_CMDQ_PRIORITY    0x3
53 #define V_CMDQ_PRIORITY(x) ((x) << S_CMDQ_PRIORITY)
54 #define G_CMDQ_PRIORITY(x) (((x) >> S_CMDQ_PRIORITY) & M_CMDQ_PRIORITY)
55 
56 #define S_DISABLE_CMDQ0_GTS    8
57 #define V_DISABLE_CMDQ0_GTS(x) ((x) << S_DISABLE_CMDQ0_GTS)
58 #define F_DISABLE_CMDQ0_GTS    V_DISABLE_CMDQ0_GTS(1U)
59 
60 #define S_DISABLE_CMDQ1_GTS    9
61 #define V_DISABLE_CMDQ1_GTS(x) ((x) << S_DISABLE_CMDQ1_GTS)
62 #define F_DISABLE_CMDQ1_GTS    V_DISABLE_CMDQ1_GTS(1U)
63 
64 #define S_DISABLE_FL0_GTS    10
65 #define V_DISABLE_FL0_GTS(x) ((x) << S_DISABLE_FL0_GTS)
66 #define F_DISABLE_FL0_GTS    V_DISABLE_FL0_GTS(1U)
67 
68 #define S_DISABLE_FL1_GTS    11
69 #define V_DISABLE_FL1_GTS(x) ((x) << S_DISABLE_FL1_GTS)
70 #define F_DISABLE_FL1_GTS    V_DISABLE_FL1_GTS(1U)
71 
72 #define S_ENABLE_BIG_ENDIAN    12
73 #define V_ENABLE_BIG_ENDIAN(x) ((x) << S_ENABLE_BIG_ENDIAN)
74 #define F_ENABLE_BIG_ENDIAN    V_ENABLE_BIG_ENDIAN(1U)
75 
76 #define S_FL_SELECTION_CRITERIA    13
77 #define V_FL_SELECTION_CRITERIA(x) ((x) << S_FL_SELECTION_CRITERIA)
78 #define F_FL_SELECTION_CRITERIA    V_FL_SELECTION_CRITERIA(1U)
79 
80 #define S_ISCSI_COALESCE    14
81 #define V_ISCSI_COALESCE(x) ((x) << S_ISCSI_COALESCE)
82 #define F_ISCSI_COALESCE    V_ISCSI_COALESCE(1U)
83 
84 #define S_RX_PKT_OFFSET    15
85 #define M_RX_PKT_OFFSET    0x7
86 #define V_RX_PKT_OFFSET(x) ((x) << S_RX_PKT_OFFSET)
87 #define G_RX_PKT_OFFSET(x) (((x) >> S_RX_PKT_OFFSET) & M_RX_PKT_OFFSET)
88 
89 #define S_VLAN_XTRACT    18
90 #define V_VLAN_XTRACT(x) ((x) << S_VLAN_XTRACT)
91 #define F_VLAN_XTRACT    V_VLAN_XTRACT(1U)
92 
93 #define A_SG_DOORBELL 0x4
94 #define A_SG_CMD0BASELWR 0x8
95 #define A_SG_CMD0BASEUPR 0xc
96 #define A_SG_CMD1BASELWR 0x10
97 #define A_SG_CMD1BASEUPR 0x14
98 #define A_SG_FL0BASELWR 0x18
99 #define A_SG_FL0BASEUPR 0x1c
100 #define A_SG_FL1BASELWR 0x20
101 #define A_SG_FL1BASEUPR 0x24
102 #define A_SG_CMD0SIZE 0x28
103 
104 #define S_CMDQ0_SIZE    0
105 #define M_CMDQ0_SIZE    0x1ffff
106 #define V_CMDQ0_SIZE(x) ((x) << S_CMDQ0_SIZE)
107 #define G_CMDQ0_SIZE(x) (((x) >> S_CMDQ0_SIZE) & M_CMDQ0_SIZE)
108 
109 #define A_SG_FL0SIZE 0x2c
110 
111 #define S_FL0_SIZE    0
112 #define M_FL0_SIZE    0x1ffff
113 #define V_FL0_SIZE(x) ((x) << S_FL0_SIZE)
114 #define G_FL0_SIZE(x) (((x) >> S_FL0_SIZE) & M_FL0_SIZE)
115 
116 #define A_SG_RSPSIZE 0x30
117 
118 #define S_RESPQ_SIZE    0
119 #define M_RESPQ_SIZE    0x1ffff
120 #define V_RESPQ_SIZE(x) ((x) << S_RESPQ_SIZE)
121 #define G_RESPQ_SIZE(x) (((x) >> S_RESPQ_SIZE) & M_RESPQ_SIZE)
122 
123 #define A_SG_RSPBASELWR 0x34
124 #define A_SG_RSPBASEUPR 0x38
125 #define A_SG_FLTHRESHOLD 0x3c
126 
127 #define S_FL_THRESHOLD    0
128 #define M_FL_THRESHOLD    0xffff
129 #define V_FL_THRESHOLD(x) ((x) << S_FL_THRESHOLD)
130 #define G_FL_THRESHOLD(x) (((x) >> S_FL_THRESHOLD) & M_FL_THRESHOLD)
131 
132 #define A_SG_RSPQUEUECREDIT 0x40
133 
134 #define S_RESPQ_CREDIT    0
135 #define M_RESPQ_CREDIT    0x1ffff
136 #define V_RESPQ_CREDIT(x) ((x) << S_RESPQ_CREDIT)
137 #define G_RESPQ_CREDIT(x) (((x) >> S_RESPQ_CREDIT) & M_RESPQ_CREDIT)
138 
139 #define A_SG_SLEEPING 0x48
140 
141 #define S_SLEEPING    0
142 #define M_SLEEPING    0xffff
143 #define V_SLEEPING(x) ((x) << S_SLEEPING)
144 #define G_SLEEPING(x) (((x) >> S_SLEEPING) & M_SLEEPING)
145 
146 #define A_SG_INTRTIMER 0x4c
147 
148 #define S_INTERRUPT_TIMER_COUNT    0
149 #define M_INTERRUPT_TIMER_COUNT    0xffffff
150 #define V_INTERRUPT_TIMER_COUNT(x) ((x) << S_INTERRUPT_TIMER_COUNT)
151 #define G_INTERRUPT_TIMER_COUNT(x) (((x) >> S_INTERRUPT_TIMER_COUNT) & M_INTERRUPT_TIMER_COUNT)
152 
153 #define A_SG_CMD0PTR 0x50
154 
155 #define S_CMDQ0_POINTER    0
156 #define M_CMDQ0_POINTER    0xffff
157 #define V_CMDQ0_POINTER(x) ((x) << S_CMDQ0_POINTER)
158 #define G_CMDQ0_POINTER(x) (((x) >> S_CMDQ0_POINTER) & M_CMDQ0_POINTER)
159 
160 #define S_CURRENT_GENERATION_BIT    16
161 #define V_CURRENT_GENERATION_BIT(x) ((x) << S_CURRENT_GENERATION_BIT)
162 #define F_CURRENT_GENERATION_BIT    V_CURRENT_GENERATION_BIT(1U)
163 
164 #define A_SG_CMD1PTR 0x54
165 
166 #define S_CMDQ1_POINTER    0
167 #define M_CMDQ1_POINTER    0xffff
168 #define V_CMDQ1_POINTER(x) ((x) << S_CMDQ1_POINTER)
169 #define G_CMDQ1_POINTER(x) (((x) >> S_CMDQ1_POINTER) & M_CMDQ1_POINTER)
170 
171 #define A_SG_FL0PTR 0x58
172 
173 #define S_FL0_POINTER    0
174 #define M_FL0_POINTER    0xffff
175 #define V_FL0_POINTER(x) ((x) << S_FL0_POINTER)
176 #define G_FL0_POINTER(x) (((x) >> S_FL0_POINTER) & M_FL0_POINTER)
177 
178 #define A_SG_FL1PTR 0x5c
179 
180 #define S_FL1_POINTER    0
181 #define M_FL1_POINTER    0xffff
182 #define V_FL1_POINTER(x) ((x) << S_FL1_POINTER)
183 #define G_FL1_POINTER(x) (((x) >> S_FL1_POINTER) & M_FL1_POINTER)
184 
185 #define A_SG_VERSION 0x6c
186 
187 #define S_DAY    0
188 #define M_DAY    0x1f
189 #define V_DAY(x) ((x) << S_DAY)
190 #define G_DAY(x) (((x) >> S_DAY) & M_DAY)
191 
192 #define S_MONTH    5
193 #define M_MONTH    0xf
194 #define V_MONTH(x) ((x) << S_MONTH)
195 #define G_MONTH(x) (((x) >> S_MONTH) & M_MONTH)
196 
197 #define A_SG_CMD1SIZE 0xb0
198 
199 #define S_CMDQ1_SIZE    0
200 #define M_CMDQ1_SIZE    0x1ffff
201 #define V_CMDQ1_SIZE(x) ((x) << S_CMDQ1_SIZE)
202 #define G_CMDQ1_SIZE(x) (((x) >> S_CMDQ1_SIZE) & M_CMDQ1_SIZE)
203 
204 #define A_SG_FL1SIZE 0xb4
205 
206 #define S_FL1_SIZE    0
207 #define M_FL1_SIZE    0x1ffff
208 #define V_FL1_SIZE(x) ((x) << S_FL1_SIZE)
209 #define G_FL1_SIZE(x) (((x) >> S_FL1_SIZE) & M_FL1_SIZE)
210 
211 #define A_SG_INT_ENABLE 0xb8
212 
213 #define S_RESPQ_EXHAUSTED    0
214 #define V_RESPQ_EXHAUSTED(x) ((x) << S_RESPQ_EXHAUSTED)
215 #define F_RESPQ_EXHAUSTED    V_RESPQ_EXHAUSTED(1U)
216 
217 #define S_RESPQ_OVERFLOW    1
218 #define V_RESPQ_OVERFLOW(x) ((x) << S_RESPQ_OVERFLOW)
219 #define F_RESPQ_OVERFLOW    V_RESPQ_OVERFLOW(1U)
220 
221 #define S_FL_EXHAUSTED    2
222 #define V_FL_EXHAUSTED(x) ((x) << S_FL_EXHAUSTED)
223 #define F_FL_EXHAUSTED    V_FL_EXHAUSTED(1U)
224 
225 #define S_PACKET_TOO_BIG    3
226 #define V_PACKET_TOO_BIG(x) ((x) << S_PACKET_TOO_BIG)
227 #define F_PACKET_TOO_BIG    V_PACKET_TOO_BIG(1U)
228 
229 #define S_PACKET_MISMATCH    4
230 #define V_PACKET_MISMATCH(x) ((x) << S_PACKET_MISMATCH)
231 #define F_PACKET_MISMATCH    V_PACKET_MISMATCH(1U)
232 
233 #define A_SG_INT_CAUSE 0xbc
234 #define A_SG_RESPACCUTIMER 0xc0
235 
236 /* MC3 registers */
237 #define A_MC3_CFG 0x100
238 
239 #define S_CLK_ENABLE    0
240 #define V_CLK_ENABLE(x) ((x) << S_CLK_ENABLE)
241 #define F_CLK_ENABLE    V_CLK_ENABLE(1U)
242 
243 #define S_READY    1
244 #define V_READY(x) ((x) << S_READY)
245 #define F_READY    V_READY(1U)
246 
247 #define S_READ_TO_WRITE_DELAY    2
248 #define M_READ_TO_WRITE_DELAY    0x7
249 #define V_READ_TO_WRITE_DELAY(x) ((x) << S_READ_TO_WRITE_DELAY)
250 #define G_READ_TO_WRITE_DELAY(x) (((x) >> S_READ_TO_WRITE_DELAY) & M_READ_TO_WRITE_DELAY)
251 
252 #define S_WRITE_TO_READ_DELAY    5
253 #define M_WRITE_TO_READ_DELAY    0x7
254 #define V_WRITE_TO_READ_DELAY(x) ((x) << S_WRITE_TO_READ_DELAY)
255 #define G_WRITE_TO_READ_DELAY(x) (((x) >> S_WRITE_TO_READ_DELAY) & M_WRITE_TO_READ_DELAY)
256 
257 #define S_MC3_BANK_CYCLE    8
258 #define M_MC3_BANK_CYCLE    0xf
259 #define V_MC3_BANK_CYCLE(x) ((x) << S_MC3_BANK_CYCLE)
260 #define G_MC3_BANK_CYCLE(x) (((x) >> S_MC3_BANK_CYCLE) & M_MC3_BANK_CYCLE)
261 
262 #define S_REFRESH_CYCLE    12
263 #define M_REFRESH_CYCLE    0xf
264 #define V_REFRESH_CYCLE(x) ((x) << S_REFRESH_CYCLE)
265 #define G_REFRESH_CYCLE(x) (((x) >> S_REFRESH_CYCLE) & M_REFRESH_CYCLE)
266 
267 #define S_PRECHARGE_CYCLE    16
268 #define M_PRECHARGE_CYCLE    0x3
269 #define V_PRECHARGE_CYCLE(x) ((x) << S_PRECHARGE_CYCLE)
270 #define G_PRECHARGE_CYCLE(x) (((x) >> S_PRECHARGE_CYCLE) & M_PRECHARGE_CYCLE)
271 
272 #define S_ACTIVE_TO_READ_WRITE_DELAY    18
273 #define V_ACTIVE_TO_READ_WRITE_DELAY(x) ((x) << S_ACTIVE_TO_READ_WRITE_DELAY)
274 #define F_ACTIVE_TO_READ_WRITE_DELAY    V_ACTIVE_TO_READ_WRITE_DELAY(1U)
275 
276 #define S_ACTIVE_TO_PRECHARGE_DELAY    19
277 #define M_ACTIVE_TO_PRECHARGE_DELAY    0x7
278 #define V_ACTIVE_TO_PRECHARGE_DELAY(x) ((x) << S_ACTIVE_TO_PRECHARGE_DELAY)
279 #define G_ACTIVE_TO_PRECHARGE_DELAY(x) (((x) >> S_ACTIVE_TO_PRECHARGE_DELAY) & M_ACTIVE_TO_PRECHARGE_DELAY)
280 
281 #define S_WRITE_RECOVERY_DELAY    22
282 #define M_WRITE_RECOVERY_DELAY    0x3
283 #define V_WRITE_RECOVERY_DELAY(x) ((x) << S_WRITE_RECOVERY_DELAY)
284 #define G_WRITE_RECOVERY_DELAY(x) (((x) >> S_WRITE_RECOVERY_DELAY) & M_WRITE_RECOVERY_DELAY)
285 
286 #define S_DENSITY    24
287 #define M_DENSITY    0x3
288 #define V_DENSITY(x) ((x) << S_DENSITY)
289 #define G_DENSITY(x) (((x) >> S_DENSITY) & M_DENSITY)
290 
291 #define S_ORGANIZATION    26
292 #define V_ORGANIZATION(x) ((x) << S_ORGANIZATION)
293 #define F_ORGANIZATION    V_ORGANIZATION(1U)
294 
295 #define S_BANKS    27
296 #define V_BANKS(x) ((x) << S_BANKS)
297 #define F_BANKS    V_BANKS(1U)
298 
299 #define S_UNREGISTERED    28
300 #define V_UNREGISTERED(x) ((x) << S_UNREGISTERED)
301 #define F_UNREGISTERED    V_UNREGISTERED(1U)
302 
303 #define S_MC3_WIDTH    29
304 #define M_MC3_WIDTH    0x3
305 #define V_MC3_WIDTH(x) ((x) << S_MC3_WIDTH)
306 #define G_MC3_WIDTH(x) (((x) >> S_MC3_WIDTH) & M_MC3_WIDTH)
307 
308 #define S_MC3_SLOW    31
309 #define V_MC3_SLOW(x) ((x) << S_MC3_SLOW)
310 #define F_MC3_SLOW    V_MC3_SLOW(1U)
311 
312 #define A_MC3_MODE 0x104
313 
314 #define S_MC3_MODE    0
315 #define M_MC3_MODE    0x3fff
316 #define V_MC3_MODE(x) ((x) << S_MC3_MODE)
317 #define G_MC3_MODE(x) (((x) >> S_MC3_MODE) & M_MC3_MODE)
318 
319 #define S_BUSY    31
320 #define V_BUSY(x) ((x) << S_BUSY)
321 #define F_BUSY    V_BUSY(1U)
322 
323 #define A_MC3_EXT_MODE 0x108
324 
325 #define S_MC3_EXTENDED_MODE    0
326 #define M_MC3_EXTENDED_MODE    0x3fff
327 #define V_MC3_EXTENDED_MODE(x) ((x) << S_MC3_EXTENDED_MODE)
328 #define G_MC3_EXTENDED_MODE(x) (((x) >> S_MC3_EXTENDED_MODE) & M_MC3_EXTENDED_MODE)
329 
330 #define A_MC3_PRECHARG 0x10c
331 #define A_MC3_REFRESH 0x110
332 
333 #define S_REFRESH_ENABLE    0
334 #define V_REFRESH_ENABLE(x) ((x) << S_REFRESH_ENABLE)
335 #define F_REFRESH_ENABLE    V_REFRESH_ENABLE(1U)
336 
337 #define S_REFRESH_DIVISOR    1
338 #define M_REFRESH_DIVISOR    0x3fff
339 #define V_REFRESH_DIVISOR(x) ((x) << S_REFRESH_DIVISOR)
340 #define G_REFRESH_DIVISOR(x) (((x) >> S_REFRESH_DIVISOR) & M_REFRESH_DIVISOR)
341 
342 #define A_MC3_STROBE 0x114
343 
344 #define S_MASTER_DLL_RESET    0
345 #define V_MASTER_DLL_RESET(x) ((x) << S_MASTER_DLL_RESET)
346 #define F_MASTER_DLL_RESET    V_MASTER_DLL_RESET(1U)
347 
348 #define S_MASTER_DLL_TAP_COUNT    1
349 #define M_MASTER_DLL_TAP_COUNT    0xff
350 #define V_MASTER_DLL_TAP_COUNT(x) ((x) << S_MASTER_DLL_TAP_COUNT)
351 #define G_MASTER_DLL_TAP_COUNT(x) (((x) >> S_MASTER_DLL_TAP_COUNT) & M_MASTER_DLL_TAP_COUNT)
352 
353 #define S_MASTER_DLL_LOCKED    9
354 #define V_MASTER_DLL_LOCKED(x) ((x) << S_MASTER_DLL_LOCKED)
355 #define F_MASTER_DLL_LOCKED    V_MASTER_DLL_LOCKED(1U)
356 
357 #define S_MASTER_DLL_MAX_TAP_COUNT    10
358 #define V_MASTER_DLL_MAX_TAP_COUNT(x) ((x) << S_MASTER_DLL_MAX_TAP_COUNT)
359 #define F_MASTER_DLL_MAX_TAP_COUNT    V_MASTER_DLL_MAX_TAP_COUNT(1U)
360 
361 #define S_MASTER_DLL_TAP_COUNT_OFFSET    11
362 #define M_MASTER_DLL_TAP_COUNT_OFFSET    0x3f
363 #define V_MASTER_DLL_TAP_COUNT_OFFSET(x) ((x) << S_MASTER_DLL_TAP_COUNT_OFFSET)
364 #define G_MASTER_DLL_TAP_COUNT_OFFSET(x) (((x) >> S_MASTER_DLL_TAP_COUNT_OFFSET) & M_MASTER_DLL_TAP_COUNT_OFFSET)
365 
366 #define S_SLAVE_DLL_RESET    11
367 #define V_SLAVE_DLL_RESET(x) ((x) << S_SLAVE_DLL_RESET)
368 #define F_SLAVE_DLL_RESET    V_SLAVE_DLL_RESET(1U)
369 
370 #define S_SLAVE_DLL_DELTA    12
371 #define M_SLAVE_DLL_DELTA    0xf
372 #define V_SLAVE_DLL_DELTA(x) ((x) << S_SLAVE_DLL_DELTA)
373 #define G_SLAVE_DLL_DELTA(x) (((x) >> S_SLAVE_DLL_DELTA) & M_SLAVE_DLL_DELTA)
374 
375 #define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT    17
376 #define M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT    0x3f
377 #define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT)
378 #define G_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT) & M_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT)
379 
380 #define S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE    23
381 #define V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(x) ((x) << S_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE)
382 #define F_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE    V_SLAVE_DELAY_LINE_MANUAL_TAP_COUNT_ENABLE(1U)
383 
384 #define S_SLAVE_DELAY_LINE_TAP_COUNT    24
385 #define M_SLAVE_DELAY_LINE_TAP_COUNT    0x3f
386 #define V_SLAVE_DELAY_LINE_TAP_COUNT(x) ((x) << S_SLAVE_DELAY_LINE_TAP_COUNT)
387 #define G_SLAVE_DELAY_LINE_TAP_COUNT(x) (((x) >> S_SLAVE_DELAY_LINE_TAP_COUNT) & M_SLAVE_DELAY_LINE_TAP_COUNT)
388 
389 #define A_MC3_ECC_CNTL 0x118
390 
391 #define S_ECC_GENERATION_ENABLE    0
392 #define V_ECC_GENERATION_ENABLE(x) ((x) << S_ECC_GENERATION_ENABLE)
393 #define F_ECC_GENERATION_ENABLE    V_ECC_GENERATION_ENABLE(1U)
394 
395 #define S_ECC_CHECK_ENABLE    1
396 #define V_ECC_CHECK_ENABLE(x) ((x) << S_ECC_CHECK_ENABLE)
397 #define F_ECC_CHECK_ENABLE    V_ECC_CHECK_ENABLE(1U)
398 
399 #define S_CORRECTABLE_ERROR_COUNT    2
400 #define M_CORRECTABLE_ERROR_COUNT    0xff
401 #define V_CORRECTABLE_ERROR_COUNT(x) ((x) << S_CORRECTABLE_ERROR_COUNT)
402 #define G_CORRECTABLE_ERROR_COUNT(x) (((x) >> S_CORRECTABLE_ERROR_COUNT) & M_CORRECTABLE_ERROR_COUNT)
403 
404 #define S_UNCORRECTABLE_ERROR_COUNT    10
405 #define M_UNCORRECTABLE_ERROR_COUNT    0xff
406 #define V_UNCORRECTABLE_ERROR_COUNT(x) ((x) << S_UNCORRECTABLE_ERROR_COUNT)
407 #define G_UNCORRECTABLE_ERROR_COUNT(x) (((x) >> S_UNCORRECTABLE_ERROR_COUNT) & M_UNCORRECTABLE_ERROR_COUNT)
408 
409 #define A_MC3_CE_ADDR 0x11c
410 
411 #define S_MC3_CE_ADDR    4
412 #define M_MC3_CE_ADDR    0xfffffff
413 #define V_MC3_CE_ADDR(x) ((x) << S_MC3_CE_ADDR)
414 #define G_MC3_CE_ADDR(x) (((x) >> S_MC3_CE_ADDR) & M_MC3_CE_ADDR)
415 
416 #define A_MC3_CE_DATA0 0x120
417 #define A_MC3_CE_DATA1 0x124
418 #define A_MC3_CE_DATA2 0x128
419 #define A_MC3_CE_DATA3 0x12c
420 #define A_MC3_CE_DATA4 0x130
421 #define A_MC3_UE_ADDR 0x134
422 
423 #define S_MC3_UE_ADDR    4
424 #define M_MC3_UE_ADDR    0xfffffff
425 #define V_MC3_UE_ADDR(x) ((x) << S_MC3_UE_ADDR)
426 #define G_MC3_UE_ADDR(x) (((x) >> S_MC3_UE_ADDR) & M_MC3_UE_ADDR)
427 
428 #define A_MC3_UE_DATA0 0x138
429 #define A_MC3_UE_DATA1 0x13c
430 #define A_MC3_UE_DATA2 0x140
431 #define A_MC3_UE_DATA3 0x144
432 #define A_MC3_UE_DATA4 0x148
433 #define A_MC3_BD_ADDR 0x14c
434 #define A_MC3_BD_DATA0 0x150
435 #define A_MC3_BD_DATA1 0x154
436 #define A_MC3_BD_DATA2 0x158
437 #define A_MC3_BD_DATA3 0x15c
438 #define A_MC3_BD_DATA4 0x160
439 #define A_MC3_BD_OP 0x164
440 
441 #define S_BACK_DOOR_OPERATION    0
442 #define V_BACK_DOOR_OPERATION(x) ((x) << S_BACK_DOOR_OPERATION)
443 #define F_BACK_DOOR_OPERATION    V_BACK_DOOR_OPERATION(1U)
444 
445 #define A_MC3_BIST_ADDR_BEG 0x168
446 #define A_MC3_BIST_ADDR_END 0x16c
447 #define A_MC3_BIST_DATA 0x170
448 #define A_MC3_BIST_OP 0x174
449 
450 #define S_OP    0
451 #define V_OP(x) ((x) << S_OP)
452 #define F_OP    V_OP(1U)
453 
454 #define S_DATA_PATTERN    1
455 #define M_DATA_PATTERN    0x3
456 #define V_DATA_PATTERN(x) ((x) << S_DATA_PATTERN)
457 #define G_DATA_PATTERN(x) (((x) >> S_DATA_PATTERN) & M_DATA_PATTERN)
458 
459 #define S_CONTINUOUS    3
460 #define V_CONTINUOUS(x) ((x) << S_CONTINUOUS)
461 #define F_CONTINUOUS    V_CONTINUOUS(1U)
462 
463 #define A_MC3_INT_ENABLE 0x178
464 
465 #define S_MC3_CORR_ERR    0
466 #define V_MC3_CORR_ERR(x) ((x) << S_MC3_CORR_ERR)
467 #define F_MC3_CORR_ERR    V_MC3_CORR_ERR(1U)
468 
469 #define S_MC3_UNCORR_ERR    1
470 #define V_MC3_UNCORR_ERR(x) ((x) << S_MC3_UNCORR_ERR)
471 #define F_MC3_UNCORR_ERR    V_MC3_UNCORR_ERR(1U)
472 
473 #define S_MC3_PARITY_ERR    2
474 #define M_MC3_PARITY_ERR    0xff
475 #define V_MC3_PARITY_ERR(x) ((x) << S_MC3_PARITY_ERR)
476 #define G_MC3_PARITY_ERR(x) (((x) >> S_MC3_PARITY_ERR) & M_MC3_PARITY_ERR)
477 
478 #define S_MC3_ADDR_ERR    10
479 #define V_MC3_ADDR_ERR(x) ((x) << S_MC3_ADDR_ERR)
480 #define F_MC3_ADDR_ERR    V_MC3_ADDR_ERR(1U)
481 
482 #define A_MC3_INT_CAUSE 0x17c
483 
484 /* MC4 registers */
485 #define A_MC4_CFG 0x180
486 
487 #define S_POWER_UP    0
488 #define V_POWER_UP(x) ((x) << S_POWER_UP)
489 #define F_POWER_UP    V_POWER_UP(1U)
490 
491 #define S_MC4_BANK_CYCLE    8
492 #define M_MC4_BANK_CYCLE    0x7
493 #define V_MC4_BANK_CYCLE(x) ((x) << S_MC4_BANK_CYCLE)
494 #define G_MC4_BANK_CYCLE(x) (((x) >> S_MC4_BANK_CYCLE) & M_MC4_BANK_CYCLE)
495 
496 #define S_MC4_NARROW    24
497 #define V_MC4_NARROW(x) ((x) << S_MC4_NARROW)
498 #define F_MC4_NARROW    V_MC4_NARROW(1U)
499 
500 #define S_MC4_SLOW    25
501 #define V_MC4_SLOW(x) ((x) << S_MC4_SLOW)
502 #define F_MC4_SLOW    V_MC4_SLOW(1U)
503 
504 #define S_MC4A_WIDTH    24
505 #define M_MC4A_WIDTH    0x3
506 #define V_MC4A_WIDTH(x) ((x) << S_MC4A_WIDTH)
507 #define G_MC4A_WIDTH(x) (((x) >> S_MC4A_WIDTH) & M_MC4A_WIDTH)
508 
509 #define S_MC4A_SLOW    26
510 #define V_MC4A_SLOW(x) ((x) << S_MC4A_SLOW)
511 #define F_MC4A_SLOW    V_MC4A_SLOW(1U)
512 
513 #define A_MC4_MODE 0x184
514 
515 #define S_MC4_MODE    0
516 #define M_MC4_MODE    0x7fff
517 #define V_MC4_MODE(x) ((x) << S_MC4_MODE)
518 #define G_MC4_MODE(x) (((x) >> S_MC4_MODE) & M_MC4_MODE)
519 
520 #define A_MC4_EXT_MODE 0x188
521 
522 #define S_MC4_EXTENDED_MODE    0
523 #define M_MC4_EXTENDED_MODE    0x7fff
524 #define V_MC4_EXTENDED_MODE(x) ((x) << S_MC4_EXTENDED_MODE)
525 #define G_MC4_EXTENDED_MODE(x) (((x) >> S_MC4_EXTENDED_MODE) & M_MC4_EXTENDED_MODE)
526 
527 #define A_MC4_REFRESH 0x190
528 #define A_MC4_STROBE 0x194
529 #define A_MC4_ECC_CNTL 0x198
530 #define A_MC4_CE_ADDR 0x19c
531 
532 #define S_MC4_CE_ADDR    4
533 #define M_MC4_CE_ADDR    0xffffff
534 #define V_MC4_CE_ADDR(x) ((x) << S_MC4_CE_ADDR)
535 #define G_MC4_CE_ADDR(x) (((x) >> S_MC4_CE_ADDR) & M_MC4_CE_ADDR)
536 
537 #define A_MC4_CE_DATA0 0x1a0
538 #define A_MC4_CE_DATA1 0x1a4
539 #define A_MC4_CE_DATA2 0x1a8
540 #define A_MC4_CE_DATA3 0x1ac
541 #define A_MC4_CE_DATA4 0x1b0
542 #define A_MC4_UE_ADDR 0x1b4
543 
544 #define S_MC4_UE_ADDR    4
545 #define M_MC4_UE_ADDR    0xffffff
546 #define V_MC4_UE_ADDR(x) ((x) << S_MC4_UE_ADDR)
547 #define G_MC4_UE_ADDR(x) (((x) >> S_MC4_UE_ADDR) & M_MC4_UE_ADDR)
548 
549 #define A_MC4_UE_DATA0 0x1b8
550 #define A_MC4_UE_DATA1 0x1bc
551 #define A_MC4_UE_DATA2 0x1c0
552 #define A_MC4_UE_DATA3 0x1c4
553 #define A_MC4_UE_DATA4 0x1c8
554 #define A_MC4_BD_ADDR 0x1cc
555 
556 #define S_MC4_BACK_DOOR_ADDR    0
557 #define M_MC4_BACK_DOOR_ADDR    0xfffffff
558 #define V_MC4_BACK_DOOR_ADDR(x) ((x) << S_MC4_BACK_DOOR_ADDR)
559 #define G_MC4_BACK_DOOR_ADDR(x) (((x) >> S_MC4_BACK_DOOR_ADDR) & M_MC4_BACK_DOOR_ADDR)
560 
561 #define A_MC4_BD_DATA0 0x1d0
562 #define A_MC4_BD_DATA1 0x1d4
563 #define A_MC4_BD_DATA2 0x1d8
564 #define A_MC4_BD_DATA3 0x1dc
565 #define A_MC4_BD_DATA4 0x1e0
566 #define A_MC4_BD_OP 0x1e4
567 
568 #define S_OPERATION    0
569 #define V_OPERATION(x) ((x) << S_OPERATION)
570 #define F_OPERATION    V_OPERATION(1U)
571 
572 #define A_MC4_BIST_ADDR_BEG 0x1e8
573 #define A_MC4_BIST_ADDR_END 0x1ec
574 #define A_MC4_BIST_DATA 0x1f0
575 #define A_MC4_BIST_OP 0x1f4
576 #define A_MC4_INT_ENABLE 0x1f8
577 
578 #define S_MC4_CORR_ERR    0
579 #define V_MC4_CORR_ERR(x) ((x) << S_MC4_CORR_ERR)
580 #define F_MC4_CORR_ERR    V_MC4_CORR_ERR(1U)
581 
582 #define S_MC4_UNCORR_ERR    1
583 #define V_MC4_UNCORR_ERR(x) ((x) << S_MC4_UNCORR_ERR)
584 #define F_MC4_UNCORR_ERR    V_MC4_UNCORR_ERR(1U)
585 
586 #define S_MC4_ADDR_ERR    2
587 #define V_MC4_ADDR_ERR(x) ((x) << S_MC4_ADDR_ERR)
588 #define F_MC4_ADDR_ERR    V_MC4_ADDR_ERR(1U)
589 
590 #define A_MC4_INT_CAUSE 0x1fc
591 
592 /* TPI registers */
593 #define A_TPI_ADDR 0x280
594 
595 #define S_TPI_ADDRESS    0
596 #define M_TPI_ADDRESS    0xffffff
597 #define V_TPI_ADDRESS(x) ((x) << S_TPI_ADDRESS)
598 #define G_TPI_ADDRESS(x) (((x) >> S_TPI_ADDRESS) & M_TPI_ADDRESS)
599 
600 #define A_TPI_WR_DATA 0x284
601 #define A_TPI_RD_DATA 0x288
602 #define A_TPI_CSR 0x28c
603 
604 #define S_TPIWR    0
605 #define V_TPIWR(x) ((x) << S_TPIWR)
606 #define F_TPIWR    V_TPIWR(1U)
607 
608 #define S_TPIRDY    1
609 #define V_TPIRDY(x) ((x) << S_TPIRDY)
610 #define F_TPIRDY    V_TPIRDY(1U)
611 
612 #define S_INT_DIR    31
613 #define V_INT_DIR(x) ((x) << S_INT_DIR)
614 #define F_INT_DIR    V_INT_DIR(1U)
615 
616 #define A_TPI_PAR 0x29c
617 
618 #define S_TPIPAR    0
619 #define M_TPIPAR    0x7f
620 #define V_TPIPAR(x) ((x) << S_TPIPAR)
621 #define G_TPIPAR(x) (((x) >> S_TPIPAR) & M_TPIPAR)
622 
623 
624 /* TP registers */
625 #define A_TP_IN_CONFIG 0x300
626 
627 #define S_TP_IN_CSPI_TUNNEL    0
628 #define V_TP_IN_CSPI_TUNNEL(x) ((x) << S_TP_IN_CSPI_TUNNEL)
629 #define F_TP_IN_CSPI_TUNNEL    V_TP_IN_CSPI_TUNNEL(1U)
630 
631 #define S_TP_IN_CSPI_ETHERNET    1
632 #define V_TP_IN_CSPI_ETHERNET(x) ((x) << S_TP_IN_CSPI_ETHERNET)
633 #define F_TP_IN_CSPI_ETHERNET    V_TP_IN_CSPI_ETHERNET(1U)
634 
635 #define S_TP_IN_CSPI_CPL    3
636 #define V_TP_IN_CSPI_CPL(x) ((x) << S_TP_IN_CSPI_CPL)
637 #define F_TP_IN_CSPI_CPL    V_TP_IN_CSPI_CPL(1U)
638 
639 #define S_TP_IN_CSPI_POS    4
640 #define V_TP_IN_CSPI_POS(x) ((x) << S_TP_IN_CSPI_POS)
641 #define F_TP_IN_CSPI_POS    V_TP_IN_CSPI_POS(1U)
642 
643 #define S_TP_IN_CSPI_CHECK_IP_CSUM    5
644 #define V_TP_IN_CSPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_IP_CSUM)
645 #define F_TP_IN_CSPI_CHECK_IP_CSUM    V_TP_IN_CSPI_CHECK_IP_CSUM(1U)
646 
647 #define S_TP_IN_CSPI_CHECK_TCP_CSUM    6
648 #define V_TP_IN_CSPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_CSPI_CHECK_TCP_CSUM)
649 #define F_TP_IN_CSPI_CHECK_TCP_CSUM    V_TP_IN_CSPI_CHECK_TCP_CSUM(1U)
650 
651 #define S_TP_IN_ESPI_TUNNEL    7
652 #define V_TP_IN_ESPI_TUNNEL(x) ((x) << S_TP_IN_ESPI_TUNNEL)
653 #define F_TP_IN_ESPI_TUNNEL    V_TP_IN_ESPI_TUNNEL(1U)
654 
655 #define S_TP_IN_ESPI_ETHERNET    8
656 #define V_TP_IN_ESPI_ETHERNET(x) ((x) << S_TP_IN_ESPI_ETHERNET)
657 #define F_TP_IN_ESPI_ETHERNET    V_TP_IN_ESPI_ETHERNET(1U)
658 
659 #define S_TP_IN_ESPI_CPL    10
660 #define V_TP_IN_ESPI_CPL(x) ((x) << S_TP_IN_ESPI_CPL)
661 #define F_TP_IN_ESPI_CPL    V_TP_IN_ESPI_CPL(1U)
662 
663 #define S_TP_IN_ESPI_POS    11
664 #define V_TP_IN_ESPI_POS(x) ((x) << S_TP_IN_ESPI_POS)
665 #define F_TP_IN_ESPI_POS    V_TP_IN_ESPI_POS(1U)
666 
667 #define S_TP_IN_ESPI_CHECK_IP_CSUM    12
668 #define V_TP_IN_ESPI_CHECK_IP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_IP_CSUM)
669 #define F_TP_IN_ESPI_CHECK_IP_CSUM    V_TP_IN_ESPI_CHECK_IP_CSUM(1U)
670 
671 #define S_TP_IN_ESPI_CHECK_TCP_CSUM    13
672 #define V_TP_IN_ESPI_CHECK_TCP_CSUM(x) ((x) << S_TP_IN_ESPI_CHECK_TCP_CSUM)
673 #define F_TP_IN_ESPI_CHECK_TCP_CSUM    V_TP_IN_ESPI_CHECK_TCP_CSUM(1U)
674 
675 #define S_OFFLOAD_DISABLE    14
676 #define V_OFFLOAD_DISABLE(x) ((x) << S_OFFLOAD_DISABLE)
677 #define F_OFFLOAD_DISABLE    V_OFFLOAD_DISABLE(1U)
678 
679 #define A_TP_OUT_CONFIG 0x304
680 
681 #define S_TP_OUT_C_ETH    0
682 #define V_TP_OUT_C_ETH(x) ((x) << S_TP_OUT_C_ETH)
683 #define F_TP_OUT_C_ETH    V_TP_OUT_C_ETH(1U)
684 
685 #define S_TP_OUT_CSPI_CPL    2
686 #define V_TP_OUT_CSPI_CPL(x) ((x) << S_TP_OUT_CSPI_CPL)
687 #define F_TP_OUT_CSPI_CPL    V_TP_OUT_CSPI_CPL(1U)
688 
689 #define S_TP_OUT_CSPI_POS    3
690 #define V_TP_OUT_CSPI_POS(x) ((x) << S_TP_OUT_CSPI_POS)
691 #define F_TP_OUT_CSPI_POS    V_TP_OUT_CSPI_POS(1U)
692 
693 #define S_TP_OUT_CSPI_GENERATE_IP_CSUM    4
694 #define V_TP_OUT_CSPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_IP_CSUM)
695 #define F_TP_OUT_CSPI_GENERATE_IP_CSUM    V_TP_OUT_CSPI_GENERATE_IP_CSUM(1U)
696 
697 #define S_TP_OUT_CSPI_GENERATE_TCP_CSUM    5
698 #define V_TP_OUT_CSPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_CSPI_GENERATE_TCP_CSUM)
699 #define F_TP_OUT_CSPI_GENERATE_TCP_CSUM    V_TP_OUT_CSPI_GENERATE_TCP_CSUM(1U)
700 
701 #define S_TP_OUT_ESPI_ETHERNET    6
702 #define V_TP_OUT_ESPI_ETHERNET(x) ((x) << S_TP_OUT_ESPI_ETHERNET)
703 #define F_TP_OUT_ESPI_ETHERNET    V_TP_OUT_ESPI_ETHERNET(1U)
704 
705 #define S_TP_OUT_ESPI_TAG_ETHERNET    7
706 #define V_TP_OUT_ESPI_TAG_ETHERNET(x) ((x) << S_TP_OUT_ESPI_TAG_ETHERNET)
707 #define F_TP_OUT_ESPI_TAG_ETHERNET    V_TP_OUT_ESPI_TAG_ETHERNET(1U)
708 
709 #define S_TP_OUT_ESPI_CPL    8
710 #define V_TP_OUT_ESPI_CPL(x) ((x) << S_TP_OUT_ESPI_CPL)
711 #define F_TP_OUT_ESPI_CPL    V_TP_OUT_ESPI_CPL(1U)
712 
713 #define S_TP_OUT_ESPI_POS    9
714 #define V_TP_OUT_ESPI_POS(x) ((x) << S_TP_OUT_ESPI_POS)
715 #define F_TP_OUT_ESPI_POS    V_TP_OUT_ESPI_POS(1U)
716 
717 #define S_TP_OUT_ESPI_GENERATE_IP_CSUM    10
718 #define V_TP_OUT_ESPI_GENERATE_IP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_IP_CSUM)
719 #define F_TP_OUT_ESPI_GENERATE_IP_CSUM    V_TP_OUT_ESPI_GENERATE_IP_CSUM(1U)
720 
721 #define S_TP_OUT_ESPI_GENERATE_TCP_CSUM    11
722 #define V_TP_OUT_ESPI_GENERATE_TCP_CSUM(x) ((x) << S_TP_OUT_ESPI_GENERATE_TCP_CSUM)
723 #define F_TP_OUT_ESPI_GENERATE_TCP_CSUM    V_TP_OUT_ESPI_GENERATE_TCP_CSUM(1U)
724 
725 #define A_TP_GLOBAL_CONFIG 0x308
726 
727 #define S_IP_TTL    0
728 #define M_IP_TTL    0xff
729 #define V_IP_TTL(x) ((x) << S_IP_TTL)
730 #define G_IP_TTL(x) (((x) >> S_IP_TTL) & M_IP_TTL)
731 
732 #define S_TCAM_SERVER_REGION_USAGE    8
733 #define M_TCAM_SERVER_REGION_USAGE    0x3
734 #define V_TCAM_SERVER_REGION_USAGE(x) ((x) << S_TCAM_SERVER_REGION_USAGE)
735 #define G_TCAM_SERVER_REGION_USAGE(x) (((x) >> S_TCAM_SERVER_REGION_USAGE) & M_TCAM_SERVER_REGION_USAGE)
736 
737 #define S_QOS_MAPPING    10
738 #define V_QOS_MAPPING(x) ((x) << S_QOS_MAPPING)
739 #define F_QOS_MAPPING    V_QOS_MAPPING(1U)
740 
741 #define S_TCP_CSUM    11
742 #define V_TCP_CSUM(x) ((x) << S_TCP_CSUM)
743 #define F_TCP_CSUM    V_TCP_CSUM(1U)
744 
745 #define S_UDP_CSUM    12
746 #define V_UDP_CSUM(x) ((x) << S_UDP_CSUM)
747 #define F_UDP_CSUM    V_UDP_CSUM(1U)
748 
749 #define S_IP_CSUM    13
750 #define V_IP_CSUM(x) ((x) << S_IP_CSUM)
751 #define F_IP_CSUM    V_IP_CSUM(1U)
752 
753 #define S_IP_ID_SPLIT    14
754 #define V_IP_ID_SPLIT(x) ((x) << S_IP_ID_SPLIT)
755 #define F_IP_ID_SPLIT    V_IP_ID_SPLIT(1U)
756 
757 #define S_PATH_MTU    15
758 #define V_PATH_MTU(x) ((x) << S_PATH_MTU)
759 #define F_PATH_MTU    V_PATH_MTU(1U)
760 
761 #define S_5TUPLE_LOOKUP    17
762 #define M_5TUPLE_LOOKUP    0x3
763 #define V_5TUPLE_LOOKUP(x) ((x) << S_5TUPLE_LOOKUP)
764 #define G_5TUPLE_LOOKUP(x) (((x) >> S_5TUPLE_LOOKUP) & M_5TUPLE_LOOKUP)
765 
766 #define S_IP_FRAGMENT_DROP    19
767 #define V_IP_FRAGMENT_DROP(x) ((x) << S_IP_FRAGMENT_DROP)
768 #define F_IP_FRAGMENT_DROP    V_IP_FRAGMENT_DROP(1U)
769 
770 #define S_PING_DROP    20
771 #define V_PING_DROP(x) ((x) << S_PING_DROP)
772 #define F_PING_DROP    V_PING_DROP(1U)
773 
774 #define S_PROTECT_MODE    21
775 #define V_PROTECT_MODE(x) ((x) << S_PROTECT_MODE)
776 #define F_PROTECT_MODE    V_PROTECT_MODE(1U)
777 
778 #define S_SYN_COOKIE_ALGORITHM    22
779 #define V_SYN_COOKIE_ALGORITHM(x) ((x) << S_SYN_COOKIE_ALGORITHM)
780 #define F_SYN_COOKIE_ALGORITHM    V_SYN_COOKIE_ALGORITHM(1U)
781 
782 #define S_ATTACK_FILTER    23
783 #define V_ATTACK_FILTER(x) ((x) << S_ATTACK_FILTER)
784 #define F_ATTACK_FILTER    V_ATTACK_FILTER(1U)
785 
786 #define S_INTERFACE_TYPE    24
787 #define V_INTERFACE_TYPE(x) ((x) << S_INTERFACE_TYPE)
788 #define F_INTERFACE_TYPE    V_INTERFACE_TYPE(1U)
789 
790 #define S_DISABLE_RX_FLOW_CONTROL    25
791 #define V_DISABLE_RX_FLOW_CONTROL(x) ((x) << S_DISABLE_RX_FLOW_CONTROL)
792 #define F_DISABLE_RX_FLOW_CONTROL    V_DISABLE_RX_FLOW_CONTROL(1U)
793 
794 #define S_SYN_COOKIE_PARAMETER    26
795 #define M_SYN_COOKIE_PARAMETER    0x3f
796 #define V_SYN_COOKIE_PARAMETER(x) ((x) << S_SYN_COOKIE_PARAMETER)
797 #define G_SYN_COOKIE_PARAMETER(x) (((x) >> S_SYN_COOKIE_PARAMETER) & M_SYN_COOKIE_PARAMETER)
798 
799 #define A_TP_GLOBAL_RX_CREDITS 0x30c
800 #define A_TP_CM_SIZE 0x310
801 #define A_TP_CM_MM_BASE 0x314
802 
803 #define S_CM_MEMMGR_BASE    0
804 #define M_CM_MEMMGR_BASE    0xfffffff
805 #define V_CM_MEMMGR_BASE(x) ((x) << S_CM_MEMMGR_BASE)
806 #define G_CM_MEMMGR_BASE(x) (((x) >> S_CM_MEMMGR_BASE) & M_CM_MEMMGR_BASE)
807 
808 #define A_TP_CM_TIMER_BASE 0x318
809 
810 #define S_CM_TIMER_BASE    0
811 #define M_CM_TIMER_BASE    0xfffffff
812 #define V_CM_TIMER_BASE(x) ((x) << S_CM_TIMER_BASE)
813 #define G_CM_TIMER_BASE(x) (((x) >> S_CM_TIMER_BASE) & M_CM_TIMER_BASE)
814 
815 #define A_TP_PM_SIZE 0x31c
816 #define A_TP_PM_TX_BASE 0x320
817 #define A_TP_PM_DEFRAG_BASE 0x324
818 #define A_TP_PM_RX_BASE 0x328
819 #define A_TP_PM_RX_PG_SIZE 0x32c
820 #define A_TP_PM_RX_MAX_PGS 0x330
821 #define A_TP_PM_TX_PG_SIZE 0x334
822 #define A_TP_PM_TX_MAX_PGS 0x338
823 #define A_TP_TCP_OPTIONS 0x340
824 
825 #define S_TIMESTAMP    0
826 #define M_TIMESTAMP    0x3
827 #define V_TIMESTAMP(x) ((x) << S_TIMESTAMP)
828 #define G_TIMESTAMP(x) (((x) >> S_TIMESTAMP) & M_TIMESTAMP)
829 
830 #define S_WINDOW_SCALE    2
831 #define M_WINDOW_SCALE    0x3
832 #define V_WINDOW_SCALE(x) ((x) << S_WINDOW_SCALE)
833 #define G_WINDOW_SCALE(x) (((x) >> S_WINDOW_SCALE) & M_WINDOW_SCALE)
834 
835 #define S_SACK    4
836 #define M_SACK    0x3
837 #define V_SACK(x) ((x) << S_SACK)
838 #define G_SACK(x) (((x) >> S_SACK) & M_SACK)
839 
840 #define S_ECN    6
841 #define M_ECN    0x3
842 #define V_ECN(x) ((x) << S_ECN)
843 #define G_ECN(x) (((x) >> S_ECN) & M_ECN)
844 
845 #define S_SACK_ALGORITHM    8
846 #define M_SACK_ALGORITHM    0x3
847 #define V_SACK_ALGORITHM(x) ((x) << S_SACK_ALGORITHM)
848 #define G_SACK_ALGORITHM(x) (((x) >> S_SACK_ALGORITHM) & M_SACK_ALGORITHM)
849 
850 #define S_MSS    10
851 #define V_MSS(x) ((x) << S_MSS)
852 #define F_MSS    V_MSS(1U)
853 
854 #define S_DEFAULT_PEER_MSS    16
855 #define M_DEFAULT_PEER_MSS    0xffff
856 #define V_DEFAULT_PEER_MSS(x) ((x) << S_DEFAULT_PEER_MSS)
857 #define G_DEFAULT_PEER_MSS(x) (((x) >> S_DEFAULT_PEER_MSS) & M_DEFAULT_PEER_MSS)
858 
859 #define A_TP_DACK_CONFIG 0x344
860 
861 #define S_DACK_MODE    0
862 #define V_DACK_MODE(x) ((x) << S_DACK_MODE)
863 #define F_DACK_MODE    V_DACK_MODE(1U)
864 
865 #define S_DACK_AUTO_MGMT    1
866 #define V_DACK_AUTO_MGMT(x) ((x) << S_DACK_AUTO_MGMT)
867 #define F_DACK_AUTO_MGMT    V_DACK_AUTO_MGMT(1U)
868 
869 #define S_DACK_AUTO_CAREFUL    2
870 #define V_DACK_AUTO_CAREFUL(x) ((x) << S_DACK_AUTO_CAREFUL)
871 #define F_DACK_AUTO_CAREFUL    V_DACK_AUTO_CAREFUL(1U)
872 
873 #define S_DACK_MSS_SELECTOR    3
874 #define M_DACK_MSS_SELECTOR    0x3
875 #define V_DACK_MSS_SELECTOR(x) ((x) << S_DACK_MSS_SELECTOR)
876 #define G_DACK_MSS_SELECTOR(x) (((x) >> S_DACK_MSS_SELECTOR) & M_DACK_MSS_SELECTOR)
877 
878 #define S_DACK_BYTE_THRESHOLD    5
879 #define M_DACK_BYTE_THRESHOLD    0xfffff
880 #define V_DACK_BYTE_THRESHOLD(x) ((x) << S_DACK_BYTE_THRESHOLD)
881 #define G_DACK_BYTE_THRESHOLD(x) (((x) >> S_DACK_BYTE_THRESHOLD) & M_DACK_BYTE_THRESHOLD)
882 
883 #define A_TP_PC_CONFIG 0x348
884 
885 #define S_TP_ACCESS_LATENCY    0
886 #define M_TP_ACCESS_LATENCY    0xf
887 #define V_TP_ACCESS_LATENCY(x) ((x) << S_TP_ACCESS_LATENCY)
888 #define G_TP_ACCESS_LATENCY(x) (((x) >> S_TP_ACCESS_LATENCY) & M_TP_ACCESS_LATENCY)
889 
890 #define S_HELD_FIN_DISABLE    4
891 #define V_HELD_FIN_DISABLE(x) ((x) << S_HELD_FIN_DISABLE)
892 #define F_HELD_FIN_DISABLE    V_HELD_FIN_DISABLE(1U)
893 
894 #define S_DDP_FC_ENABLE    5
895 #define V_DDP_FC_ENABLE(x) ((x) << S_DDP_FC_ENABLE)
896 #define F_DDP_FC_ENABLE    V_DDP_FC_ENABLE(1U)
897 
898 #define S_RDMA_ERR_ENABLE    6
899 #define V_RDMA_ERR_ENABLE(x) ((x) << S_RDMA_ERR_ENABLE)
900 #define F_RDMA_ERR_ENABLE    V_RDMA_ERR_ENABLE(1U)
901 
902 #define S_FAST_PDU_DELIVERY    7
903 #define V_FAST_PDU_DELIVERY(x) ((x) << S_FAST_PDU_DELIVERY)
904 #define F_FAST_PDU_DELIVERY    V_FAST_PDU_DELIVERY(1U)
905 
906 #define S_CLEAR_FIN    8
907 #define V_CLEAR_FIN(x) ((x) << S_CLEAR_FIN)
908 #define F_CLEAR_FIN    V_CLEAR_FIN(1U)
909 
910 #define S_DIS_TX_FILL_WIN_PUSH	  12
911 #define V_DIS_TX_FILL_WIN_PUSH(x) ((x) << S_DIS_TX_FILL_WIN_PUSH)
912 #define F_DIS_TX_FILL_WIN_PUSH	  V_DIS_TX_FILL_WIN_PUSH(1U)
913 
914 #define S_TP_PC_REV    30
915 #define M_TP_PC_REV    0x3
916 #define V_TP_PC_REV(x) ((x) << S_TP_PC_REV)
917 #define G_TP_PC_REV(x) (((x) >> S_TP_PC_REV) & M_TP_PC_REV)
918 
919 #define A_TP_BACKOFF0 0x350
920 
921 #define S_ELEMENT0    0
922 #define M_ELEMENT0    0xff
923 #define V_ELEMENT0(x) ((x) << S_ELEMENT0)
924 #define G_ELEMENT0(x) (((x) >> S_ELEMENT0) & M_ELEMENT0)
925 
926 #define S_ELEMENT1    8
927 #define M_ELEMENT1    0xff
928 #define V_ELEMENT1(x) ((x) << S_ELEMENT1)
929 #define G_ELEMENT1(x) (((x) >> S_ELEMENT1) & M_ELEMENT1)
930 
931 #define S_ELEMENT2    16
932 #define M_ELEMENT2    0xff
933 #define V_ELEMENT2(x) ((x) << S_ELEMENT2)
934 #define G_ELEMENT2(x) (((x) >> S_ELEMENT2) & M_ELEMENT2)
935 
936 #define S_ELEMENT3    24
937 #define M_ELEMENT3    0xff
938 #define V_ELEMENT3(x) ((x) << S_ELEMENT3)
939 #define G_ELEMENT3(x) (((x) >> S_ELEMENT3) & M_ELEMENT3)
940 
941 #define A_TP_BACKOFF1 0x354
942 #define A_TP_BACKOFF2 0x358
943 #define A_TP_BACKOFF3 0x35c
944 #define A_TP_PARA_REG0 0x360
945 
946 #define S_VAR_MULT    0
947 #define M_VAR_MULT    0xf
948 #define V_VAR_MULT(x) ((x) << S_VAR_MULT)
949 #define G_VAR_MULT(x) (((x) >> S_VAR_MULT) & M_VAR_MULT)
950 
951 #define S_VAR_GAIN    4
952 #define M_VAR_GAIN    0xf
953 #define V_VAR_GAIN(x) ((x) << S_VAR_GAIN)
954 #define G_VAR_GAIN(x) (((x) >> S_VAR_GAIN) & M_VAR_GAIN)
955 
956 #define S_SRTT_GAIN    8
957 #define M_SRTT_GAIN    0xf
958 #define V_SRTT_GAIN(x) ((x) << S_SRTT_GAIN)
959 #define G_SRTT_GAIN(x) (((x) >> S_SRTT_GAIN) & M_SRTT_GAIN)
960 
961 #define S_RTTVAR_INIT    12
962 #define M_RTTVAR_INIT    0xf
963 #define V_RTTVAR_INIT(x) ((x) << S_RTTVAR_INIT)
964 #define G_RTTVAR_INIT(x) (((x) >> S_RTTVAR_INIT) & M_RTTVAR_INIT)
965 
966 #define S_DUP_THRESH    20
967 #define M_DUP_THRESH    0xf
968 #define V_DUP_THRESH(x) ((x) << S_DUP_THRESH)
969 #define G_DUP_THRESH(x) (((x) >> S_DUP_THRESH) & M_DUP_THRESH)
970 
971 #define S_INIT_CONG_WIN    24
972 #define M_INIT_CONG_WIN    0x7
973 #define V_INIT_CONG_WIN(x) ((x) << S_INIT_CONG_WIN)
974 #define G_INIT_CONG_WIN(x) (((x) >> S_INIT_CONG_WIN) & M_INIT_CONG_WIN)
975 
976 #define A_TP_PARA_REG1 0x364
977 
978 #define S_INITIAL_SLOW_START_THRESHOLD    0
979 #define M_INITIAL_SLOW_START_THRESHOLD    0xffff
980 #define V_INITIAL_SLOW_START_THRESHOLD(x) ((x) << S_INITIAL_SLOW_START_THRESHOLD)
981 #define G_INITIAL_SLOW_START_THRESHOLD(x) (((x) >> S_INITIAL_SLOW_START_THRESHOLD) & M_INITIAL_SLOW_START_THRESHOLD)
982 
983 #define S_RECEIVE_BUFFER_SIZE    16
984 #define M_RECEIVE_BUFFER_SIZE    0xffff
985 #define V_RECEIVE_BUFFER_SIZE(x) ((x) << S_RECEIVE_BUFFER_SIZE)
986 #define G_RECEIVE_BUFFER_SIZE(x) (((x) >> S_RECEIVE_BUFFER_SIZE) & M_RECEIVE_BUFFER_SIZE)
987 
988 #define A_TP_PARA_REG2 0x368
989 
990 #define S_RX_COALESCE_SIZE    0
991 #define M_RX_COALESCE_SIZE    0xffff
992 #define V_RX_COALESCE_SIZE(x) ((x) << S_RX_COALESCE_SIZE)
993 #define G_RX_COALESCE_SIZE(x) (((x) >> S_RX_COALESCE_SIZE) & M_RX_COALESCE_SIZE)
994 
995 #define S_MAX_RX_SIZE    16
996 #define M_MAX_RX_SIZE    0xffff
997 #define V_MAX_RX_SIZE(x) ((x) << S_MAX_RX_SIZE)
998 #define G_MAX_RX_SIZE(x) (((x) >> S_MAX_RX_SIZE) & M_MAX_RX_SIZE)
999 
1000 #define A_TP_PARA_REG3 0x36c
1001 
1002 #define S_RX_COALESCING_PSH_DELIVER    0
1003 #define V_RX_COALESCING_PSH_DELIVER(x) ((x) << S_RX_COALESCING_PSH_DELIVER)
1004 #define F_RX_COALESCING_PSH_DELIVER    V_RX_COALESCING_PSH_DELIVER(1U)
1005 
1006 #define S_RX_COALESCING_ENABLE    1
1007 #define V_RX_COALESCING_ENABLE(x) ((x) << S_RX_COALESCING_ENABLE)
1008 #define F_RX_COALESCING_ENABLE    V_RX_COALESCING_ENABLE(1U)
1009 
1010 #define S_TAHOE_ENABLE    2
1011 #define V_TAHOE_ENABLE(x) ((x) << S_TAHOE_ENABLE)
1012 #define F_TAHOE_ENABLE    V_TAHOE_ENABLE(1U)
1013 
1014 #define S_MAX_REORDER_FRAGMENTS    12
1015 #define M_MAX_REORDER_FRAGMENTS    0x7
1016 #define V_MAX_REORDER_FRAGMENTS(x) ((x) << S_MAX_REORDER_FRAGMENTS)
1017 #define G_MAX_REORDER_FRAGMENTS(x) (((x) >> S_MAX_REORDER_FRAGMENTS) & M_MAX_REORDER_FRAGMENTS)
1018 
1019 #define A_TP_TIMER_RESOLUTION 0x390
1020 
1021 #define S_DELAYED_ACK_TIMER_RESOLUTION    0
1022 #define M_DELAYED_ACK_TIMER_RESOLUTION    0x3f
1023 #define V_DELAYED_ACK_TIMER_RESOLUTION(x) ((x) << S_DELAYED_ACK_TIMER_RESOLUTION)
1024 #define G_DELAYED_ACK_TIMER_RESOLUTION(x) (((x) >> S_DELAYED_ACK_TIMER_RESOLUTION) & M_DELAYED_ACK_TIMER_RESOLUTION)
1025 
1026 #define S_GENERIC_TIMER_RESOLUTION    16
1027 #define M_GENERIC_TIMER_RESOLUTION    0x3f
1028 #define V_GENERIC_TIMER_RESOLUTION(x) ((x) << S_GENERIC_TIMER_RESOLUTION)
1029 #define G_GENERIC_TIMER_RESOLUTION(x) (((x) >> S_GENERIC_TIMER_RESOLUTION) & M_GENERIC_TIMER_RESOLUTION)
1030 
1031 #define A_TP_2MSL 0x394
1032 
1033 #define S_2MSL    0
1034 #define M_2MSL    0x3fffffff
1035 #define V_2MSL(x) ((x) << S_2MSL)
1036 #define G_2MSL(x) (((x) >> S_2MSL) & M_2MSL)
1037 
1038 #define A_TP_RXT_MIN 0x398
1039 
1040 #define S_RETRANSMIT_TIMER_MIN    0
1041 #define M_RETRANSMIT_TIMER_MIN    0xffff
1042 #define V_RETRANSMIT_TIMER_MIN(x) ((x) << S_RETRANSMIT_TIMER_MIN)
1043 #define G_RETRANSMIT_TIMER_MIN(x) (((x) >> S_RETRANSMIT_TIMER_MIN) & M_RETRANSMIT_TIMER_MIN)
1044 
1045 #define A_TP_RXT_MAX 0x39c
1046 
1047 #define S_RETRANSMIT_TIMER_MAX    0
1048 #define M_RETRANSMIT_TIMER_MAX    0x3fffffff
1049 #define V_RETRANSMIT_TIMER_MAX(x) ((x) << S_RETRANSMIT_TIMER_MAX)
1050 #define G_RETRANSMIT_TIMER_MAX(x) (((x) >> S_RETRANSMIT_TIMER_MAX) & M_RETRANSMIT_TIMER_MAX)
1051 
1052 #define A_TP_PERS_MIN 0x3a0
1053 
1054 #define S_PERSIST_TIMER_MIN    0
1055 #define M_PERSIST_TIMER_MIN    0xffff
1056 #define V_PERSIST_TIMER_MIN(x) ((x) << S_PERSIST_TIMER_MIN)
1057 #define G_PERSIST_TIMER_MIN(x) (((x) >> S_PERSIST_TIMER_MIN) & M_PERSIST_TIMER_MIN)
1058 
1059 #define A_TP_PERS_MAX 0x3a4
1060 
1061 #define S_PERSIST_TIMER_MAX    0
1062 #define M_PERSIST_TIMER_MAX    0x3fffffff
1063 #define V_PERSIST_TIMER_MAX(x) ((x) << S_PERSIST_TIMER_MAX)
1064 #define G_PERSIST_TIMER_MAX(x) (((x) >> S_PERSIST_TIMER_MAX) & M_PERSIST_TIMER_MAX)
1065 
1066 #define A_TP_KEEP_IDLE 0x3ac
1067 
1068 #define S_KEEP_ALIVE_IDLE_TIME    0
1069 #define M_KEEP_ALIVE_IDLE_TIME    0x3fffffff
1070 #define V_KEEP_ALIVE_IDLE_TIME(x) ((x) << S_KEEP_ALIVE_IDLE_TIME)
1071 #define G_KEEP_ALIVE_IDLE_TIME(x) (((x) >> S_KEEP_ALIVE_IDLE_TIME) & M_KEEP_ALIVE_IDLE_TIME)
1072 
1073 #define A_TP_KEEP_INTVL 0x3b0
1074 
1075 #define S_KEEP_ALIVE_INTERVAL_TIME    0
1076 #define M_KEEP_ALIVE_INTERVAL_TIME    0x3fffffff
1077 #define V_KEEP_ALIVE_INTERVAL_TIME(x) ((x) << S_KEEP_ALIVE_INTERVAL_TIME)
1078 #define G_KEEP_ALIVE_INTERVAL_TIME(x) (((x) >> S_KEEP_ALIVE_INTERVAL_TIME) & M_KEEP_ALIVE_INTERVAL_TIME)
1079 
1080 #define A_TP_INIT_SRTT 0x3b4
1081 
1082 #define S_INITIAL_SRTT    0
1083 #define M_INITIAL_SRTT    0xffff
1084 #define V_INITIAL_SRTT(x) ((x) << S_INITIAL_SRTT)
1085 #define G_INITIAL_SRTT(x) (((x) >> S_INITIAL_SRTT) & M_INITIAL_SRTT)
1086 
1087 #define A_TP_DACK_TIME 0x3b8
1088 
1089 #define S_DELAYED_ACK_TIME    0
1090 #define M_DELAYED_ACK_TIME    0x7ff
1091 #define V_DELAYED_ACK_TIME(x) ((x) << S_DELAYED_ACK_TIME)
1092 #define G_DELAYED_ACK_TIME(x) (((x) >> S_DELAYED_ACK_TIME) & M_DELAYED_ACK_TIME)
1093 
1094 #define A_TP_FINWAIT2_TIME 0x3bc
1095 
1096 #define S_FINWAIT2_TIME    0
1097 #define M_FINWAIT2_TIME    0x3fffffff
1098 #define V_FINWAIT2_TIME(x) ((x) << S_FINWAIT2_TIME)
1099 #define G_FINWAIT2_TIME(x) (((x) >> S_FINWAIT2_TIME) & M_FINWAIT2_TIME)
1100 
1101 #define A_TP_FAST_FINWAIT2_TIME 0x3c0
1102 
1103 #define S_FAST_FINWAIT2_TIME    0
1104 #define M_FAST_FINWAIT2_TIME    0x3fffffff
1105 #define V_FAST_FINWAIT2_TIME(x) ((x) << S_FAST_FINWAIT2_TIME)
1106 #define G_FAST_FINWAIT2_TIME(x) (((x) >> S_FAST_FINWAIT2_TIME) & M_FAST_FINWAIT2_TIME)
1107 
1108 #define A_TP_SHIFT_CNT 0x3c4
1109 
1110 #define S_KEEPALIVE_MAX    0
1111 #define M_KEEPALIVE_MAX    0xff
1112 #define V_KEEPALIVE_MAX(x) ((x) << S_KEEPALIVE_MAX)
1113 #define G_KEEPALIVE_MAX(x) (((x) >> S_KEEPALIVE_MAX) & M_KEEPALIVE_MAX)
1114 
1115 #define S_WINDOWPROBE_MAX    8
1116 #define M_WINDOWPROBE_MAX    0xff
1117 #define V_WINDOWPROBE_MAX(x) ((x) << S_WINDOWPROBE_MAX)
1118 #define G_WINDOWPROBE_MAX(x) (((x) >> S_WINDOWPROBE_MAX) & M_WINDOWPROBE_MAX)
1119 
1120 #define S_RETRANSMISSION_MAX    16
1121 #define M_RETRANSMISSION_MAX    0xff
1122 #define V_RETRANSMISSION_MAX(x) ((x) << S_RETRANSMISSION_MAX)
1123 #define G_RETRANSMISSION_MAX(x) (((x) >> S_RETRANSMISSION_MAX) & M_RETRANSMISSION_MAX)
1124 
1125 #define S_SYN_MAX    24
1126 #define M_SYN_MAX    0xff
1127 #define V_SYN_MAX(x) ((x) << S_SYN_MAX)
1128 #define G_SYN_MAX(x) (((x) >> S_SYN_MAX) & M_SYN_MAX)
1129 
1130 #define A_TP_QOS_REG0 0x3e0
1131 
1132 #define S_L3_VALUE    0
1133 #define M_L3_VALUE    0x3f
1134 #define V_L3_VALUE(x) ((x) << S_L3_VALUE)
1135 #define G_L3_VALUE(x) (((x) >> S_L3_VALUE) & M_L3_VALUE)
1136 
1137 #define A_TP_QOS_REG1 0x3e4
1138 #define A_TP_QOS_REG2 0x3e8
1139 #define A_TP_QOS_REG3 0x3ec
1140 #define A_TP_QOS_REG4 0x3f0
1141 #define A_TP_QOS_REG5 0x3f4
1142 #define A_TP_QOS_REG6 0x3f8
1143 #define A_TP_QOS_REG7 0x3fc
1144 #define A_TP_MTU_REG0 0x404
1145 #define A_TP_MTU_REG1 0x408
1146 #define A_TP_MTU_REG2 0x40c
1147 #define A_TP_MTU_REG3 0x410
1148 #define A_TP_MTU_REG4 0x414
1149 #define A_TP_MTU_REG5 0x418
1150 #define A_TP_MTU_REG6 0x41c
1151 #define A_TP_MTU_REG7 0x420
1152 #define A_TP_RESET 0x44c
1153 
1154 #define S_TP_RESET    0
1155 #define V_TP_RESET(x) ((x) << S_TP_RESET)
1156 #define F_TP_RESET    V_TP_RESET(1U)
1157 
1158 #define S_CM_MEMMGR_INIT    1
1159 #define V_CM_MEMMGR_INIT(x) ((x) << S_CM_MEMMGR_INIT)
1160 #define F_CM_MEMMGR_INIT    V_CM_MEMMGR_INIT(1U)
1161 
1162 #define A_TP_MIB_INDEX 0x450
1163 #define A_TP_MIB_DATA 0x454
1164 #define A_TP_SYNC_TIME_HI 0x458
1165 #define A_TP_SYNC_TIME_LO 0x45c
1166 #define A_TP_CM_MM_RX_FLST_BASE 0x460
1167 
1168 #define S_CM_MEMMGR_RX_FREE_LIST_BASE    0
1169 #define M_CM_MEMMGR_RX_FREE_LIST_BASE    0xfffffff
1170 #define V_CM_MEMMGR_RX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_RX_FREE_LIST_BASE)
1171 #define G_CM_MEMMGR_RX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_RX_FREE_LIST_BASE) & M_CM_MEMMGR_RX_FREE_LIST_BASE)
1172 
1173 #define A_TP_CM_MM_TX_FLST_BASE 0x464
1174 
1175 #define S_CM_MEMMGR_TX_FREE_LIST_BASE    0
1176 #define M_CM_MEMMGR_TX_FREE_LIST_BASE    0xfffffff
1177 #define V_CM_MEMMGR_TX_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_TX_FREE_LIST_BASE)
1178 #define G_CM_MEMMGR_TX_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_TX_FREE_LIST_BASE) & M_CM_MEMMGR_TX_FREE_LIST_BASE)
1179 
1180 #define A_TP_CM_MM_P_FLST_BASE 0x468
1181 
1182 #define S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE    0
1183 #define M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE    0xfffffff
1184 #define V_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) ((x) << S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE)
1185 #define G_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE(x) (((x) >> S_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE) & M_CM_MEMMGR_PSTRUCT_FREE_LIST_BASE)
1186 
1187 #define A_TP_CM_MM_MAX_P 0x46c
1188 
1189 #define S_CM_MEMMGR_MAX_PSTRUCT    0
1190 #define M_CM_MEMMGR_MAX_PSTRUCT    0xfffffff
1191 #define V_CM_MEMMGR_MAX_PSTRUCT(x) ((x) << S_CM_MEMMGR_MAX_PSTRUCT)
1192 #define G_CM_MEMMGR_MAX_PSTRUCT(x) (((x) >> S_CM_MEMMGR_MAX_PSTRUCT) & M_CM_MEMMGR_MAX_PSTRUCT)
1193 
1194 #define A_TP_INT_ENABLE 0x470
1195 
1196 #define S_TX_FREE_LIST_EMPTY    0
1197 #define V_TX_FREE_LIST_EMPTY(x) ((x) << S_TX_FREE_LIST_EMPTY)
1198 #define F_TX_FREE_LIST_EMPTY    V_TX_FREE_LIST_EMPTY(1U)
1199 
1200 #define S_RX_FREE_LIST_EMPTY    1
1201 #define V_RX_FREE_LIST_EMPTY(x) ((x) << S_RX_FREE_LIST_EMPTY)
1202 #define F_RX_FREE_LIST_EMPTY    V_RX_FREE_LIST_EMPTY(1U)
1203 
1204 #define A_TP_INT_CAUSE 0x474
1205 #define A_TP_TIMER_SEPARATOR 0x4a4
1206 
1207 #define S_DISABLE_PAST_TIMER_INSERTION    0
1208 #define V_DISABLE_PAST_TIMER_INSERTION(x) ((x) << S_DISABLE_PAST_TIMER_INSERTION)
1209 #define F_DISABLE_PAST_TIMER_INSERTION    V_DISABLE_PAST_TIMER_INSERTION(1U)
1210 
1211 #define S_MODULATION_TIMER_SEPARATOR    1
1212 #define M_MODULATION_TIMER_SEPARATOR    0x7fff
1213 #define V_MODULATION_TIMER_SEPARATOR(x) ((x) << S_MODULATION_TIMER_SEPARATOR)
1214 #define G_MODULATION_TIMER_SEPARATOR(x) (((x) >> S_MODULATION_TIMER_SEPARATOR) & M_MODULATION_TIMER_SEPARATOR)
1215 
1216 #define S_GLOBAL_TIMER_SEPARATOR    16
1217 #define M_GLOBAL_TIMER_SEPARATOR    0xffff
1218 #define V_GLOBAL_TIMER_SEPARATOR(x) ((x) << S_GLOBAL_TIMER_SEPARATOR)
1219 #define G_GLOBAL_TIMER_SEPARATOR(x) (((x) >> S_GLOBAL_TIMER_SEPARATOR) & M_GLOBAL_TIMER_SEPARATOR)
1220 
1221 #define A_TP_CM_FC_MODE 0x4b0
1222 #define A_TP_PC_CONGESTION_CNTL 0x4b4
1223 #define A_TP_TX_DROP_CONFIG 0x4b8
1224 
1225 #define S_ENABLE_TX_DROP    31
1226 #define V_ENABLE_TX_DROP(x) ((x) << S_ENABLE_TX_DROP)
1227 #define F_ENABLE_TX_DROP    V_ENABLE_TX_DROP(1U)
1228 
1229 #define S_ENABLE_TX_ERROR    30
1230 #define V_ENABLE_TX_ERROR(x) ((x) << S_ENABLE_TX_ERROR)
1231 #define F_ENABLE_TX_ERROR    V_ENABLE_TX_ERROR(1U)
1232 
1233 #define S_DROP_TICKS_CNT    4
1234 #define M_DROP_TICKS_CNT    0x3ffffff
1235 #define V_DROP_TICKS_CNT(x) ((x) << S_DROP_TICKS_CNT)
1236 #define G_DROP_TICKS_CNT(x) (((x) >> S_DROP_TICKS_CNT) & M_DROP_TICKS_CNT)
1237 
1238 #define S_NUM_PKTS_DROPPED    0
1239 #define M_NUM_PKTS_DROPPED    0xf
1240 #define V_NUM_PKTS_DROPPED(x) ((x) << S_NUM_PKTS_DROPPED)
1241 #define G_NUM_PKTS_DROPPED(x) (((x) >> S_NUM_PKTS_DROPPED) & M_NUM_PKTS_DROPPED)
1242 
1243 #define A_TP_TX_DROP_COUNT 0x4bc
1244 
1245 /* RAT registers */
1246 #define A_RAT_ROUTE_CONTROL 0x580
1247 
1248 #define S_USE_ROUTE_TABLE    0
1249 #define V_USE_ROUTE_TABLE(x) ((x) << S_USE_ROUTE_TABLE)
1250 #define F_USE_ROUTE_TABLE    V_USE_ROUTE_TABLE(1U)
1251 
1252 #define S_ENABLE_CSPI    1
1253 #define V_ENABLE_CSPI(x) ((x) << S_ENABLE_CSPI)
1254 #define F_ENABLE_CSPI    V_ENABLE_CSPI(1U)
1255 
1256 #define S_ENABLE_PCIX    2
1257 #define V_ENABLE_PCIX(x) ((x) << S_ENABLE_PCIX)
1258 #define F_ENABLE_PCIX    V_ENABLE_PCIX(1U)
1259 
1260 #define A_RAT_ROUTE_TABLE_INDEX 0x584
1261 
1262 #define S_ROUTE_TABLE_INDEX    0
1263 #define M_ROUTE_TABLE_INDEX    0xf
1264 #define V_ROUTE_TABLE_INDEX(x) ((x) << S_ROUTE_TABLE_INDEX)
1265 #define G_ROUTE_TABLE_INDEX(x) (((x) >> S_ROUTE_TABLE_INDEX) & M_ROUTE_TABLE_INDEX)
1266 
1267 #define A_RAT_ROUTE_TABLE_DATA 0x588
1268 #define A_RAT_NO_ROUTE 0x58c
1269 
1270 #define S_CPL_OPCODE    0
1271 #define M_CPL_OPCODE    0xff
1272 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)
1273 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & M_CPL_OPCODE)
1274 
1275 #define A_RAT_INTR_ENABLE 0x590
1276 
1277 #define S_ZEROROUTEERROR    0
1278 #define V_ZEROROUTEERROR(x) ((x) << S_ZEROROUTEERROR)
1279 #define F_ZEROROUTEERROR    V_ZEROROUTEERROR(1U)
1280 
1281 #define S_CSPIFRAMINGERROR    1
1282 #define V_CSPIFRAMINGERROR(x) ((x) << S_CSPIFRAMINGERROR)
1283 #define F_CSPIFRAMINGERROR    V_CSPIFRAMINGERROR(1U)
1284 
1285 #define S_SGEFRAMINGERROR    2
1286 #define V_SGEFRAMINGERROR(x) ((x) << S_SGEFRAMINGERROR)
1287 #define F_SGEFRAMINGERROR    V_SGEFRAMINGERROR(1U)
1288 
1289 #define S_TPFRAMINGERROR    3
1290 #define V_TPFRAMINGERROR(x) ((x) << S_TPFRAMINGERROR)
1291 #define F_TPFRAMINGERROR    V_TPFRAMINGERROR(1U)
1292 
1293 #define A_RAT_INTR_CAUSE 0x594
1294 
1295 /* CSPI registers */
1296 #define A_CSPI_RX_AE_WM 0x810
1297 #define A_CSPI_RX_AF_WM 0x814
1298 #define A_CSPI_CALENDAR_LEN 0x818
1299 
1300 #define S_CALENDARLENGTH    0
1301 #define M_CALENDARLENGTH    0xffff
1302 #define V_CALENDARLENGTH(x) ((x) << S_CALENDARLENGTH)
1303 #define G_CALENDARLENGTH(x) (((x) >> S_CALENDARLENGTH) & M_CALENDARLENGTH)
1304 
1305 #define A_CSPI_FIFO_STATUS_ENABLE 0x820
1306 
1307 #define S_FIFOSTATUSENABLE    0
1308 #define V_FIFOSTATUSENABLE(x) ((x) << S_FIFOSTATUSENABLE)
1309 #define F_FIFOSTATUSENABLE    V_FIFOSTATUSENABLE(1U)
1310 
1311 #define A_CSPI_MAXBURST1_MAXBURST2 0x828
1312 
1313 #define S_MAXBURST1    0
1314 #define M_MAXBURST1    0xffff
1315 #define V_MAXBURST1(x) ((x) << S_MAXBURST1)
1316 #define G_MAXBURST1(x) (((x) >> S_MAXBURST1) & M_MAXBURST1)
1317 
1318 #define S_MAXBURST2    16
1319 #define M_MAXBURST2    0xffff
1320 #define V_MAXBURST2(x) ((x) << S_MAXBURST2)
1321 #define G_MAXBURST2(x) (((x) >> S_MAXBURST2) & M_MAXBURST2)
1322 
1323 #define A_CSPI_TRAIN 0x82c
1324 
1325 #define S_CSPI_TRAIN_ALPHA    0
1326 #define M_CSPI_TRAIN_ALPHA    0xffff
1327 #define V_CSPI_TRAIN_ALPHA(x) ((x) << S_CSPI_TRAIN_ALPHA)
1328 #define G_CSPI_TRAIN_ALPHA(x) (((x) >> S_CSPI_TRAIN_ALPHA) & M_CSPI_TRAIN_ALPHA)
1329 
1330 #define S_CSPI_TRAIN_DATA_MAXT    16
1331 #define M_CSPI_TRAIN_DATA_MAXT    0xffff
1332 #define V_CSPI_TRAIN_DATA_MAXT(x) ((x) << S_CSPI_TRAIN_DATA_MAXT)
1333 #define G_CSPI_TRAIN_DATA_MAXT(x) (((x) >> S_CSPI_TRAIN_DATA_MAXT) & M_CSPI_TRAIN_DATA_MAXT)
1334 
1335 #define A_CSPI_INTR_STATUS 0x848
1336 
1337 #define S_DIP4ERR    0
1338 #define V_DIP4ERR(x) ((x) << S_DIP4ERR)
1339 #define F_DIP4ERR    V_DIP4ERR(1U)
1340 
1341 #define S_RXDROP    1
1342 #define V_RXDROP(x) ((x) << S_RXDROP)
1343 #define F_RXDROP    V_RXDROP(1U)
1344 
1345 #define S_TXDROP    2
1346 #define V_TXDROP(x) ((x) << S_TXDROP)
1347 #define F_TXDROP    V_TXDROP(1U)
1348 
1349 #define S_RXOVERFLOW    3
1350 #define V_RXOVERFLOW(x) ((x) << S_RXOVERFLOW)
1351 #define F_RXOVERFLOW    V_RXOVERFLOW(1U)
1352 
1353 #define S_RAMPARITYERR    4
1354 #define V_RAMPARITYERR(x) ((x) << S_RAMPARITYERR)
1355 #define F_RAMPARITYERR    V_RAMPARITYERR(1U)
1356 
1357 #define A_CSPI_INTR_ENABLE 0x84c
1358 
1359 /* ESPI registers */
1360 #define A_ESPI_SCH_TOKEN0 0x880
1361 
1362 #define S_SCHTOKEN0    0
1363 #define M_SCHTOKEN0    0xffff
1364 #define V_SCHTOKEN0(x) ((x) << S_SCHTOKEN0)
1365 #define G_SCHTOKEN0(x) (((x) >> S_SCHTOKEN0) & M_SCHTOKEN0)
1366 
1367 #define A_ESPI_SCH_TOKEN1 0x884
1368 
1369 #define S_SCHTOKEN1    0
1370 #define M_SCHTOKEN1    0xffff
1371 #define V_SCHTOKEN1(x) ((x) << S_SCHTOKEN1)
1372 #define G_SCHTOKEN1(x) (((x) >> S_SCHTOKEN1) & M_SCHTOKEN1)
1373 
1374 #define A_ESPI_SCH_TOKEN2 0x888
1375 
1376 #define S_SCHTOKEN2    0
1377 #define M_SCHTOKEN2    0xffff
1378 #define V_SCHTOKEN2(x) ((x) << S_SCHTOKEN2)
1379 #define G_SCHTOKEN2(x) (((x) >> S_SCHTOKEN2) & M_SCHTOKEN2)
1380 
1381 #define A_ESPI_SCH_TOKEN3 0x88c
1382 
1383 #define S_SCHTOKEN3    0
1384 #define M_SCHTOKEN3    0xffff
1385 #define V_SCHTOKEN3(x) ((x) << S_SCHTOKEN3)
1386 #define G_SCHTOKEN3(x) (((x) >> S_SCHTOKEN3) & M_SCHTOKEN3)
1387 
1388 #define A_ESPI_RX_FIFO_ALMOST_EMPTY_WATERMARK 0x890
1389 
1390 #define S_ALMOSTEMPTY    0
1391 #define M_ALMOSTEMPTY    0xffff
1392 #define V_ALMOSTEMPTY(x) ((x) << S_ALMOSTEMPTY)
1393 #define G_ALMOSTEMPTY(x) (((x) >> S_ALMOSTEMPTY) & M_ALMOSTEMPTY)
1394 
1395 #define A_ESPI_RX_FIFO_ALMOST_FULL_WATERMARK 0x894
1396 
1397 #define S_ALMOSTFULL    0
1398 #define M_ALMOSTFULL    0xffff
1399 #define V_ALMOSTFULL(x) ((x) << S_ALMOSTFULL)
1400 #define G_ALMOSTFULL(x) (((x) >> S_ALMOSTFULL) & M_ALMOSTFULL)
1401 
1402 #define A_ESPI_CALENDAR_LENGTH 0x898
1403 #define A_PORT_CONFIG 0x89c
1404 
1405 #define S_RX_NPORTS    0
1406 #define M_RX_NPORTS    0xff
1407 #define V_RX_NPORTS(x) ((x) << S_RX_NPORTS)
1408 #define G_RX_NPORTS(x) (((x) >> S_RX_NPORTS) & M_RX_NPORTS)
1409 
1410 #define S_TX_NPORTS    8
1411 #define M_TX_NPORTS    0xff
1412 #define V_TX_NPORTS(x) ((x) << S_TX_NPORTS)
1413 #define G_TX_NPORTS(x) (((x) >> S_TX_NPORTS) & M_TX_NPORTS)
1414 
1415 #define A_ESPI_FIFO_STATUS_ENABLE 0x8a0
1416 
1417 #define S_RXSTATUSENABLE    0
1418 #define V_RXSTATUSENABLE(x) ((x) << S_RXSTATUSENABLE)
1419 #define F_RXSTATUSENABLE    V_RXSTATUSENABLE(1U)
1420 
1421 #define S_TXDROPENABLE    1
1422 #define V_TXDROPENABLE(x) ((x) << S_TXDROPENABLE)
1423 #define F_TXDROPENABLE    V_TXDROPENABLE(1U)
1424 
1425 #define S_RXENDIANMODE    2
1426 #define V_RXENDIANMODE(x) ((x) << S_RXENDIANMODE)
1427 #define F_RXENDIANMODE    V_RXENDIANMODE(1U)
1428 
1429 #define S_TXENDIANMODE    3
1430 #define V_TXENDIANMODE(x) ((x) << S_TXENDIANMODE)
1431 #define F_TXENDIANMODE    V_TXENDIANMODE(1U)
1432 
1433 #define S_INTEL1010MODE    4
1434 #define V_INTEL1010MODE(x) ((x) << S_INTEL1010MODE)
1435 #define F_INTEL1010MODE    V_INTEL1010MODE(1U)
1436 
1437 #define A_ESPI_MAXBURST1_MAXBURST2 0x8a8
1438 #define A_ESPI_TRAIN 0x8ac
1439 
1440 #define S_MAXTRAINALPHA    0
1441 #define M_MAXTRAINALPHA    0xffff
1442 #define V_MAXTRAINALPHA(x) ((x) << S_MAXTRAINALPHA)
1443 #define G_MAXTRAINALPHA(x) (((x) >> S_MAXTRAINALPHA) & M_MAXTRAINALPHA)
1444 
1445 #define S_MAXTRAINDATA    16
1446 #define M_MAXTRAINDATA    0xffff
1447 #define V_MAXTRAINDATA(x) ((x) << S_MAXTRAINDATA)
1448 #define G_MAXTRAINDATA(x) (((x) >> S_MAXTRAINDATA) & M_MAXTRAINDATA)
1449 
1450 #define A_RAM_STATUS 0x8b0
1451 
1452 #define S_RXFIFOPARITYERROR    0
1453 #define M_RXFIFOPARITYERROR    0x3ff
1454 #define V_RXFIFOPARITYERROR(x) ((x) << S_RXFIFOPARITYERROR)
1455 #define G_RXFIFOPARITYERROR(x) (((x) >> S_RXFIFOPARITYERROR) & M_RXFIFOPARITYERROR)
1456 
1457 #define S_TXFIFOPARITYERROR    10
1458 #define M_TXFIFOPARITYERROR    0x3ff
1459 #define V_TXFIFOPARITYERROR(x) ((x) << S_TXFIFOPARITYERROR)
1460 #define G_TXFIFOPARITYERROR(x) (((x) >> S_TXFIFOPARITYERROR) & M_TXFIFOPARITYERROR)
1461 
1462 #define S_RXFIFOOVERFLOW    20
1463 #define M_RXFIFOOVERFLOW    0x3ff
1464 #define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW)
1465 #define G_RXFIFOOVERFLOW(x) (((x) >> S_RXFIFOOVERFLOW) & M_RXFIFOOVERFLOW)
1466 
1467 #define A_TX_DROP_COUNT0 0x8b4
1468 
1469 #define S_TXPORT0DROPCNT    0
1470 #define M_TXPORT0DROPCNT    0xffff
1471 #define V_TXPORT0DROPCNT(x) ((x) << S_TXPORT0DROPCNT)
1472 #define G_TXPORT0DROPCNT(x) (((x) >> S_TXPORT0DROPCNT) & M_TXPORT0DROPCNT)
1473 
1474 #define S_TXPORT1DROPCNT    16
1475 #define M_TXPORT1DROPCNT    0xffff
1476 #define V_TXPORT1DROPCNT(x) ((x) << S_TXPORT1DROPCNT)
1477 #define G_TXPORT1DROPCNT(x) (((x) >> S_TXPORT1DROPCNT) & M_TXPORT1DROPCNT)
1478 
1479 #define A_TX_DROP_COUNT1 0x8b8
1480 
1481 #define S_TXPORT2DROPCNT    0
1482 #define M_TXPORT2DROPCNT    0xffff
1483 #define V_TXPORT2DROPCNT(x) ((x) << S_TXPORT2DROPCNT)
1484 #define G_TXPORT2DROPCNT(x) (((x) >> S_TXPORT2DROPCNT) & M_TXPORT2DROPCNT)
1485 
1486 #define S_TXPORT3DROPCNT    16
1487 #define M_TXPORT3DROPCNT    0xffff
1488 #define V_TXPORT3DROPCNT(x) ((x) << S_TXPORT3DROPCNT)
1489 #define G_TXPORT3DROPCNT(x) (((x) >> S_TXPORT3DROPCNT) & M_TXPORT3DROPCNT)
1490 
1491 #define A_RX_DROP_COUNT0 0x8bc
1492 
1493 #define S_RXPORT0DROPCNT    0
1494 #define M_RXPORT0DROPCNT    0xffff
1495 #define V_RXPORT0DROPCNT(x) ((x) << S_RXPORT0DROPCNT)
1496 #define G_RXPORT0DROPCNT(x) (((x) >> S_RXPORT0DROPCNT) & M_RXPORT0DROPCNT)
1497 
1498 #define S_RXPORT1DROPCNT    16
1499 #define M_RXPORT1DROPCNT    0xffff
1500 #define V_RXPORT1DROPCNT(x) ((x) << S_RXPORT1DROPCNT)
1501 #define G_RXPORT1DROPCNT(x) (((x) >> S_RXPORT1DROPCNT) & M_RXPORT1DROPCNT)
1502 
1503 #define A_RX_DROP_COUNT1 0x8c0
1504 
1505 #define S_RXPORT2DROPCNT    0
1506 #define M_RXPORT2DROPCNT    0xffff
1507 #define V_RXPORT2DROPCNT(x) ((x) << S_RXPORT2DROPCNT)
1508 #define G_RXPORT2DROPCNT(x) (((x) >> S_RXPORT2DROPCNT) & M_RXPORT2DROPCNT)
1509 
1510 #define S_RXPORT3DROPCNT    16
1511 #define M_RXPORT3DROPCNT    0xffff
1512 #define V_RXPORT3DROPCNT(x) ((x) << S_RXPORT3DROPCNT)
1513 #define G_RXPORT3DROPCNT(x) (((x) >> S_RXPORT3DROPCNT) & M_RXPORT3DROPCNT)
1514 
1515 #define A_DIP4_ERROR_COUNT 0x8c4
1516 
1517 #define S_DIP4ERRORCNT    0
1518 #define M_DIP4ERRORCNT    0xfff
1519 #define V_DIP4ERRORCNT(x) ((x) << S_DIP4ERRORCNT)
1520 #define G_DIP4ERRORCNT(x) (((x) >> S_DIP4ERRORCNT) & M_DIP4ERRORCNT)
1521 
1522 #define S_DIP4ERRORCNTSHADOW    12
1523 #define M_DIP4ERRORCNTSHADOW    0xfff
1524 #define V_DIP4ERRORCNTSHADOW(x) ((x) << S_DIP4ERRORCNTSHADOW)
1525 #define G_DIP4ERRORCNTSHADOW(x) (((x) >> S_DIP4ERRORCNTSHADOW) & M_DIP4ERRORCNTSHADOW)
1526 
1527 #define S_TRICN_RX_TRAIN_ERR    24
1528 #define V_TRICN_RX_TRAIN_ERR(x) ((x) << S_TRICN_RX_TRAIN_ERR)
1529 #define F_TRICN_RX_TRAIN_ERR    V_TRICN_RX_TRAIN_ERR(1U)
1530 
1531 #define S_TRICN_RX_TRAINING    25
1532 #define V_TRICN_RX_TRAINING(x) ((x) << S_TRICN_RX_TRAINING)
1533 #define F_TRICN_RX_TRAINING    V_TRICN_RX_TRAINING(1U)
1534 
1535 #define S_TRICN_RX_TRAIN_OK    26
1536 #define V_TRICN_RX_TRAIN_OK(x) ((x) << S_TRICN_RX_TRAIN_OK)
1537 #define F_TRICN_RX_TRAIN_OK    V_TRICN_RX_TRAIN_OK(1U)
1538 
1539 #define A_ESPI_INTR_STATUS 0x8c8
1540 
1541 #define S_DIP2PARITYERR    5
1542 #define V_DIP2PARITYERR(x) ((x) << S_DIP2PARITYERR)
1543 #define F_DIP2PARITYERR    V_DIP2PARITYERR(1U)
1544 
1545 #define A_ESPI_INTR_ENABLE 0x8cc
1546 #define A_RX_DROP_THRESHOLD 0x8d0
1547 #define A_ESPI_RX_RESET 0x8ec
1548 
1549 #define S_ESPI_RX_LNK_RST    0
1550 #define V_ESPI_RX_LNK_RST(x) ((x) << S_ESPI_RX_LNK_RST)
1551 #define F_ESPI_RX_LNK_RST    V_ESPI_RX_LNK_RST(1U)
1552 
1553 #define S_ESPI_RX_CORE_RST    1
1554 #define V_ESPI_RX_CORE_RST(x) ((x) << S_ESPI_RX_CORE_RST)
1555 #define F_ESPI_RX_CORE_RST    V_ESPI_RX_CORE_RST(1U)
1556 
1557 #define S_RX_CLK_STATUS	   2
1558 #define V_RX_CLK_STATUS(x) ((x) << S_RX_CLK_STATUS)
1559 #define F_RX_CLK_STATUS	   V_RX_CLK_STATUS(1U)
1560 
1561 #define A_ESPI_MISC_CONTROL 0x8f0
1562 
1563 #define S_OUT_OF_SYNC_COUNT    0
1564 #define M_OUT_OF_SYNC_COUNT    0xf
1565 #define V_OUT_OF_SYNC_COUNT(x) ((x) << S_OUT_OF_SYNC_COUNT)
1566 #define G_OUT_OF_SYNC_COUNT(x) (((x) >> S_OUT_OF_SYNC_COUNT) & M_OUT_OF_SYNC_COUNT)
1567 
1568 #define S_DIP2_COUNT_MODE_ENABLE    4
1569 #define V_DIP2_COUNT_MODE_ENABLE(x) ((x) << S_DIP2_COUNT_MODE_ENABLE)
1570 #define F_DIP2_COUNT_MODE_ENABLE    V_DIP2_COUNT_MODE_ENABLE(1U)
1571 
1572 #define S_DIP2_PARITY_ERR_THRES    5
1573 #define M_DIP2_PARITY_ERR_THRES    0xf
1574 #define V_DIP2_PARITY_ERR_THRES(x) ((x) << S_DIP2_PARITY_ERR_THRES)
1575 #define G_DIP2_PARITY_ERR_THRES(x) (((x) >> S_DIP2_PARITY_ERR_THRES) & M_DIP2_PARITY_ERR_THRES)
1576 
1577 #define S_DIP4_THRES    9
1578 #define M_DIP4_THRES    0xfff
1579 #define V_DIP4_THRES(x) ((x) << S_DIP4_THRES)
1580 #define G_DIP4_THRES(x) (((x) >> S_DIP4_THRES) & M_DIP4_THRES)
1581 
1582 #define S_DIP4_THRES_ENABLE    21
1583 #define V_DIP4_THRES_ENABLE(x) ((x) << S_DIP4_THRES_ENABLE)
1584 #define F_DIP4_THRES_ENABLE    V_DIP4_THRES_ENABLE(1U)
1585 
1586 #define S_FORCE_DISABLE_STATUS    22
1587 #define V_FORCE_DISABLE_STATUS(x) ((x) << S_FORCE_DISABLE_STATUS)
1588 #define F_FORCE_DISABLE_STATUS    V_FORCE_DISABLE_STATUS(1U)
1589 
1590 #define S_DYNAMIC_DESKEW    23
1591 #define V_DYNAMIC_DESKEW(x) ((x) << S_DYNAMIC_DESKEW)
1592 #define F_DYNAMIC_DESKEW    V_DYNAMIC_DESKEW(1U)
1593 
1594 #define S_MONITORED_PORT_NUM    25
1595 #define M_MONITORED_PORT_NUM    0x3
1596 #define V_MONITORED_PORT_NUM(x) ((x) << S_MONITORED_PORT_NUM)
1597 #define G_MONITORED_PORT_NUM(x) (((x) >> S_MONITORED_PORT_NUM) & M_MONITORED_PORT_NUM)
1598 
1599 #define S_MONITORED_DIRECTION    27
1600 #define V_MONITORED_DIRECTION(x) ((x) << S_MONITORED_DIRECTION)
1601 #define F_MONITORED_DIRECTION    V_MONITORED_DIRECTION(1U)
1602 
1603 #define S_MONITORED_INTERFACE    28
1604 #define V_MONITORED_INTERFACE(x) ((x) << S_MONITORED_INTERFACE)
1605 #define F_MONITORED_INTERFACE    V_MONITORED_INTERFACE(1U)
1606 
1607 #define A_ESPI_DIP2_ERR_COUNT 0x8f4
1608 
1609 #define S_DIP2_ERR_CNT    0
1610 #define M_DIP2_ERR_CNT    0xf
1611 #define V_DIP2_ERR_CNT(x) ((x) << S_DIP2_ERR_CNT)
1612 #define G_DIP2_ERR_CNT(x) (((x) >> S_DIP2_ERR_CNT) & M_DIP2_ERR_CNT)
1613 
1614 #define A_ESPI_CMD_ADDR 0x8f8
1615 
1616 #define S_WRITE_DATA    0
1617 #define M_WRITE_DATA    0xff
1618 #define V_WRITE_DATA(x) ((x) << S_WRITE_DATA)
1619 #define G_WRITE_DATA(x) (((x) >> S_WRITE_DATA) & M_WRITE_DATA)
1620 
1621 #define S_REGISTER_OFFSET    8
1622 #define M_REGISTER_OFFSET    0xf
1623 #define V_REGISTER_OFFSET(x) ((x) << S_REGISTER_OFFSET)
1624 #define G_REGISTER_OFFSET(x) (((x) >> S_REGISTER_OFFSET) & M_REGISTER_OFFSET)
1625 
1626 #define S_CHANNEL_ADDR    12
1627 #define M_CHANNEL_ADDR    0xf
1628 #define V_CHANNEL_ADDR(x) ((x) << S_CHANNEL_ADDR)
1629 #define G_CHANNEL_ADDR(x) (((x) >> S_CHANNEL_ADDR) & M_CHANNEL_ADDR)
1630 
1631 #define S_MODULE_ADDR    16
1632 #define M_MODULE_ADDR    0x3
1633 #define V_MODULE_ADDR(x) ((x) << S_MODULE_ADDR)
1634 #define G_MODULE_ADDR(x) (((x) >> S_MODULE_ADDR) & M_MODULE_ADDR)
1635 
1636 #define S_BUNDLE_ADDR    20
1637 #define M_BUNDLE_ADDR    0x3
1638 #define V_BUNDLE_ADDR(x) ((x) << S_BUNDLE_ADDR)
1639 #define G_BUNDLE_ADDR(x) (((x) >> S_BUNDLE_ADDR) & M_BUNDLE_ADDR)
1640 
1641 #define S_SPI4_COMMAND    24
1642 #define M_SPI4_COMMAND    0xff
1643 #define V_SPI4_COMMAND(x) ((x) << S_SPI4_COMMAND)
1644 #define G_SPI4_COMMAND(x) (((x) >> S_SPI4_COMMAND) & M_SPI4_COMMAND)
1645 
1646 #define A_ESPI_GOSTAT 0x8fc
1647 
1648 #define S_READ_DATA    0
1649 #define M_READ_DATA    0xff
1650 #define V_READ_DATA(x) ((x) << S_READ_DATA)
1651 #define G_READ_DATA(x) (((x) >> S_READ_DATA) & M_READ_DATA)
1652 
1653 #define S_ESPI_CMD_BUSY    8
1654 #define V_ESPI_CMD_BUSY(x) ((x) << S_ESPI_CMD_BUSY)
1655 #define F_ESPI_CMD_BUSY    V_ESPI_CMD_BUSY(1U)
1656 
1657 #define S_ERROR_ACK    9
1658 #define V_ERROR_ACK(x) ((x) << S_ERROR_ACK)
1659 #define F_ERROR_ACK    V_ERROR_ACK(1U)
1660 
1661 #define S_UNMAPPED_ERR    10
1662 #define V_UNMAPPED_ERR(x) ((x) << S_UNMAPPED_ERR)
1663 #define F_UNMAPPED_ERR    V_UNMAPPED_ERR(1U)
1664 
1665 #define S_TRANSACTION_TIMER    16
1666 #define M_TRANSACTION_TIMER    0xff
1667 #define V_TRANSACTION_TIMER(x) ((x) << S_TRANSACTION_TIMER)
1668 #define G_TRANSACTION_TIMER(x) (((x) >> S_TRANSACTION_TIMER) & M_TRANSACTION_TIMER)
1669 
1670 
1671 /* ULP registers */
1672 #define A_ULP_ULIMIT 0x980
1673 #define A_ULP_TAGMASK 0x984
1674 #define A_ULP_HREG_INDEX 0x988
1675 #define A_ULP_HREG_DATA 0x98c
1676 #define A_ULP_INT_ENABLE 0x990
1677 #define A_ULP_INT_CAUSE 0x994
1678 
1679 #define S_HREG_PAR_ERR    0
1680 #define V_HREG_PAR_ERR(x) ((x) << S_HREG_PAR_ERR)
1681 #define F_HREG_PAR_ERR    V_HREG_PAR_ERR(1U)
1682 
1683 #define S_EGRS_DATA_PAR_ERR    1
1684 #define V_EGRS_DATA_PAR_ERR(x) ((x) << S_EGRS_DATA_PAR_ERR)
1685 #define F_EGRS_DATA_PAR_ERR    V_EGRS_DATA_PAR_ERR(1U)
1686 
1687 #define S_INGRS_DATA_PAR_ERR    2
1688 #define V_INGRS_DATA_PAR_ERR(x) ((x) << S_INGRS_DATA_PAR_ERR)
1689 #define F_INGRS_DATA_PAR_ERR    V_INGRS_DATA_PAR_ERR(1U)
1690 
1691 #define S_PM_INTR    3
1692 #define V_PM_INTR(x) ((x) << S_PM_INTR)
1693 #define F_PM_INTR    V_PM_INTR(1U)
1694 
1695 #define S_PM_E2C_SYNC_ERR    4
1696 #define V_PM_E2C_SYNC_ERR(x) ((x) << S_PM_E2C_SYNC_ERR)
1697 #define F_PM_E2C_SYNC_ERR    V_PM_E2C_SYNC_ERR(1U)
1698 
1699 #define S_PM_C2E_SYNC_ERR    5
1700 #define V_PM_C2E_SYNC_ERR(x) ((x) << S_PM_C2E_SYNC_ERR)
1701 #define F_PM_C2E_SYNC_ERR    V_PM_C2E_SYNC_ERR(1U)
1702 
1703 #define S_PM_E2C_EMPTY_ERR    6
1704 #define V_PM_E2C_EMPTY_ERR(x) ((x) << S_PM_E2C_EMPTY_ERR)
1705 #define F_PM_E2C_EMPTY_ERR    V_PM_E2C_EMPTY_ERR(1U)
1706 
1707 #define S_PM_C2E_EMPTY_ERR    7
1708 #define V_PM_C2E_EMPTY_ERR(x) ((x) << S_PM_C2E_EMPTY_ERR)
1709 #define F_PM_C2E_EMPTY_ERR    V_PM_C2E_EMPTY_ERR(1U)
1710 
1711 #define S_PM_PAR_ERR    8
1712 #define M_PM_PAR_ERR    0xffff
1713 #define V_PM_PAR_ERR(x) ((x) << S_PM_PAR_ERR)
1714 #define G_PM_PAR_ERR(x) (((x) >> S_PM_PAR_ERR) & M_PM_PAR_ERR)
1715 
1716 #define S_PM_E2C_WRT_FULL    24
1717 #define V_PM_E2C_WRT_FULL(x) ((x) << S_PM_E2C_WRT_FULL)
1718 #define F_PM_E2C_WRT_FULL    V_PM_E2C_WRT_FULL(1U)
1719 
1720 #define S_PM_C2E_WRT_FULL    25
1721 #define V_PM_C2E_WRT_FULL(x) ((x) << S_PM_C2E_WRT_FULL)
1722 #define F_PM_C2E_WRT_FULL    V_PM_C2E_WRT_FULL(1U)
1723 
1724 #define A_ULP_PIO_CTRL 0x998
1725 
1726 /* PL registers */
1727 #define A_PL_ENABLE 0xa00
1728 
1729 #define S_PL_INTR_SGE_ERR    0
1730 #define V_PL_INTR_SGE_ERR(x) ((x) << S_PL_INTR_SGE_ERR)
1731 #define F_PL_INTR_SGE_ERR    V_PL_INTR_SGE_ERR(1U)
1732 
1733 #define S_PL_INTR_SGE_DATA    1
1734 #define V_PL_INTR_SGE_DATA(x) ((x) << S_PL_INTR_SGE_DATA)
1735 #define F_PL_INTR_SGE_DATA    V_PL_INTR_SGE_DATA(1U)
1736 
1737 #define S_PL_INTR_MC3    2
1738 #define V_PL_INTR_MC3(x) ((x) << S_PL_INTR_MC3)
1739 #define F_PL_INTR_MC3    V_PL_INTR_MC3(1U)
1740 
1741 #define S_PL_INTR_MC4    3
1742 #define V_PL_INTR_MC4(x) ((x) << S_PL_INTR_MC4)
1743 #define F_PL_INTR_MC4    V_PL_INTR_MC4(1U)
1744 
1745 #define S_PL_INTR_MC5    4
1746 #define V_PL_INTR_MC5(x) ((x) << S_PL_INTR_MC5)
1747 #define F_PL_INTR_MC5    V_PL_INTR_MC5(1U)
1748 
1749 #define S_PL_INTR_RAT    5
1750 #define V_PL_INTR_RAT(x) ((x) << S_PL_INTR_RAT)
1751 #define F_PL_INTR_RAT    V_PL_INTR_RAT(1U)
1752 
1753 #define S_PL_INTR_TP    6
1754 #define V_PL_INTR_TP(x) ((x) << S_PL_INTR_TP)
1755 #define F_PL_INTR_TP    V_PL_INTR_TP(1U)
1756 
1757 #define S_PL_INTR_ULP    7
1758 #define V_PL_INTR_ULP(x) ((x) << S_PL_INTR_ULP)
1759 #define F_PL_INTR_ULP    V_PL_INTR_ULP(1U)
1760 
1761 #define S_PL_INTR_ESPI    8
1762 #define V_PL_INTR_ESPI(x) ((x) << S_PL_INTR_ESPI)
1763 #define F_PL_INTR_ESPI    V_PL_INTR_ESPI(1U)
1764 
1765 #define S_PL_INTR_CSPI    9
1766 #define V_PL_INTR_CSPI(x) ((x) << S_PL_INTR_CSPI)
1767 #define F_PL_INTR_CSPI    V_PL_INTR_CSPI(1U)
1768 
1769 #define S_PL_INTR_PCIX    10
1770 #define V_PL_INTR_PCIX(x) ((x) << S_PL_INTR_PCIX)
1771 #define F_PL_INTR_PCIX    V_PL_INTR_PCIX(1U)
1772 
1773 #define S_PL_INTR_EXT    11
1774 #define V_PL_INTR_EXT(x) ((x) << S_PL_INTR_EXT)
1775 #define F_PL_INTR_EXT    V_PL_INTR_EXT(1U)
1776 
1777 #define A_PL_CAUSE 0xa04
1778 
1779 /* MC5 registers */
1780 #define A_MC5_CONFIG 0xc04
1781 
1782 #define S_MODE    0
1783 #define V_MODE(x) ((x) << S_MODE)
1784 #define F_MODE    V_MODE(1U)
1785 
1786 #define S_TCAM_RESET    1
1787 #define V_TCAM_RESET(x) ((x) << S_TCAM_RESET)
1788 #define F_TCAM_RESET    V_TCAM_RESET(1U)
1789 
1790 #define S_TCAM_READY    2
1791 #define V_TCAM_READY(x) ((x) << S_TCAM_READY)
1792 #define F_TCAM_READY    V_TCAM_READY(1U)
1793 
1794 #define S_DBGI_ENABLE    4
1795 #define V_DBGI_ENABLE(x) ((x) << S_DBGI_ENABLE)
1796 #define F_DBGI_ENABLE    V_DBGI_ENABLE(1U)
1797 
1798 #define S_M_BUS_ENABLE    5
1799 #define V_M_BUS_ENABLE(x) ((x) << S_M_BUS_ENABLE)
1800 #define F_M_BUS_ENABLE    V_M_BUS_ENABLE(1U)
1801 
1802 #define S_PARITY_ENABLE    6
1803 #define V_PARITY_ENABLE(x) ((x) << S_PARITY_ENABLE)
1804 #define F_PARITY_ENABLE    V_PARITY_ENABLE(1U)
1805 
1806 #define S_SYN_ISSUE_MODE    7
1807 #define M_SYN_ISSUE_MODE    0x3
1808 #define V_SYN_ISSUE_MODE(x) ((x) << S_SYN_ISSUE_MODE)
1809 #define G_SYN_ISSUE_MODE(x) (((x) >> S_SYN_ISSUE_MODE) & M_SYN_ISSUE_MODE)
1810 
1811 #define S_BUILD    16
1812 #define V_BUILD(x) ((x) << S_BUILD)
1813 #define F_BUILD    V_BUILD(1U)
1814 
1815 #define S_COMPRESSION_ENABLE    17
1816 #define V_COMPRESSION_ENABLE(x) ((x) << S_COMPRESSION_ENABLE)
1817 #define F_COMPRESSION_ENABLE    V_COMPRESSION_ENABLE(1U)
1818 
1819 #define S_NUM_LIP    18
1820 #define M_NUM_LIP    0x3f
1821 #define V_NUM_LIP(x) ((x) << S_NUM_LIP)
1822 #define G_NUM_LIP(x) (((x) >> S_NUM_LIP) & M_NUM_LIP)
1823 
1824 #define S_TCAM_PART_CNT    24
1825 #define M_TCAM_PART_CNT    0x3
1826 #define V_TCAM_PART_CNT(x) ((x) << S_TCAM_PART_CNT)
1827 #define G_TCAM_PART_CNT(x) (((x) >> S_TCAM_PART_CNT) & M_TCAM_PART_CNT)
1828 
1829 #define S_TCAM_PART_TYPE    26
1830 #define M_TCAM_PART_TYPE    0x3
1831 #define V_TCAM_PART_TYPE(x) ((x) << S_TCAM_PART_TYPE)
1832 #define G_TCAM_PART_TYPE(x) (((x) >> S_TCAM_PART_TYPE) & M_TCAM_PART_TYPE)
1833 
1834 #define S_TCAM_PART_SIZE    28
1835 #define M_TCAM_PART_SIZE    0x3
1836 #define V_TCAM_PART_SIZE(x) ((x) << S_TCAM_PART_SIZE)
1837 #define G_TCAM_PART_SIZE(x) (((x) >> S_TCAM_PART_SIZE) & M_TCAM_PART_SIZE)
1838 
1839 #define S_TCAM_PART_TYPE_HI    30
1840 #define V_TCAM_PART_TYPE_HI(x) ((x) << S_TCAM_PART_TYPE_HI)
1841 #define F_TCAM_PART_TYPE_HI    V_TCAM_PART_TYPE_HI(1U)
1842 
1843 #define A_MC5_SIZE 0xc08
1844 
1845 #define S_SIZE    0
1846 #define M_SIZE    0x3fffff
1847 #define V_SIZE(x) ((x) << S_SIZE)
1848 #define G_SIZE(x) (((x) >> S_SIZE) & M_SIZE)
1849 
1850 #define A_MC5_ROUTING_TABLE_INDEX 0xc0c
1851 
1852 #define S_START_OF_ROUTING_TABLE    0
1853 #define M_START_OF_ROUTING_TABLE    0x3fffff
1854 #define V_START_OF_ROUTING_TABLE(x) ((x) << S_START_OF_ROUTING_TABLE)
1855 #define G_START_OF_ROUTING_TABLE(x) (((x) >> S_START_OF_ROUTING_TABLE) & M_START_OF_ROUTING_TABLE)
1856 
1857 #define A_MC5_SERVER_INDEX 0xc14
1858 
1859 #define S_START_OF_SERVER_INDEX    0
1860 #define M_START_OF_SERVER_INDEX    0x3fffff
1861 #define V_START_OF_SERVER_INDEX(x) ((x) << S_START_OF_SERVER_INDEX)
1862 #define G_START_OF_SERVER_INDEX(x) (((x) >> S_START_OF_SERVER_INDEX) & M_START_OF_SERVER_INDEX)
1863 
1864 #define A_MC5_LIP_RAM_ADDR 0xc18
1865 
1866 #define S_LOCAL_IP_RAM_ADDR    0
1867 #define M_LOCAL_IP_RAM_ADDR    0x3f
1868 #define V_LOCAL_IP_RAM_ADDR(x) ((x) << S_LOCAL_IP_RAM_ADDR)
1869 #define G_LOCAL_IP_RAM_ADDR(x) (((x) >> S_LOCAL_IP_RAM_ADDR) & M_LOCAL_IP_RAM_ADDR)
1870 
1871 #define S_RAM_WRITE_ENABLE    8
1872 #define V_RAM_WRITE_ENABLE(x) ((x) << S_RAM_WRITE_ENABLE)
1873 #define F_RAM_WRITE_ENABLE    V_RAM_WRITE_ENABLE(1U)
1874 
1875 #define A_MC5_LIP_RAM_DATA 0xc1c
1876 #define A_MC5_RSP_LATENCY 0xc20
1877 
1878 #define S_SEARCH_RESPONSE_LATENCY    0
1879 #define M_SEARCH_RESPONSE_LATENCY    0x1f
1880 #define V_SEARCH_RESPONSE_LATENCY(x) ((x) << S_SEARCH_RESPONSE_LATENCY)
1881 #define G_SEARCH_RESPONSE_LATENCY(x) (((x) >> S_SEARCH_RESPONSE_LATENCY) & M_SEARCH_RESPONSE_LATENCY)
1882 
1883 #define S_LEARN_RESPONSE_LATENCY    8
1884 #define M_LEARN_RESPONSE_LATENCY    0x1f
1885 #define V_LEARN_RESPONSE_LATENCY(x) ((x) << S_LEARN_RESPONSE_LATENCY)
1886 #define G_LEARN_RESPONSE_LATENCY(x) (((x) >> S_LEARN_RESPONSE_LATENCY) & M_LEARN_RESPONSE_LATENCY)
1887 
1888 #define A_MC5_PARITY_LATENCY 0xc24
1889 
1890 #define S_SRCHLAT    0
1891 #define M_SRCHLAT    0x1f
1892 #define V_SRCHLAT(x) ((x) << S_SRCHLAT)
1893 #define G_SRCHLAT(x) (((x) >> S_SRCHLAT) & M_SRCHLAT)
1894 
1895 #define S_PARLAT    8
1896 #define M_PARLAT    0x1f
1897 #define V_PARLAT(x) ((x) << S_PARLAT)
1898 #define G_PARLAT(x) (((x) >> S_PARLAT) & M_PARLAT)
1899 
1900 #define A_MC5_WR_LRN_VERIFY 0xc28
1901 
1902 #define S_POVEREN    0
1903 #define V_POVEREN(x) ((x) << S_POVEREN)
1904 #define F_POVEREN    V_POVEREN(1U)
1905 
1906 #define S_LRNVEREN    1
1907 #define V_LRNVEREN(x) ((x) << S_LRNVEREN)
1908 #define F_LRNVEREN    V_LRNVEREN(1U)
1909 
1910 #define S_VWVEREN    2
1911 #define V_VWVEREN(x) ((x) << S_VWVEREN)
1912 #define F_VWVEREN    V_VWVEREN(1U)
1913 
1914 #define A_MC5_PART_ID_INDEX 0xc2c
1915 
1916 #define S_IDINDEX    0
1917 #define M_IDINDEX    0xf
1918 #define V_IDINDEX(x) ((x) << S_IDINDEX)
1919 #define G_IDINDEX(x) (((x) >> S_IDINDEX) & M_IDINDEX)
1920 
1921 #define A_MC5_RESET_MAX 0xc30
1922 
1923 #define S_RSTMAX    0
1924 #define M_RSTMAX    0x1ff
1925 #define V_RSTMAX(x) ((x) << S_RSTMAX)
1926 #define G_RSTMAX(x) (((x) >> S_RSTMAX) & M_RSTMAX)
1927 
1928 #define A_MC5_INT_ENABLE 0xc40
1929 
1930 #define S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR    0
1931 #define V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR)
1932 #define F_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR    V_MC5_INT_HIT_OUT_ACTIVE_REGION_ERR(1U)
1933 
1934 #define S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR    1
1935 #define V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_ACTIVE_REGION_ERR)
1936 #define F_MC5_INT_HIT_IN_ACTIVE_REGION_ERR    V_MC5_INT_HIT_IN_ACTIVE_REGION_ERR(1U)
1937 
1938 #define S_MC5_INT_HIT_IN_RT_REGION_ERR    2
1939 #define V_MC5_INT_HIT_IN_RT_REGION_ERR(x) ((x) << S_MC5_INT_HIT_IN_RT_REGION_ERR)
1940 #define F_MC5_INT_HIT_IN_RT_REGION_ERR    V_MC5_INT_HIT_IN_RT_REGION_ERR(1U)
1941 
1942 #define S_MC5_INT_MISS_ERR    3
1943 #define V_MC5_INT_MISS_ERR(x) ((x) << S_MC5_INT_MISS_ERR)
1944 #define F_MC5_INT_MISS_ERR    V_MC5_INT_MISS_ERR(1U)
1945 
1946 #define S_MC5_INT_LIP0_ERR    4
1947 #define V_MC5_INT_LIP0_ERR(x) ((x) << S_MC5_INT_LIP0_ERR)
1948 #define F_MC5_INT_LIP0_ERR    V_MC5_INT_LIP0_ERR(1U)
1949 
1950 #define S_MC5_INT_LIP_MISS_ERR    5
1951 #define V_MC5_INT_LIP_MISS_ERR(x) ((x) << S_MC5_INT_LIP_MISS_ERR)
1952 #define F_MC5_INT_LIP_MISS_ERR    V_MC5_INT_LIP_MISS_ERR(1U)
1953 
1954 #define S_MC5_INT_PARITY_ERR    6
1955 #define V_MC5_INT_PARITY_ERR(x) ((x) << S_MC5_INT_PARITY_ERR)
1956 #define F_MC5_INT_PARITY_ERR    V_MC5_INT_PARITY_ERR(1U)
1957 
1958 #define S_MC5_INT_ACTIVE_REGION_FULL    7
1959 #define V_MC5_INT_ACTIVE_REGION_FULL(x) ((x) << S_MC5_INT_ACTIVE_REGION_FULL)
1960 #define F_MC5_INT_ACTIVE_REGION_FULL    V_MC5_INT_ACTIVE_REGION_FULL(1U)
1961 
1962 #define S_MC5_INT_NFA_SRCH_ERR    8
1963 #define V_MC5_INT_NFA_SRCH_ERR(x) ((x) << S_MC5_INT_NFA_SRCH_ERR)
1964 #define F_MC5_INT_NFA_SRCH_ERR    V_MC5_INT_NFA_SRCH_ERR(1U)
1965 
1966 #define S_MC5_INT_SYN_COOKIE    9
1967 #define V_MC5_INT_SYN_COOKIE(x) ((x) << S_MC5_INT_SYN_COOKIE)
1968 #define F_MC5_INT_SYN_COOKIE    V_MC5_INT_SYN_COOKIE(1U)
1969 
1970 #define S_MC5_INT_SYN_COOKIE_BAD    10
1971 #define V_MC5_INT_SYN_COOKIE_BAD(x) ((x) << S_MC5_INT_SYN_COOKIE_BAD)
1972 #define F_MC5_INT_SYN_COOKIE_BAD    V_MC5_INT_SYN_COOKIE_BAD(1U)
1973 
1974 #define S_MC5_INT_SYN_COOKIE_OFF    11
1975 #define V_MC5_INT_SYN_COOKIE_OFF(x) ((x) << S_MC5_INT_SYN_COOKIE_OFF)
1976 #define F_MC5_INT_SYN_COOKIE_OFF    V_MC5_INT_SYN_COOKIE_OFF(1U)
1977 
1978 #define S_MC5_INT_UNKNOWN_CMD    15
1979 #define V_MC5_INT_UNKNOWN_CMD(x) ((x) << S_MC5_INT_UNKNOWN_CMD)
1980 #define F_MC5_INT_UNKNOWN_CMD    V_MC5_INT_UNKNOWN_CMD(1U)
1981 
1982 #define S_MC5_INT_REQUESTQ_PARITY_ERR    16
1983 #define V_MC5_INT_REQUESTQ_PARITY_ERR(x) ((x) << S_MC5_INT_REQUESTQ_PARITY_ERR)
1984 #define F_MC5_INT_REQUESTQ_PARITY_ERR    V_MC5_INT_REQUESTQ_PARITY_ERR(1U)
1985 
1986 #define S_MC5_INT_DISPATCHQ_PARITY_ERR    17
1987 #define V_MC5_INT_DISPATCHQ_PARITY_ERR(x) ((x) << S_MC5_INT_DISPATCHQ_PARITY_ERR)
1988 #define F_MC5_INT_DISPATCHQ_PARITY_ERR    V_MC5_INT_DISPATCHQ_PARITY_ERR(1U)
1989 
1990 #define S_MC5_INT_DEL_ACT_EMPTY    18
1991 #define V_MC5_INT_DEL_ACT_EMPTY(x) ((x) << S_MC5_INT_DEL_ACT_EMPTY)
1992 #define F_MC5_INT_DEL_ACT_EMPTY    V_MC5_INT_DEL_ACT_EMPTY(1U)
1993 
1994 #define A_MC5_INT_CAUSE 0xc44
1995 #define A_MC5_INT_TID 0xc48
1996 #define A_MC5_INT_PTID 0xc4c
1997 #define A_MC5_DBGI_CONFIG 0xc74
1998 #define A_MC5_DBGI_REQ_CMD 0xc78
1999 
2000 #define S_CMDMODE    0
2001 #define M_CMDMODE    0x7
2002 #define V_CMDMODE(x) ((x) << S_CMDMODE)
2003 #define G_CMDMODE(x) (((x) >> S_CMDMODE) & M_CMDMODE)
2004 
2005 #define S_SADRSEL    4
2006 #define V_SADRSEL(x) ((x) << S_SADRSEL)
2007 #define F_SADRSEL    V_SADRSEL(1U)
2008 
2009 #define S_WRITE_BURST_SIZE    22
2010 #define M_WRITE_BURST_SIZE    0x3ff
2011 #define V_WRITE_BURST_SIZE(x) ((x) << S_WRITE_BURST_SIZE)
2012 #define G_WRITE_BURST_SIZE(x) (((x) >> S_WRITE_BURST_SIZE) & M_WRITE_BURST_SIZE)
2013 
2014 #define A_MC5_DBGI_REQ_ADDR0 0xc7c
2015 #define A_MC5_DBGI_REQ_ADDR1 0xc80
2016 #define A_MC5_DBGI_REQ_ADDR2 0xc84
2017 #define A_MC5_DBGI_REQ_DATA0 0xc88
2018 #define A_MC5_DBGI_REQ_DATA1 0xc8c
2019 #define A_MC5_DBGI_REQ_DATA2 0xc90
2020 #define A_MC5_DBGI_REQ_DATA3 0xc94
2021 #define A_MC5_DBGI_REQ_DATA4 0xc98
2022 #define A_MC5_DBGI_REQ_MASK0 0xc9c
2023 #define A_MC5_DBGI_REQ_MASK1 0xca0
2024 #define A_MC5_DBGI_REQ_MASK2 0xca4
2025 #define A_MC5_DBGI_REQ_MASK3 0xca8
2026 #define A_MC5_DBGI_REQ_MASK4 0xcac
2027 #define A_MC5_DBGI_RSP_STATUS 0xcb0
2028 
2029 #define S_DBGI_RSP_VALID    0
2030 #define V_DBGI_RSP_VALID(x) ((x) << S_DBGI_RSP_VALID)
2031 #define F_DBGI_RSP_VALID    V_DBGI_RSP_VALID(1U)
2032 
2033 #define S_DBGI_RSP_HIT    1
2034 #define V_DBGI_RSP_HIT(x) ((x) << S_DBGI_RSP_HIT)
2035 #define F_DBGI_RSP_HIT    V_DBGI_RSP_HIT(1U)
2036 
2037 #define S_DBGI_RSP_ERR    2
2038 #define V_DBGI_RSP_ERR(x) ((x) << S_DBGI_RSP_ERR)
2039 #define F_DBGI_RSP_ERR    V_DBGI_RSP_ERR(1U)
2040 
2041 #define S_DBGI_RSP_ERR_REASON    8
2042 #define M_DBGI_RSP_ERR_REASON    0x7
2043 #define V_DBGI_RSP_ERR_REASON(x) ((x) << S_DBGI_RSP_ERR_REASON)
2044 #define G_DBGI_RSP_ERR_REASON(x) (((x) >> S_DBGI_RSP_ERR_REASON) & M_DBGI_RSP_ERR_REASON)
2045 
2046 #define A_MC5_DBGI_RSP_DATA0 0xcb4
2047 #define A_MC5_DBGI_RSP_DATA1 0xcb8
2048 #define A_MC5_DBGI_RSP_DATA2 0xcbc
2049 #define A_MC5_DBGI_RSP_DATA3 0xcc0
2050 #define A_MC5_DBGI_RSP_DATA4 0xcc4
2051 #define A_MC5_DBGI_RSP_LAST_CMD 0xcc8
2052 #define A_MC5_POPEN_DATA_WR_CMD 0xccc
2053 #define A_MC5_POPEN_MASK_WR_CMD 0xcd0
2054 #define A_MC5_AOPEN_SRCH_CMD 0xcd4
2055 #define A_MC5_AOPEN_LRN_CMD 0xcd8
2056 #define A_MC5_SYN_SRCH_CMD 0xcdc
2057 #define A_MC5_SYN_LRN_CMD 0xce0
2058 #define A_MC5_ACK_SRCH_CMD 0xce4
2059 #define A_MC5_ACK_LRN_CMD 0xce8
2060 #define A_MC5_ILOOKUP_CMD 0xcec
2061 #define A_MC5_ELOOKUP_CMD 0xcf0
2062 #define A_MC5_DATA_WRITE_CMD 0xcf4
2063 #define A_MC5_DATA_READ_CMD 0xcf8
2064 #define A_MC5_MASK_WRITE_CMD 0xcfc
2065 
2066 /* PCICFG registers */
2067 #define A_PCICFG_PM_CSR 0x44
2068 #define A_PCICFG_VPD_ADDR 0x4a
2069 
2070 #define S_VPD_ADDR    0
2071 #define M_VPD_ADDR    0x7fff
2072 #define V_VPD_ADDR(x) ((x) << S_VPD_ADDR)
2073 #define G_VPD_ADDR(x) (((x) >> S_VPD_ADDR) & M_VPD_ADDR)
2074 
2075 #define S_VPD_OP_FLAG    15
2076 #define V_VPD_OP_FLAG(x) ((x) << S_VPD_OP_FLAG)
2077 #define F_VPD_OP_FLAG    V_VPD_OP_FLAG(1U)
2078 
2079 #define A_PCICFG_VPD_DATA 0x4c
2080 #define A_PCICFG_PCIX_CMD 0x60
2081 #define A_PCICFG_INTR_ENABLE 0xf4
2082 
2083 #define S_MASTER_PARITY_ERR    0
2084 #define V_MASTER_PARITY_ERR(x) ((x) << S_MASTER_PARITY_ERR)
2085 #define F_MASTER_PARITY_ERR    V_MASTER_PARITY_ERR(1U)
2086 
2087 #define S_SIG_TARGET_ABORT    1
2088 #define V_SIG_TARGET_ABORT(x) ((x) << S_SIG_TARGET_ABORT)
2089 #define F_SIG_TARGET_ABORT    V_SIG_TARGET_ABORT(1U)
2090 
2091 #define S_RCV_TARGET_ABORT    2
2092 #define V_RCV_TARGET_ABORT(x) ((x) << S_RCV_TARGET_ABORT)
2093 #define F_RCV_TARGET_ABORT    V_RCV_TARGET_ABORT(1U)
2094 
2095 #define S_RCV_MASTER_ABORT    3
2096 #define V_RCV_MASTER_ABORT(x) ((x) << S_RCV_MASTER_ABORT)
2097 #define F_RCV_MASTER_ABORT    V_RCV_MASTER_ABORT(1U)
2098 
2099 #define S_SIG_SYS_ERR    4
2100 #define V_SIG_SYS_ERR(x) ((x) << S_SIG_SYS_ERR)
2101 #define F_SIG_SYS_ERR    V_SIG_SYS_ERR(1U)
2102 
2103 #define S_DET_PARITY_ERR    5
2104 #define V_DET_PARITY_ERR(x) ((x) << S_DET_PARITY_ERR)
2105 #define F_DET_PARITY_ERR    V_DET_PARITY_ERR(1U)
2106 
2107 #define S_PIO_PARITY_ERR    6
2108 #define V_PIO_PARITY_ERR(x) ((x) << S_PIO_PARITY_ERR)
2109 #define F_PIO_PARITY_ERR    V_PIO_PARITY_ERR(1U)
2110 
2111 #define S_WF_PARITY_ERR    7
2112 #define V_WF_PARITY_ERR(x) ((x) << S_WF_PARITY_ERR)
2113 #define F_WF_PARITY_ERR    V_WF_PARITY_ERR(1U)
2114 
2115 #define S_RF_PARITY_ERR    8
2116 #define M_RF_PARITY_ERR    0x3
2117 #define V_RF_PARITY_ERR(x) ((x) << S_RF_PARITY_ERR)
2118 #define G_RF_PARITY_ERR(x) (((x) >> S_RF_PARITY_ERR) & M_RF_PARITY_ERR)
2119 
2120 #define S_CF_PARITY_ERR    10
2121 #define M_CF_PARITY_ERR    0x3
2122 #define V_CF_PARITY_ERR(x) ((x) << S_CF_PARITY_ERR)
2123 #define G_CF_PARITY_ERR(x) (((x) >> S_CF_PARITY_ERR) & M_CF_PARITY_ERR)
2124 
2125 #define A_PCICFG_INTR_CAUSE 0xf8
2126 #define A_PCICFG_MODE 0xfc
2127 
2128 #define S_PCI_MODE_64BIT    0
2129 #define V_PCI_MODE_64BIT(x) ((x) << S_PCI_MODE_64BIT)
2130 #define F_PCI_MODE_64BIT    V_PCI_MODE_64BIT(1U)
2131 
2132 #define S_PCI_MODE_66MHZ    1
2133 #define V_PCI_MODE_66MHZ(x) ((x) << S_PCI_MODE_66MHZ)
2134 #define F_PCI_MODE_66MHZ    V_PCI_MODE_66MHZ(1U)
2135 
2136 #define S_PCI_MODE_PCIX_INITPAT    2
2137 #define M_PCI_MODE_PCIX_INITPAT    0x7
2138 #define V_PCI_MODE_PCIX_INITPAT(x) ((x) << S_PCI_MODE_PCIX_INITPAT)
2139 #define G_PCI_MODE_PCIX_INITPAT(x) (((x) >> S_PCI_MODE_PCIX_INITPAT) & M_PCI_MODE_PCIX_INITPAT)
2140 
2141 #define S_PCI_MODE_PCIX    5
2142 #define V_PCI_MODE_PCIX(x) ((x) << S_PCI_MODE_PCIX)
2143 #define F_PCI_MODE_PCIX    V_PCI_MODE_PCIX(1U)
2144 
2145 #define S_PCI_MODE_CLK    6
2146 #define M_PCI_MODE_CLK    0x3
2147 #define V_PCI_MODE_CLK(x) ((x) << S_PCI_MODE_CLK)
2148 #define G_PCI_MODE_CLK(x) (((x) >> S_PCI_MODE_CLK) & M_PCI_MODE_CLK)
2149 
2150