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Searched refs:GEN7_UCGCTL4 (Results 1 – 2 of 2) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Di915_reg.h4575 #define GEN7_UCGCTL4 0x940c macro
H A Dintel_pm.c4402 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE); in valleyview_init_clock_gating()