1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_NXGE_NXGE_SR_HW_H
27 #define	_SYS_NXGE_NXGE_SR_HW_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 #define	ESR_NEPTUNE_DEV_ADDR	0x1E
34 #define	ESR_NEPTUNE_BASE	0
35 #define	ESR_PORT_ADDR_BASE	0
36 #define	PCISR_DEV_ADDR		0x1E
37 #define	PCISR_BASE		0
38 #define	PCISR_PORT_ADDR_BASE	2
39 
40 #define	PB	0
41 
42 #define	SR_RX_TX_COMMON_CONTROL	PB + 0x000
43 #define	SR_RX_TX_RESET_CONTROL	PB + 0x004
44 #define	SR_RX_POWER_CONTROL	PB + 0x008
45 #define	SR_TX_POWER_CONTROL	PB + 0x00C
46 #define	SR_MISC_POWER_CONTROL	PB + 0x010
47 #define	SR_RX_TX_CONTROL_A	PB + 0x100
48 #define	SR_RX_TX_TUNING_A	PB + 0x104
49 #define	SR_RX_SYNCCHAR_A	PB + 0x108
50 #define	SR_RX_TX_TEST_A		PB + 0x10C
51 #define	SR_GLUE_CONTROL0_A	PB + 0x110
52 #define	SR_GLUE_CONTROL1_A	PB + 0x114
53 #define	SR_RX_TX_CONTROL_B	PB + 0x120
54 #define	SR_RX_TX_TUNING_B	PB + 0x124
55 #define	SR_RX_SYNCCHAR_B	PB + 0x128
56 #define	SR_RX_TX_TEST_B		PB + 0x12C
57 #define	SR_GLUE_CONTROL0_B	PB + 0x130
58 #define	SR_GLUE_CONTROL1_B	PB + 0x134
59 #define	SR_RX_TX_CONTROL_C	PB + 0x140
60 #define	SR_RX_TX_TUNING_C	PB + 0x144
61 #define	SR_RX_SYNCCHAR_C	PB + 0x148
62 #define	SR_RX_TX_TEST_C		PB + 0x14C
63 #define	SR_GLUE_CONTROL0_C	PB + 0x150
64 #define	SR_GLUE_CONTROL1_C	PB + 0x154
65 #define	SR_RX_TX_CONTROL_D	PB + 0x160
66 #define	SR_RX_TX_TUNING_D	PB + 0x164
67 #define	SR_RX_SYNCCHAR_D	PB + 0x168
68 #define	SR_RX_TX_TEST_D		PB + 0x16C
69 #define	SR_GLUE_CONTROL0_D	PB + 0x170
70 #define	SR_GLUE_CONTROL1_D	PB + 0x174
71 #define	SR_RX_TX_TUNING_1_A	PB + 0x184
72 #define	SR_RX_TX_TUNING_1_B	PB + 0x1A4
73 #define	SR_RX_TX_TUNING_1_C	PB + 0x1C4
74 #define	SR_RX_TX_TUNING_1_D	PB + 0x1E4
75 #define	SR_RX_TX_TUNING_2_A	PB + 0x204
76 #define	SR_RX_TX_TUNING_2_B	PB + 0x224
77 #define	SR_RX_TX_TUNING_2_C	PB + 0x244
78 #define	SR_RX_TX_TUNING_2_D	PB + 0x264
79 #define	SR_RX_TX_TUNING_3_A	PB + 0x284
80 #define	SR_RX_TX_TUNING_3_B	PB + 0x2A4
81 #define	SR_RX_TX_TUNING_3_C	PB + 0x2C4
82 #define	SR_RX_TX_TUNING_3_D	PB + 0x2E4
83 
84 /*
85  * Shift right by 1 because the PRM requires that all the serdes register
86  * address be divided by 2
87  */
88 #define	ESR_NEP_RX_TX_COMMON_CONTROL_L_ADDR()	(ESR_NEPTUNE_BASE +\
89 						(SR_RX_TX_COMMON_CONTROL >> 1))
90 #define	ESR_NEP_RX_TX_COMMON_CONTROL_H_ADDR()	(ESR_NEPTUNE_BASE +\
91 						(SR_RX_TX_COMMON_CONTROL >> 1)\
92 						+ 1)
93 #define	ESR_NEP_RX_TX_RESET_CONTROL_L_ADDR()	(ESR_NEPTUNE_BASE +\
94 						(SR_RX_TX_RESET_CONTROL >> 1))
95 #define	ESR_NEP_RX_TX_RESET_CONTROL_H_ADDR()	(ESR_NEPTUNE_BASE +\
96 						(SR_RX_TX_RESET_CONTROL >> 1)\
97 						+ 1)
98 #define	ESR_NEP_RX_POWER_CONTROL_L_ADDR()	(ESR_NEPTUNE_BASE +\
99 						(SR_RX_POWER_CONTROL >> 1))
100 #define	ESR_NEP_RX_POWER_CONTROL_H_ADDR()	(ESR_NEPTUNE_BASE +\
101 						(SR_RX_POWER_CONTROL >> 1) + 1)
102 #define	ESR_NEP_TX_POWER_CONTROL_L_ADDR()	(ESR_NEPTUNE_BASE +\
103 						(SR_TX_POWER_CONTROL >> 1))
104 #define	ESR_NEP_TX_POWER_CONTROL_H_ADDR()	(ESR_NEPTUNE_BASE +\
105 						(SR_TX_POWER_CONTROL >> 1) + 1)
106 #define	ESR_NEP_MISC_POWER_CONTROL_L_ADDR()	(ESR_NEPTUNE_BASE +\
107 						(SR_MISC_POWER_CONTROL >> 1))
108 #define	ESR_NEP_MISC_POWER_CONTROL_H_ADDR()	(ESR_NEPTUNE_BASE +\
109 						(SR_MISC_POWER_CONTROL >> 1)\
110 						+ 1)
111 #define	ESR_NEP_RX_TX_CONTROL_L_ADDR(chan)	((ESR_NEPTUNE_BASE +\
112 						SR_RX_TX_CONTROL_A +\
113 						(chan * 0x20)) >> 1)
114 #define	ESR_NEP_RX_TX_CONTROL_H_ADDR(chan)	((ESR_NEPTUNE_BASE +\
115 						SR_RX_TX_CONTROL_A +\
116 						(chan * 0x20)) >> 1) + 1
117 #define	ESR_NEP_RX_TX_TUNING_L_ADDR(chan)	((ESR_NEPTUNE_BASE +\
118 						SR_RX_TX_TUNING_A +\
119 						(chan * 0x20)) >> 1)
120 #define	ESR_NEP_RX_TX_TUNING_H_ADDR(chan)	((ESR_NEPTUNE_BASE +\
121 						SR_RX_TX_TUNING_A +\
122 						(chan * 0x20)) >> 1) + 1
123 #define	ESR_NEP_RX_TX_SYNCCHAR_L_ADDR(chan)	((ESR_NEPTUNE_BASE +\
124 						SR_RX_SYNCCHAR_A +\
125 						(chan * 0x20)) >> 1)
126 #define	ESR_NEP_RX_TX_SYNCCHAR_H_ADDR(chan)	((ESR_NEPTUNE_BASE +\
127 						SR_RX_SYNCCHAR_A +\
128 						(chan * 0x20)) >> 1) + 1
129 #define	ESR_NEP_RX_TX_TEST_L_ADDR(chan)		((ESR_NEPTUNE_BASE +\
130 						SR_RX_TX_TEST_A +\
131 						(chan * 0x20)) >> 1)
132 #define	ESR_NEP_RX_TX_TEST_H_ADDR(chan)		((ESR_NEPTUNE_BASE +\
133 						SR_RX_TX_TEST_A +\
134 						(chan * 0x20)) >> 1) + 1
135 #define	ESR_NEP_GLUE_CONTROL0_L_ADDR(chan)	((ESR_NEPTUNE_BASE +\
136 						SR_GLUE_CONTROL0_A +\
137 						(chan * 0x20)) >> 1)
138 #define	ESR_NEP_GLUE_CONTROL0_H_ADDR(chan)	((ESR_NEPTUNE_BASE +\
139 						SR_GLUE_CONTROL0_A +\
140 						(chan * 0x20)) >> 1) + 1
141 #define	ESR_NEP_GLUE_CONTROL1_L_ADDR(chan)	((ESR_NEPTUNE_BASE +\
142 						SR_GLUE_CONTROL1_A +\
143 						(chan * 0x20)) >> 1)
144 #define	ESR_NEP_GLUE_CONTROL1_H_ADDR(chan)	((ESR_NEPTUNE_BASE +\
145 						SR_GLUE_CONTROL1_A +\
146 						(chan * 0x20)) >> 1) + 1
147 #define	ESR_NEP_RX_TX_TUNING_1_L_ADDR(chan)	((ESR_NEPTUNE_BASE +\
148 						SR_RX_TX_TUNING_1_A +\
149 						(chan * 0x20)) >> 1)
150 #define	ESR_NEP_RX_TX_TUNING_1_H_ADDR(chan)	((ESR_NEPTUNE_BASE +\
151 						SR_RX_TX_TUNING_1_A +\
152 						(chan * 0x20)) >> 1) + 1
153 #define	ESR_NEP_RX_TX_TUNING_2_L_ADDR(chan)	((ESR_NEPTUNE_BASE +\
154 						SR_RX_TX_TUNING_2_A +\
155 						(chan * 0x20)) >> 1)
156 #define	ESR_NEP_RX_TX_TUNING_2_H_ADDR(chan)	((ESR_NEPTUNE_BASE +\
157 						SR_RX_TX_TUNING_2_A +\
158 						(chan * 0x20)) >> 1) + 1
159 #define	ESR_NEP_RX_TX_TUNING_3_L_ADDR(chan)	((ESR_NEPTUNE_BASE +\
160 						SR_RX_TX_TUNING_3_A +\
161 						(chan * 0x20)) >> 1)
162 #define	ESR_NEP_RX_TX_TUNING_3_H_ADDR(chan)	((ESR_NEPTUNE_BASE +\
163 						SR_RX_TX_TUNING_3_A +\
164 						(chan * 0x20)) >> 1) + 1
165 
166 typedef	union _sr_rx_tx_common_ctrl_l {
167 	uint16_t value;
168 	struct {
169 #if defined(_BIT_FIELDS_HTOL)
170 		uint16_t res3		: 3;
171 		uint16_t refclkr_freq	: 5;
172 		uint16_t res4		: 8;
173 #elif defined(_BIT_FIELDS_LTOH)
174 		uint16_t res4		: 8;
175 		uint16_t refclkr_freq	: 5;
176 		uint16_t res3		: 3;
177 #else
178 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
179 #endif
180 	} bits;
181 } sr_rx_tx_common_ctrl_l;
182 
183 typedef	union _sr_rx_tx_common_ctrl_h {
184 	uint16_t value;
185 	struct {
186 #if defined(_BIT_FIELDS_HTOL)
187 		uint16_t res1		: 5;
188 		uint16_t tdmaster	: 3;
189 		uint16_t tp		: 2;
190 		uint16_t tz		: 2;
191 		uint16_t res2		: 2;
192 		uint16_t revlbrefsel	: 2;
193 #elif defined(_BIT_FIELDS_LTOH)
194 		uint16_t revlbrefsel	: 2;
195 		uint16_t res2		: 2;
196 		uint16_t tz		: 2;
197 		uint16_t tp		: 2;
198 		uint16_t tdmaster	: 3;
199 		uint16_t res1		: 5;
200 #else
201 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
202 #endif
203 	} bits;
204 } sr_rx_tx_common_ctrl_h;
205 
206 
207 /* RX TX Common Control Register field values */
208 
209 #define	TDMASTER_LANE_A		0
210 #define	TDMASTER_LANE_B		1
211 #define	TDMASTER_LANE_C		2
212 #define	TDMASTER_LANE_D		3
213 
214 #define	REVLBREFSEL_GBT_RBC_A_O		0
215 #define	REVLBREFSEL_GBT_RBC_B_O		1
216 #define	REVLBREFSEL_GBT_RBC_C_O		2
217 #define	REVLBREFSEL_GBT_RBC_D_O		3
218 
219 #define	REFCLKR_FREQ_SIM		0
220 #define	REFCLKR_FREQ_53_125		0x1
221 #define	REFCLKR_FREQ_62_5		0x3
222 #define	REFCLKR_FREQ_70_83		0x4
223 #define	REFCLKR_FREQ_75			0x5
224 #define	REFCLKR_FREQ_78_125		0x6
225 #define	REFCLKR_FREQ_79_6875		0x7
226 #define	REFCLKR_FREQ_83_33		0x8
227 #define	REFCLKR_FREQ_85			0x9
228 #define	REFCLKR_FREQ_100		0xA
229 #define	REFCLKR_FREQ_104_17		0xB
230 #define	REFCLKR_FREQ_106_25		0xC
231 #define	REFCLKR_FREQ_120		0xF
232 #define	REFCLKR_FREQ_125		0x10
233 #define	REFCLKR_FREQ_127_5		0x11
234 #define	REFCLKR_FREQ_141_67		0x13
235 #define	REFCLKR_FREQ_150		0x15
236 #define	REFCLKR_FREQ_156_25		0x16
237 #define	REFCLKR_FREQ_159_375		0x17
238 #define	REFCLKR_FREQ_170		0x19
239 #define	REFCLKR_FREQ_212_5		0x1E
240 
241 typedef	union _sr_rx_tx_reset_ctrl_l {
242 	uint16_t value;
243 	struct {
244 #if defined(_BIT_FIELDS_HTOL)
245 		uint16_t rxreset_0a	: 1;
246 		uint16_t rxreset_0b	: 1;
247 		uint16_t rxreset_0c	: 1;
248 		uint16_t rxreset_0d	: 1;
249 		uint16_t rxreset_1a	: 1;
250 		uint16_t rxreset_1b	: 1;
251 		uint16_t rxreset_1c	: 1;
252 		uint16_t rxreset_1d	: 1;
253 		uint16_t rxreset_2a	: 1;
254 		uint16_t rxreset_2b	: 1;
255 		uint16_t rxreset_2c	: 1;
256 		uint16_t rxreset_2d	: 1;
257 		uint16_t rxreset_3a	: 1;
258 		uint16_t rxreset_3b	: 1;
259 		uint16_t rxreset_3c	: 1;
260 		uint16_t rxreset_3d	: 1;
261 #elif defined(_BIT_FIELDS_LTOH)
262 		uint16_t rxreset_3d	: 1;
263 		uint16_t rxreset_3c	: 1;
264 		uint16_t rxreset_3b	: 1;
265 		uint16_t rxreset_3a	: 1;
266 		uint16_t rxreset_2d	: 1;
267 		uint16_t rxreset_2c	: 1;
268 		uint16_t rxreset_2b	: 1;
269 		uint16_t rxreset_2a	: 1;
270 		uint16_t rxreset_1d	: 1;
271 		uint16_t rxreset_1c	: 1;
272 		uint16_t rxreset_1b	: 1;
273 		uint16_t rxreset_1a	: 1;
274 		uint16_t rxreset_0d	: 1;
275 		uint16_t rxreset_0c	: 1;
276 		uint16_t rxreset_0b	: 1;
277 		uint16_t rxreset_0a	: 1;
278 #else
279 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
280 #endif
281 	} bits;
282 } sr_rx_tx_reset_ctrl_l;
283 
284 
285 typedef	union _sr_rx_tx_reset_ctrl_h {
286 	uint16_t value;
287 	struct {
288 #if defined(_BIT_FIELDS_HTOL)
289 		uint16_t txreset_0a	: 1;
290 		uint16_t txreset_0b	: 1;
291 		uint16_t txreset_0c	: 1;
292 		uint16_t txreset_0d	: 1;
293 		uint16_t txreset_1a	: 1;
294 		uint16_t txreset_1b	: 1;
295 		uint16_t txreset_1c	: 1;
296 		uint16_t txreset_1d	: 1;
297 		uint16_t txreset_2a	: 1;
298 		uint16_t txreset_2b	: 1;
299 		uint16_t txreset_2c	: 1;
300 		uint16_t txreset_2d	: 1;
301 		uint16_t txreset_3a	: 1;
302 		uint16_t txreset_3b	: 1;
303 		uint16_t txreset_3c	: 1;
304 		uint16_t txreset_3d	: 1;
305 #elif defined(_BIT_FIELDS_LTOH)
306 		uint16_t txreset_3d	: 1;
307 		uint16_t txreset_3c	: 1;
308 		uint16_t txreset_3b	: 1;
309 		uint16_t txreset_3a	: 1;
310 		uint16_t txreset_2d	: 1;
311 		uint16_t txreset_2c	: 1;
312 		uint16_t txreset_2b	: 1;
313 		uint16_t txreset_2a	: 1;
314 		uint16_t txreset_1d	: 1;
315 		uint16_t txreset_1c	: 1;
316 		uint16_t txreset_1b	: 1;
317 		uint16_t txreset_1a	: 1;
318 		uint16_t txreset_0d	: 1;
319 		uint16_t txreset_0c	: 1;
320 		uint16_t txreset_0b	: 1;
321 		uint16_t txreset_0a	: 1;
322 #else
323 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
324 #endif
325 	} bits;
326 } sr_rx_tx_reset_ctrl_h;
327 
328 typedef	union _sr_rx_power_ctrl_l {
329 	uint16_t value;
330 	struct {
331 #if defined(_BIT_FIELDS_HTOL)
332 		uint16_t pdrxlos_0a	: 1;
333 		uint16_t pdrxlos_0b	: 1;
334 		uint16_t pdrxlos_0c	: 1;
335 		uint16_t pdrxlos_0d	: 1;
336 		uint16_t pdrxlos_1a	: 1;
337 		uint16_t pdrxlos_1b	: 1;
338 		uint16_t pdrxlos_1c	: 1;
339 		uint16_t pdrxlos_1d	: 1;
340 		uint16_t pdrxlos_2a	: 1;
341 		uint16_t pdrxlos_2b	: 1;
342 		uint16_t pdrxlos_2c	: 1;
343 		uint16_t pdrxlos_2d	: 1;
344 		uint16_t pdrxlos_3a	: 1;
345 		uint16_t pdrxlos_3b	: 1;
346 		uint16_t pdrxlos_3c	: 1;
347 		uint16_t pdrxlos_3d	: 1;
348 #elif defined(_BIT_FIELDS_LTOH)
349 		uint16_t pdrxlos_3d	: 1;
350 		uint16_t pdrxlos_3c	: 1;
351 		uint16_t pdrxlos_3b	: 1;
352 		uint16_t pdrxlos_3a	: 1;
353 		uint16_t pdrxlos_2d	: 1;
354 		uint16_t pdrxlos_2c	: 1;
355 		uint16_t pdrxlos_2b	: 1;
356 		uint16_t pdrxlos_2a	: 1;
357 		uint16_t pdrxlos_1d	: 1;
358 		uint16_t pdrxlos_1c	: 1;
359 		uint16_t pdrxlos_1b	: 1;
360 		uint16_t pdrxlos_1a	: 1;
361 		uint16_t pdrxlos_0d	: 1;
362 		uint16_t pdrxlos_0c	: 1;
363 		uint16_t pdrxlos_0b	: 1;
364 		uint16_t pdrxlos_0a	: 1;
365 #else
366 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
367 #endif
368 	} bits;
369 } sr_rx_power_ctrl_l_t;
370 
371 
372 typedef	union _sr_rx_power_ctrl_h {
373 	uint16_t value;
374 	struct {
375 #if defined(_BIT_FIELDS_HTOL)
376 		uint16_t pdownr_0a	: 1;
377 		uint16_t pdownr_0b	: 1;
378 		uint16_t pdownr_0c	: 1;
379 		uint16_t pdownr_0d	: 1;
380 		uint16_t pdownr_1a	: 1;
381 		uint16_t pdownr_1b	: 1;
382 		uint16_t pdownr_1c	: 1;
383 		uint16_t pdownr_1d	: 1;
384 		uint16_t pdownr_2a	: 1;
385 		uint16_t pdownr_2b	: 1;
386 		uint16_t pdownr_2c	: 1;
387 		uint16_t pdownr_2d	: 1;
388 		uint16_t pdownr_3a	: 1;
389 		uint16_t pdownr_3b	: 1;
390 		uint16_t pdownr_3c	: 1;
391 		uint16_t pdownr_3d	: 1;
392 #elif defined(_BIT_FIELDS_LTOH)
393 		uint16_t pdownr_3d	: 1;
394 		uint16_t pdownr_3c	: 1;
395 		uint16_t pdownr_3b	: 1;
396 		uint16_t pdownr_3a	: 1;
397 		uint16_t pdownr_2d	: 1;
398 		uint16_t pdownr_2c	: 1;
399 		uint16_t pdownr_2b	: 1;
400 		uint16_t pdownr_2a	: 1;
401 		uint16_t pdownr_1d	: 1;
402 		uint16_t pdownr_1c	: 1;
403 		uint16_t pdownr_1b	: 1;
404 		uint16_t pdownr_1a	: 1;
405 		uint16_t pdownr_0d	: 1;
406 		uint16_t pdownr_0c	: 1;
407 		uint16_t pdownr_0b	: 1;
408 		uint16_t pdownr_0a	: 1;
409 #else
410 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
411 #endif
412 	} bits;
413 } sr_rx_power_ctrl_h_t;
414 
415 typedef	union _sr_tx_power_ctrl_l {
416 	uint16_t value;
417 	struct {
418 #if defined(_BIT_FIELDS_HTOL)
419 		uint16_t res1		: 8;
420 		uint16_t pdownppll0	: 1;
421 		uint16_t pdownppll1	: 1;
422 		uint16_t pdownppll2	: 1;
423 		uint16_t pdownppll3	: 1;
424 		uint16_t res2		: 4;
425 #elif defined(_BIT_FIELDS_LTOH)
426 		uint16_t res2		: 4;
427 		uint16_t pdownppll3	: 1;
428 		uint16_t pdownppll2	: 1;
429 		uint16_t pdownppll1	: 1;
430 		uint16_t pdownppll0	: 1;
431 		uint16_t res1		: 8;
432 #else
433 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
434 #endif
435 	} bits;
436 } sr_tx_power_ctrl_l_t;
437 
438 typedef	union _sr_tx_power_ctrl_h {
439 	uint16_t value;
440 	struct {
441 #if defined(_BIT_FIELDS_HTOL)
442 		uint16_t pdownt_0a	: 1;
443 		uint16_t pdownt_0b	: 1;
444 		uint16_t pdownt_0c	: 1;
445 		uint16_t pdownt_0d	: 1;
446 		uint16_t pdownt_1a	: 1;
447 		uint16_t pdownt_1b	: 1;
448 		uint16_t pdownt_1c	: 1;
449 		uint16_t pdownt_1d	: 1;
450 		uint16_t pdownt_2a	: 1;
451 		uint16_t pdownt_2b	: 1;
452 		uint16_t pdownt_2c	: 1;
453 		uint16_t pdownt_2d	: 1;
454 		uint16_t pdownt_3a	: 1;
455 		uint16_t pdownt_3b	: 1;
456 		uint16_t pdownt_3c	: 1;
457 		uint16_t pdownt_3d	: 1;
458 #elif defined(_BIT_FIELDS_LTOH)
459 		uint16_t pdownt_3d	: 1;
460 		uint16_t pdownt_3c	: 1;
461 		uint16_t pdownt_3b	: 1;
462 		uint16_t pdownt_3a	: 1;
463 		uint16_t pdownt_2d	: 1;
464 		uint16_t pdownt_2c	: 1;
465 		uint16_t pdownt_2b	: 1;
466 		uint16_t pdownt_2a	: 1;
467 		uint16_t pdownt_1d	: 1;
468 		uint16_t pdownt_1c	: 1;
469 		uint16_t pdownt_1b	: 1;
470 		uint16_t pdownt_1a	: 1;
471 		uint16_t pdownt_0d	: 1;
472 		uint16_t pdownt_0c	: 1;
473 		uint16_t pdownt_0b	: 1;
474 		uint16_t pdownt_0a	: 1;
475 #else
476 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
477 #endif
478 	} bits;
479 } sr_tx_power_ctrl_h_t;
480 
481 typedef	union _sr_misc_power_ctrl_l {
482 	uint16_t value;
483 	struct {
484 #if defined(_BIT_FIELDS_HTOL)
485 		uint16_t res1		: 3;
486 		uint16_t pdrtrim	: 1;
487 		uint16_t pdownpecl0	: 1;
488 		uint16_t pdownpecl1	: 1;
489 		uint16_t pdownpecl2	: 1;
490 		uint16_t pdownpecl3	: 1;
491 		uint16_t pdownppll0	: 1;
492 		uint16_t pdownppll1	: 1;
493 		uint16_t pdownppll2	: 1;
494 		uint16_t pdownppll3	: 1;
495 		uint16_t res2		: 4;
496 #elif defined(_BIT_FIELDS_LTOH)
497 		uint16_t res2		: 4;
498 		uint16_t pdownppll3	: 1;
499 		uint16_t pdownppll2	: 1;
500 		uint16_t pdownppll1	: 1;
501 		uint16_t pdownppll0	: 1;
502 		uint16_t pdownpecl3	: 1;
503 		uint16_t pdownpecl2	: 1;
504 		uint16_t pdownpecl1	: 1;
505 		uint16_t pdownpecl0	: 1;
506 		uint16_t pdrtrim	: 1;
507 		uint16_t res1		: 3;
508 #else
509 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
510 #endif
511 	} bits;
512 } sr_misc_power_ctrl_l_t;
513 
514 typedef	union _misc_power_ctrl_h {
515 	uint16_t value;
516 	struct {
517 #if defined(_BIT_FIELDS_HTOL)
518 		uint16_t pdclkout0	: 1;
519 		uint16_t pdclkout1	: 1;
520 		uint16_t pdclkout2	: 1;
521 		uint16_t pdclkout3	: 1;
522 		uint16_t res1		: 12;
523 #elif defined(_BIT_FIELDS_LTOH)
524 		uint16_t res1		: 12;
525 		uint16_t pdclkout3	: 1;
526 		uint16_t pdclkout2	: 1;
527 		uint16_t pdclkout1	: 1;
528 		uint16_t pdclkout0	: 1;
529 #else
530 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
531 #endif
532 	} bits;
533 } misc_power_ctrl_h_t;
534 
535 typedef	union _sr_rx_tx_ctrl_l {
536 	uint16_t value;
537 	struct {
538 #if defined(_BIT_FIELDS_HTOL)
539 		uint16_t res1		: 2;
540 		uint16_t rxpreswin	: 2;
541 		uint16_t res2		: 1;
542 		uint16_t risefall	: 3;
543 		uint16_t res3		: 7;
544 		uint16_t enstretch	: 1;
545 #elif defined(_BIT_FIELDS_LTOH)
546 		uint16_t enstretch	: 1;
547 		uint16_t res3		: 7;
548 		uint16_t risefall	: 3;
549 		uint16_t res2		: 1;
550 		uint16_t rxpreswin	: 2;
551 		uint16_t res1		: 2;
552 #else
553 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
554 #endif
555 	} bits;
556 } sr_rx_tx_ctrl_l_t;
557 
558 typedef	union _sr_rx_tx_ctrl_h {
559 	uint16_t value;
560 	struct {
561 #if defined(_BIT_FIELDS_HTOL)
562 		uint16_t biascntl	: 1;
563 		uint16_t res1		: 5;
564 		uint16_t tdenfifo	: 1;
565 		uint16_t tdws20		: 1;
566 		uint16_t vmuxlo		: 2;
567 		uint16_t vpulselo	: 2;
568 		uint16_t res2		: 4;
569 #elif defined(_BIT_FIELDS_LTOH)
570 		uint16_t res2		: 4;
571 		uint16_t vpulselo	: 2;
572 		uint16_t vmuxlo		: 2;
573 		uint16_t tdws20		: 1;
574 		uint16_t tdenfifo	: 1;
575 		uint16_t res1		: 5;
576 		uint16_t biascntl	: 1;
577 #else
578 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
579 #endif
580 	} bits;
581 } sr_rx_tx_ctrl_h_t;
582 
583 #define	RXPRESWIN_52US_300BITTIMES	0
584 #define	RXPRESWIN_53US_300BITTIMES	1
585 #define	RXPRESWIN_54US_300BITTIMES	2
586 #define	RXPRESWIN_55US_300BITTIMES	3
587 
588 typedef	union _sr_rx_tx_tuning_l {
589 	uint16_t value;
590 	struct {
591 #if defined(_BIT_FIELDS_HTOL)
592 		uint16_t rxeq		: 4;
593 		uint16_t res1		: 12;
594 #elif defined(_BIT_FIELDS_LTOH)
595 		uint16_t res1		: 12;
596 		uint16_t rxeq		: 4;
597 #else
598 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
599 #endif
600 	} bits;
601 } sr_rx_tx_tuning_l_t;
602 
603 typedef	union _sr_rx_tx_tuning_h {
604 	uint16_t value;
605 	struct {
606 #if defined(_BIT_FIELDS_HTOL)
607 		uint16_t res1		: 8;
608 		uint16_t rp		: 2;
609 		uint16_t rz		: 2;
610 		uint16_t vtxlo		: 4;
611 #elif defined(_BIT_FIELDS_LTOH)
612 		uint16_t vtxlo		: 4;
613 		uint16_t rz		: 2;
614 		uint16_t rp		: 2;
615 		uint16_t res1		: 8;
616 #else
617 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
618 #endif
619 	} bits;
620 } sr_rx_tx_tuning_h_t;
621 
622 typedef	union _sr_rx_syncchar_l {
623 	uint16_t value;
624 	struct {
625 #if defined(_BIT_FIELDS_HTOL)
626 		uint16_t syncchar_0_3	: 4;
627 		uint16_t res1		: 2;
628 		uint16_t syncmask	: 10;
629 #elif defined(_BIT_FIELDS_LTOH)
630 		uint16_t syncmask	: 10;
631 		uint16_t res1		: 2;
632 		uint16_t syncchar_0_3	: 4;
633 #else
634 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
635 #endif
636 	} bits;
637 } sr_rx_syncchar_l_t;
638 
639 typedef	union _sr_rx_syncchar_h {
640 	uint16_t value;
641 	struct {
642 #if defined(_BIT_FIELDS_HTOL)
643 		uint16_t res1		: 1;
644 		uint16_t syncpol	: 1;
645 		uint16_t res2		: 8;
646 		uint16_t syncchar_4_10	: 6;
647 #elif defined(_BIT_FIELDS_LTOH)
648 		uint16_t syncchar_4_10	: 6;
649 		uint16_t res2		: 8;
650 		uint16_t syncpol	: 1;
651 		uint16_t res1		: 1;
652 #else
653 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
654 #endif
655 	} bits;
656 } sr_rx_syncchar_h_t;
657 
658 typedef	union _sr_rx_tx_test_l {
659 	uint16_t value;
660 	struct {
661 #if defined(_BIT_FIELDS_HTOL)
662 		uint16_t res1		: 15;
663 		uint16_t ref50		: 1;
664 #elif defined(_BIT_FIELDS_LTOH)
665 		uint16_t ref50		: 1;
666 		uint16_t res1		: 15;
667 #else
668 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
669 #endif
670 	} bits;
671 } sr_rx_tx_test_l_t;
672 
673 typedef	union _sr_rx_tx_test_h {
674 	uint16_t value;
675 	struct {
676 #if defined(_BIT_FIELDS_HTOL)
677 		uint16_t res1		: 5;
678 		uint16_t selftest	: 3;
679 		uint16_t res2		: 8;
680 #elif defined(_BIT_FIELDS_LTOH)
681 		uint16_t res2		: 8;
682 		uint16_t selftest	: 3;
683 		uint16_t res1		: 5;
684 #else
685 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
686 #endif
687 	} bits;
688 } sr_rx_tx_test_h_t;
689 
690 typedef	union _sr_glue_ctrl0_l {
691 	uint16_t value;
692 	struct {
693 #if defined(_BIT_FIELDS_HTOL)
694 		uint16_t rxlos_test	: 1;
695 		uint16_t res1		: 1;
696 		uint16_t rxlosenable	: 1;
697 		uint16_t fastresync	: 1;
698 		uint16_t samplerate	: 4;
699 		uint16_t thresholdcount	: 8;
700 #elif defined(_BIT_FIELDS_LTOH)
701 		uint16_t thresholdcount	: 8;
702 		uint16_t samplerate	: 4;
703 		uint16_t fastresync	: 1;
704 		uint16_t rxlosenable	: 1;
705 		uint16_t res1		: 1;
706 		uint16_t rxlos_test	: 1;
707 #else
708 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
709 #endif
710 	} bits;
711 } sr_glue_ctrl0_l_t;
712 
713 typedef	union _sr_glue_ctrl0_h {
714 	uint16_t value;
715 	struct {
716 #if defined(_BIT_FIELDS_HTOL)
717 		uint16_t res1		: 5;
718 		uint16_t bitlocktime	: 3;
719 		uint16_t res2		: 8;
720 #elif defined(_BIT_FIELDS_LTOH)
721 		uint16_t res2		: 8;
722 		uint16_t bitlocktime	: 3;
723 		uint16_t res1		: 5;
724 #else
725 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
726 #endif
727 	} bits;
728 } sr_glue_ctrl0_h_t;
729 
730 #define	BITLOCKTIME_64_CYCLES		0
731 #define	BITLOCKTIME_128_CYCLES		1
732 #define	BITLOCKTIME_256_CYCLES		2
733 #define	BITLOCKTIME_300_CYCLES		3
734 #define	BITLOCKTIME_384_CYCLES		4
735 #define	BITLOCKTIME_512_CYCLES		5
736 #define	BITLOCKTIME_1024_CYCLES		6
737 #define	BITLOCKTIME_2048_CYCLES		7
738 
739 typedef	union _sr_glue_ctrl1_l {
740 	uint16_t value;
741 	struct {
742 #if defined(_BIT_FIELDS_HTOL)
743 		uint16_t res1		: 14;
744 		uint16_t inittime	: 2;
745 #elif defined(_BIT_FIELDS_LTOH)
746 		uint16_t inittime	: 2;
747 		uint16_t res1		: 14;
748 #else
749 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
750 #endif
751 	} bits;
752 } sr_glue_ctrl1_l_t;
753 
754 typedef	union glue_ctrl1_h {
755 	uint16_t value;
756 	struct {
757 #if defined(_BIT_FIELDS_HTOL)
758 		uint16_t termr_cfg	: 2;
759 		uint16_t termt_cfg	: 2;
760 		uint16_t rtrimen	: 2;
761 		uint16_t res1		: 10;
762 #elif defined(_BIT_FIELDS_LTOH)
763 		uint16_t res1		: 10;
764 		uint16_t rtrimen	: 2;
765 		uint16_t termt_cfg	: 2;
766 		uint16_t termr_cfg	: 2;
767 #else
768 #error one of _BIT_FIELDS_HTOL or _BIT_FIELDS_LTOH must be defined
769 #endif
770 	} bits;
771 } glue_ctrl1_h_t;
772 
773 #define	TERM_CFG_67OHM		0
774 #define	TERM_CFG_72OHM		1
775 #define	TERM_CFG_80OHM		2
776 #define	TERM_CFG_87OHM		3
777 #define	TERM_CFG_46OHM		4
778 #define	TERM_CFG_48OHM		5
779 #define	TERM_CFG_52OHM		6
780 #define	TERM_CFG_55OHM		7
781 
782 #define	INITTIME_60US		0
783 #define	INITTIME_120US		1
784 #define	INITTIME_240US		2
785 #define	INITTIME_480US		3
786 
787 #ifdef	__cplusplus
788 }
789 #endif
790 
791 #endif	/* _SYS_NXGE_NXGE_SR_HW_H */
792