1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at
9  * http://www.opensource.org/licenses/cddl1.txt.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright (c) 2004-2012 Emulex. All rights reserved.
24  * Use is subject to license terms.
25  * Copyright 2020 RackTop Systems, Inc.
26  */
27 
28 #ifndef _EMLXS_MBOX_H
29 #define	_EMLXS_MBOX_H
30 
31 #ifdef	__cplusplus
32 extern "C" {
33 #endif
34 
35 /* SLI 2/3 Mailbox defines */
36 
37 #define	MBOX_SIZE			256
38 #define	MBOX_EXTENSION_OFFSET		MBOX_SIZE
39 
40 #ifdef MBOX_EXT_SUPPORT
41 #define	MBOX_EXTENSION_SIZE		1024
42 #else
43 #define	MBOX_EXTENSION_SIZE		0
44 #endif /* MBOX_EXT_SUPPORT */
45 
46 
47 
48 /* ==== Mailbox Commands ==== */
49 #define	MBX_SHUTDOWN			0x00	/* terminate testing */
50 #define	MBX_LOAD_SM			0x01
51 #define	MBX_READ_NV			0x02
52 #define	MBX_WRITE_NV			0x03
53 #define	MBX_RUN_BIU_DIAG		0x04
54 #define	MBX_INIT_LINK			0x05
55 #define	MBX_DOWN_LINK			0x06
56 #define	MBX_CONFIG_LINK			0x07
57 #define	MBX_PART_SLIM			0x08
58 #define	MBX_CONFIG_RING			0x09
59 #define	MBX_RESET_RING			0x0A
60 #define	MBX_READ_CONFIG			0x0B
61 #define	MBX_READ_RCONFIG		0x0C
62 #define	MBX_READ_SPARM			0x0D
63 #define	MBX_READ_STATUS			0x0E
64 #define	MBX_READ_RPI			0x0F
65 #define	MBX_READ_XRI			0x10
66 #define	MBX_READ_REV			0x11
67 #define	MBX_READ_LNK_STAT		0x12
68 #define	MBX_REG_LOGIN			0x13
69 #define	MBX_UNREG_LOGIN			0x14  /* SLI2/3 */
70 #define	MBX_UNREG_RPI			0x14  /* SLI4 */
71 #define	MBX_READ_LA			0x15
72 #define	MBX_CLEAR_LA			0x16
73 #define	MBX_DUMP_MEMORY			0x17
74 #define	MBX_DUMP_CONTEXT		0x18
75 #define	MBX_RUN_DIAGS			0x19
76 #define	MBX_RESTART			0x1A
77 #define	MBX_UPDATE_CFG			0x1B
78 #define	MBX_DOWN_LOAD			0x1C
79 #define	MBX_DEL_LD_ENTRY		0x1D
80 #define	MBX_RUN_PROGRAM			0x1E
81 #define	MBX_SET_MASK			0x20
82 #define	MBX_SET_VARIABLE		0x21
83 #define	MBX_UNREG_D_ID			0x23
84 #define	MBX_KILL_BOARD			0x24
85 #define	MBX_CONFIG_FARP			0x25
86 #define	MBX_BEACON			0x2A
87 #define	MBX_READ_VPI			0x2B
88 #define	MBX_CONFIG_MSIX			0x30
89 #define	MBX_HEARTBEAT			0x31
90 #define	MBX_WRITE_VPARMS		0x32
91 #define	MBX_ASYNC_EVENT			0x33
92 
93 #define	MBX_READ_EVENT_LOG_STATUS	0x37
94 #define	MBX_READ_EVENT_LOG		0x38
95 #define	MBX_WRITE_EVENT_LOG		0x39
96 #define	MBX_NV_LOG			0x3A
97 #define	MBX_PORT_CAPABILITIES		0x3B
98 #define	MBX_IOV_CONTROL			0x3C
99 #define	MBX_IOV_MBX			0x3D
100 
101 
102 #define	MBX_CONFIG_HBQ			0x7C  /* SLI3 */
103 #define	MBX_LOAD_AREA			0x81
104 #define	MBX_RUN_BIU_DIAG64		0x84
105 #define	MBX_GET_DEBUG			0x86
106 #define	MBX_CONFIG_PORT			0x88
107 #define	MBX_READ_SPARM64		0x8D
108 #define	MBX_READ_RPI64			0x8F
109 #define	MBX_CONFIG_MSI			0x90
110 #define	MBX_REG_LOGIN64			0x93 /* SLI2/3 */
111 #define	MBX_REG_RPI			0x93 /* SLI4 */
112 #define	MBX_READ_LA64			0x95 /* SLI2/3 */
113 #define	MBX_READ_TOPOLOGY		0x95 /* SLI4 */
114 #define	MBX_REG_VPI			0x96 /* NPIV */
115 #define	MBX_UNREG_VPI			0x97 /* NPIV */
116 #define	MBX_FLASH_WR_ULA		0x98
117 #define	MBX_SET_DEBUG			0x99
118 #define	MBX_SLI_CONFIG			0x9B
119 #define	MBX_LOAD_EXP_ROM		0x9C
120 #define	MBX_REQUEST_FEATURES		0x9D
121 #define	MBX_RESUME_RPI			0x9E
122 #define	MBX_REG_VFI			0x9F
123 #define	MBX_REG_FCFI			0xA0
124 #define	MBX_UNREG_VFI			0xA1
125 #define	MBX_UNREG_FCFI			0xA2
126 #define	MBX_INIT_VFI			0xA3
127 #define	MBX_INIT_VPI			0xA4
128 #define	MBX_ACCESS_VDATA		0xA5
129 #define	MBX_MAX_CMDS			0xA6
130 
131 
132 /*
133  * Define Status
134  */
135 #define	MBX_SUCCESS			0x0
136 #define	MBX_FAILURE			0x1
137 #define	MBXERR_NUM_IOCBS		0x2
138 #define	MBXERR_IOCBS_EXCEEDED		0x3
139 #define	MBXERR_BAD_RING_NUMBER		0x4
140 #define	MBXERR_MASK_ENTRIES_RANGE	0x5
141 #define	MBXERR_MASKS_EXCEEDED		0x6
142 #define	MBXERR_BAD_PROFILE		0x7
143 #define	MBXERR_BAD_DEF_CLASS		0x8
144 #define	MBXERR_BAD_MAX_RESPONDER	0x9
145 #define	MBXERR_BAD_MAX_ORIGINATOR	0xA
146 #define	MBXERR_RPI_REGISTERED		0xB
147 #define	MBXERR_RPI_FULL			0xC
148 #define	MBXERR_NO_RESOURCES		0xD
149 #define	MBXERR_BAD_RCV_LENGTH		0xE
150 #define	MBXERR_DMA_ERROR		0xF
151 #define	MBXERR_NOT_SUPPORTED		0x10
152 #define	MBXERR_UNSUPPORTED_FEATURE	0x11
153 #define	MBXERR_UNKNOWN_COMMAND		0x12
154 #define	MBXERR_BAD_IP_BIT		0x13
155 #define	MBXERR_BAD_PCB_ALIGN		0x14
156 #define	MBXERR_BAD_HBQ_ID		0x15
157 #define	MBXERR_BAD_HBQ_STATE		0x16
158 #define	MBXERR_BAD_HBQ_MASK_NUM		0x17
159 #define	MBXERR_BAD_HBQ_MASK_SUBSET	0x18
160 #define	MBXERR_HBQ_CREATE_FAIL		0x19
161 #define	MBXERR_HBQ_EXISTING		0x1A
162 #define	MBXERR_HBQ_RSPRING_FULL		0x1B
163 #define	MBXERR_HBQ_DUP_MASK		0x1C
164 #define	MBXERR_HBQ_INVAL_GET_PTR	0x1D
165 #define	MBXERR_BAD_HBQ_SIZE		0x1E
166 #define	MBXERR_BAD_HBQ_ORDER		0x1F
167 #define	MBXERR_INVALID_ID		0x20
168 
169 #define	MBXERR_INVALID_VFI		0x30
170 
171 #define	MBXERR_FLASH_WRITE_FAILED	0x100
172 
173 #define	MBXERR_INVALID_LINKSPEED	0x500
174 
175 #define	MBXERR_BAD_REDIRECT		0x900
176 #define	MBXERR_RING_ALREADY_CONFIG	0x901
177 
178 #define	MBXERR_RING_INACTIVE		0xA00
179 
180 #define	MBXERR_RPI_INACTIVE		0xF00
181 
182 #define	MBXERR_NO_ACTIVE_XRI		0x1100
183 #define	MBXERR_XRI_NOT_ACTIVE		0x1101
184 
185 #define	MBXERR_RPI_INUSE		0x1400
186 
187 #define	MBXERR_NO_LINK_ATTENTION	0x1500
188 
189 #define	MBXERR_INVALID_SLI_MODE		0x8800
190 #define	MBXERR_INVALID_HOST_PTR		0x8801
191 #define	MBXERR_CANT_CFG_SLI_MODE	0x8802
192 #define	MBXERR_BAD_OVERLAY		0x8803
193 #define	MBXERR_INVALID_FEAT_REQ		0x8804
194 
195 #define	MBXERR_CONFIG_CANT_COMPLETE	0x88FF
196 
197 #define	MBXERR_DID_ALREADY_REGISTERED	0x9600
198 #define	MBXERR_DID_INCONSISTENT		0x9601
199 #define	MBXERR_VPI_TOO_LARGE		0x9603
200 
201 #define	MBXERR_STILL_ASSOCIATED		0x9700
202 
203 #define	MBXERR_INVALID_VF_STATE		0x9F00
204 #define	MBXERR_VFI_ALREADY_REGISTERED	0x9F02
205 #define	MBXERR_VFI_TOO_LARGE		0x9F03
206 
207 #define	MBXERR_LOAD_FW_FAILED		0xFFFE
208 #define	MBXERR_FIND_FW_FAILED		0xFFFF
209 
210 /* Driver special codes */
211 #define	MBX_DRIVER_RESERVED		0xF9 /* Set to lowest drv status */
212 #define	MBX_NONEMBED_ERROR		0xF9
213 #define	MBX_OVERTEMP_ERROR		0xFA
214 #define	MBX_HARDWARE_ERROR		0xFB
215 #define	MBX_DRVR_ERROR			0xFC
216 #define	MBX_BUSY			0xFD
217 #define	MBX_TIMEOUT			0xFE
218 #define	MBX_NOT_FINISHED		0xFF
219 
220 /*
221  * flags for EMLXS_SLI_ISSUE_MBOX_CMD()
222  */
223 #define	MBX_POLL	0x01	/* poll mailbox till command done, */
224 				/* then return */
225 #define	MBX_SLEEP	0x02	/* sleep till mailbox intr cmpl */
226 				/* wakes thread up */
227 #define	MBX_WAIT	0x03	/* wait for comand done, then return */
228 #define	MBX_NOWAIT	0x04	/* issue command then return immediately */
229 #define	MBX_BOOTSTRAP	0x80	/* issue a command on the bootstrap mbox */
230 
231 
232 
233 /*
234  * Begin Structure Definitions for Mailbox Commands
235  */
236 
237 typedef struct revcompat
238 {
239 #ifdef EMLXS_BIG_ENDIAN
240 	uint32_t	ldflag:1;	/* Set in SRAM descriptor */
241 	uint32_t	ldcount:7;	/* For use by program load */
242 	uint32_t	kernel:4;	/* Kernel ID */
243 	uint32_t	kver:4;	/* Kernel compatibility version */
244 	uint32_t	SMver:4;	/* Sequence Manager version */
245 					/* 0 if none */
246 	uint32_t	ENDECver:4;	/* ENDEC+ version, 0 if none */
247 	uint32_t	BIUtype:4;	/* PCI = 0 */
248 	uint32_t	BIUver:4;	/* BIU version, 0 if none */
249 #endif
250 #ifdef EMLXS_LITTLE_ENDIAN
251 	uint32_t	BIUver:4;	/* BIU version, 0 if none */
252 	uint32_t	BIUtype:4;	/* PCI = 0 */
253 	uint32_t	ENDECver:4;	/* ENDEC+ version, 0 if none */
254 	uint32_t	SMver:4;	/* Sequence Manager version */
255 					/* 0 if none */
256 	uint32_t	kver:4;	/* Kernel compatibility version */
257 	uint32_t	kernel:4;	/* Kernel ID */
258 	uint32_t	ldcount:7;	/* For use by program load */
259 	uint32_t	ldflag:1;	/* Set in SRAM descriptor */
260 #endif
261 } REVCOMPAT;
262 
263 typedef struct id_word
264 {
265 #ifdef EMLXS_BIG_ENDIAN
266 	uint8_t		Type;
267 	uint8_t		Id;
268 	uint8_t		Ver;
269 	uint8_t		Rev;
270 #endif
271 #ifdef EMLXS_LITTLE_ENDIAN
272 	uint8_t		Rev;
273 	uint8_t		Ver;
274 	uint8_t		Id;
275 	uint8_t		Type;
276 #endif
277 	union
278 	{
279 		REVCOMPAT	cp;
280 		uint32_t	revcomp;
281 	} un;
282 } PROG_ID;
283 
284 typedef struct
285 {
286 #ifdef EMLXS_BIG_ENDIAN
287 	uint8_t		tval;
288 	uint8_t		tmask;
289 	uint8_t		rval;
290 	uint8_t		rmask;
291 #endif
292 #ifdef EMLXS_LITTLE_ENDIAN
293 	uint8_t		rmask;
294 	uint8_t		rval;
295 	uint8_t		tmask;
296 	uint8_t		tval;
297 #endif
298 } RR_REG;
299 
300 
301 /* Structure used for a HBQ entry */
302 typedef struct
303 {
304 	ULP_BDE64	bde;
305 	union UN_TAG
306 	{
307 		uint32_t	w;
308 		struct
309 		{
310 #ifdef EMLXS_BIG_ENDIAN
311 			uint32_t	HBQ_tag:4;
312 			uint32_t	HBQE_tag:28;
313 #endif
314 #ifdef EMLXS_LITTLE_ENDIAN
315 			uint32_t	HBQE_tag:28;
316 			uint32_t	HBQ_tag:4;
317 #endif
318 		} ext;
319 	} unt;
320 } HBQE_t;
321 
322 typedef struct
323 {
324 #ifdef EMLXS_BIG_ENDIAN
325 	uint8_t		tmatch;
326 	uint8_t		tmask;
327 	uint8_t		rctlmatch;
328 	uint8_t		rctlmask;
329 #endif
330 #ifdef EMLXS_LITTLE_ENDIAN
331 	uint8_t		rctlmask;
332 	uint8_t		rctlmatch;
333 	uint8_t		tmask;
334 	uint8_t		tmatch;
335 #endif
336 } HBQ_MASK;
337 
338 #define	EMLXS_MAX_HBQ_BUFFERS	4096
339 
340 typedef struct
341 {
342 	uint32_t	HBQ_num_mask;		/* number of mask entries in */
343 						/* port array */
344 	uint32_t	HBQ_recvNotify;		/* Rcv buffer notification */
345 	uint32_t	HBQ_numEntries;		/* # of entries in HBQ */
346 	uint32_t	HBQ_headerLen;		/* 0 if not profile 4 or 5 */
347 	uint32_t	HBQ_logEntry;		/* Set to 1 if this HBQ used */
348 						/* for LogEntry */
349 	uint32_t	HBQ_profile;		/* Selection profile 0=all, */
350 						/* 7=logentry */
351 	uint32_t	HBQ_ringMask;		/* Binds HBQ to a ring e.g. */
352 						/* Ring0=b0001, ring2=b0100 */
353 	uint32_t	HBQ_id;			/* index of this hbq in ring */
354 						/* of HBQs[] */
355 	uint32_t	HBQ_PutIdx_next;	/* Index to next HBQ slot to */
356 						/* use */
357 	uint32_t	HBQ_PutIdx;		/* HBQ slot to use */
358 	uint32_t	HBQ_GetIdx;		/* Local copy of Get index */
359 						/* from Port */
360 	uint16_t	HBQ_PostBufCnt;		/* Current number of entries */
361 						/* in list */
362 	MATCHMAP	*HBQ_PostBufs[EMLXS_MAX_HBQ_BUFFERS];
363 	MATCHMAP	HBQ_host_buf;		/* HBQ host buffer for HBQEs */
364 	HBQ_MASK	HBQ_Masks[6];
365 
366 	union
367 	{
368 		uint32_t	allprofiles[12];
369 
370 		struct
371 		{
372 #ifdef EMLXS_BIG_ENDIAN
373 			uint32_t	seqlenoff:16;
374 			uint32_t	maxlen:16;
375 #endif
376 #ifdef EMLXS_LITTLE_ENDIAN
377 			uint32_t	maxlen:16;
378 			uint32_t	seqlenoff:16;
379 #endif
380 #ifdef EMLXS_BIG_ENDIAN
381 			uint32_t	rsvd1:28;
382 			uint32_t	seqlenbcnt:4;
383 #endif
384 #ifdef EMLXS_LITTLE_ENDIAN
385 			uint32_t	seqlenbcnt:4;
386 			uint32_t	rsvd1:28;
387 #endif
388 			uint32_t	rsvd[10];
389 		} profile2;
390 
391 		struct
392 		{
393 #ifdef EMLXS_BIG_ENDIAN
394 			uint32_t	seqlenoff:16;
395 			uint32_t	maxlen:16;
396 #endif
397 #ifdef EMLXS_LITTLE_ENDIAN
398 			uint32_t	maxlen:16;
399 			uint32_t	seqlenoff:16;
400 #endif
401 #ifdef EMLXS_BIG_ENDIAN
402 			uint32_t	cmdcodeoff:28;
403 			uint32_t	rsvd1:12;
404 			uint32_t	seqlenbcnt:4;
405 #endif
406 #ifdef EMLXS_LITTLE_ENDIAN
407 			uint32_t	seqlenbcnt:4;
408 			uint32_t	rsvd1:12;
409 			uint32_t	cmdcodeoff:28;
410 #endif
411 			uint32_t	cmdmatch[8];
412 
413 			uint32_t	rsvd[2];
414 		} profile3;
415 
416 		struct
417 		{
418 #ifdef EMLXS_BIG_ENDIAN
419 			uint32_t	seqlenoff:16;
420 			uint32_t	maxlen:16;
421 #endif
422 #ifdef EMLXS_LITTLE_ENDIAN
423 			uint32_t	maxlen:16;
424 			uint32_t	seqlenoff:16;
425 #endif
426 #ifdef EMLXS_BIG_ENDIAN
427 			uint32_t	cmdcodeoff:28;
428 			uint32_t	rsvd1:12;
429 			uint32_t	seqlenbcnt:4;
430 #endif
431 #ifdef EMLXS_LITTLE_ENDIAN
432 			uint32_t	seqlenbcnt:4;
433 			uint32_t	rsvd1:12;
434 			uint32_t	cmdcodeoff:28;
435 #endif
436 			uint32_t	cmdmatch[8];
437 
438 			uint32_t	rsvd[2];
439 		} profile5;
440 	} profiles;
441 } HBQ_INIT_t;
442 
443 
444 
445 /* Structure for MB Command LOAD_SM and DOWN_LOAD */
446 
447 
448 typedef struct
449 {
450 #ifdef EMLXS_BIG_ENDIAN
451 	uint32_t	rsvd2:24;
452 	uint32_t	keep:1;
453 	uint32_t	acknowledgment:1;
454 	uint32_t	version:1;
455 	uint32_t	erase_or_prog:1;
456 	uint32_t	update_flash:1;
457 	uint32_t	update_ram:1;
458 	uint32_t	method:1;
459 	uint32_t	load_cmplt:1;
460 #endif
461 #ifdef EMLXS_LITTLE_ENDIAN
462 	uint32_t	load_cmplt:1;
463 	uint32_t	method:1;
464 	uint32_t	update_ram:1;
465 	uint32_t	update_flash:1;
466 	uint32_t	erase_or_prog:1;
467 	uint32_t	version:1;
468 	uint32_t	acknowledgment:1;
469 	uint32_t	keep:1;
470 	uint32_t	rsvd2:24;
471 #endif
472 
473 #define	DL_FROM_BDE	0	/* method */
474 #define	DL_FROM_SLIM	1
475 
476 #define	PROGRAM_FLASH	0	/* erase_or_prog */
477 #define	ERASE_FLASH	1
478 
479 	uint32_t	dl_to_adr;
480 	uint32_t	dl_len;
481 	union
482 	{
483 		uint32_t	dl_from_slim_offset;
484 		ULP_BDE		dl_from_bde;
485 		ULP_BDE64	dl_from_bde64;
486 		PROG_ID		prog_id;
487 	} un;
488 } LOAD_SM_VAR;
489 
490 
491 /* Structure for MB Command READ_NVPARM (02) */
492 /* Good for SLI2/3 and SLI4 */
493 
494 typedef struct
495 {
496 	uint32_t	rsvd1[3];	/* Read as all one's */
497 	uint32_t	rsvd2;		/* Read as all zero's */
498 	uint32_t	portname[2];	/* N_PORT name */
499 	uint32_t	nodename[2];	/* NODE name */
500 #ifdef EMLXS_BIG_ENDIAN
501 	uint32_t	pref_DID:24;
502 	uint32_t	hardAL_PA:8;
503 #endif
504 #ifdef EMLXS_LITTLE_ENDIAN
505 	uint32_t	hardAL_PA:8;
506 	uint32_t	pref_DID:24;
507 #endif
508 	uint32_t	rsvd3[21];	/* Read as all one's */
509 } READ_NV_VAR;
510 
511 
512 /* Structure for MB Command WRITE_NVPARMS (03) */
513 /* Good for SLI2/3 and SLI4 */
514 
515 typedef struct
516 {
517 	uint32_t	rsvd1[3];	/* Must be all one's */
518 	uint32_t	rsvd2;		/* Must be all zero's */
519 	uint32_t	portname[2];	/* N_PORT name */
520 	uint32_t	nodename[2];	/* NODE name */
521 #ifdef EMLXS_BIG_ENDIAN
522 	uint32_t	pref_DID:24;
523 	uint32_t	hardAL_PA:8;
524 #endif
525 #ifdef EMLXS_LITTLE_ENDIAN
526 	uint32_t	hardAL_PA:8;
527 	uint32_t	pref_DID:24;
528 #endif
529 	uint32_t	rsvd3[21];	/* Must be all one's */
530 } WRITE_NV_VAR;
531 
532 
533 /* Structure for MB Command RUN_BIU_DIAG64 (0x84) */
534 /* Good for SLI2/3 and SLI4 */
535 
536 typedef struct
537 {
538 	uint32_t	rsvd1;
539 	union
540 	{
541 		struct
542 		{
543 			ULP_BDE64	xmit_bde64;
544 			ULP_BDE64	rcv_bde64;
545 		} s2;
546 	} un;
547 } BIU_DIAG_VAR;
548 
549 
550 /* Structure for MB Command INIT_LINK (05) */
551 /* Good for SLI2/3 and SLI4 */
552 
553 typedef struct
554 {
555 #ifdef EMLXS_BIG_ENDIAN
556 	uint32_t	rsvd1:24;
557 	uint32_t	lipsr_AL_PA:8;	/* AL_PA to issue Lip Selective */
558 					/* Reset to */
559 #endif
560 #ifdef EMLXS_LITTLE_ENDIAN
561 	uint32_t	lipsr_AL_PA:8;	/* AL_PA to issue Lip Selective */
562 					/* Reset to */
563 	uint32_t	rsvd1:24;
564 #endif
565 
566 #ifdef EMLXS_BIG_ENDIAN
567 	uint8_t		fabric_AL_PA;	/* If using a Fabric Assigned AL_PA */
568 	uint8_t		rsvd2;
569 	uint16_t	link_flags;
570 #endif
571 #ifdef EMLXS_LITTLE_ENDIAN
572 	uint16_t	link_flags;
573 	uint8_t		rsvd2;
574 	uint8_t		fabric_AL_PA;	/* If using a Fabric Assigned AL_PA */
575 #endif
576 #define	FLAGS_LOCAL_LB			0x01	/* link_flags (=1) */
577 						/* ENDEC loopback */
578 #define	FLAGS_TOPOLOGY_MODE_LOOP_PT	0x00	/* Attempt loop then pt-pt */
579 #define	FLAGS_TOPOLOGY_MODE_PT_PT	0x02	/* Attempt pt-pt only */
580 #define	FLAGS_TOPOLOGY_MODE_LOOP	0x04	/* Attempt loop only */
581 #define	FLAGS_TOPOLOGY_MODE_PT_LOOP	0x06	/* Attempt pt-pt then loop */
582 #define	FLAGS_LIRP_LILP			0x80	/* LIRP / LILP is disabled */
583 
584 #define	FLAGS_TOPOLOGY_FAILOVER		0x0400	/* Bit 10 */
585 #define	FLAGS_LINK_SPEED		0x0800	/* Bit 11 */
586 #define	FLAGS_PREABORT_RETURN		0x4000	/* Bit 14 */
587 
588 	uint32_t	link_speed;	/* NEW_FEATURE */
589 #define	LINK_SPEED_AUTO			0x0	/* Auto selection */
590 #define	LINK_SPEED_1G			0x1	/* 1 Gigabaud */
591 #define	LINK_SPEED_2G			0x2	/* 2 Gigabaud */
592 #define	LINK_SPEED_4G			0x4	/* 4 Gigabaud */
593 #define	LINK_SPEED_8G			0x8	/* 8 Gigabaud */
594 #define	LINK_SPEED_10G			0x10	/* 10 Gigabaud */
595 #define	LINK_SPEED_16G			0x11	/* 16 Gigabaud */
596 #define	LINK_SPEED_32G			0x14	/* 32 Gigabaud */
597 
598 } INIT_LINK_VAR;
599 
600 
601 /* Structure for MB Command DOWN_LINK (06) */
602 /* Good for SLI2/3 and SLI4 */
603 
604 typedef struct
605 {
606 	uint32_t	rsvd1;
607 } DOWN_LINK_VAR;
608 
609 
610 /* Structure for MB Command CONFIG_LINK (07) */
611 
612 typedef struct
613 {
614 #ifdef EMLXS_BIG_ENDIAN
615 	uint32_t	cr:1;
616 	uint32_t	ci:1;
617 	uint32_t	cr_delay:6;
618 	uint32_t	cr_count:8;
619 	uint32_t	rsvd1:8;
620 	uint32_t	MaxBBC:8;
621 #endif
622 #ifdef EMLXS_LITTLE_ENDIAN
623 	uint32_t	MaxBBC:8;	/* Word 0 */
624 	uint32_t	rsvd1:8;
625 	uint32_t	cr_count:8;
626 	uint32_t	cr_delay:6;
627 	uint32_t	ci:1;
628 	uint32_t	cr:1;
629 #endif
630 	uint32_t	myId;		/* Word 1: alpa,n_port_id */
631 	uint32_t	rsvd2;
632 	uint32_t	edtov;		/* Word 3 */
633 	uint32_t	arbtov;		/* Word 4, lp_tov */
634 	uint32_t	ratov;		/* Word 5 */
635 	uint32_t	rttov;
636 	uint32_t	altov;		/* Word 7 */
637 	uint32_t	crtov;		/* Word 8, rsvd9 */
638 #ifdef EMLXS_BIG_ENDIAN
639 	uint32_t	rrq_enable:1;
640 	uint32_t	rrq_immed:1;
641 	uint32_t	rsvd4:29;
642 	uint32_t	ack0_enable:1;
643 	uint32_t	rsvd5:19;
644 	uint32_t	cscn:1;
645 	uint32_t	bbscn:4;
646 	uint32_t	rsvd3:8;	/* Word 9 */
647 #endif
648 #ifdef EMLXS_LITTLE_ENDIAN
649 	uint32_t	rsvd3:8;	/* Word 9 */
650 	uint32_t	bbscn:4;
651 	uint32_t	cscn:1;
652 	uint32_t	rsvd5:19;
653 	uint32_t	ack0_enable:1;	/* Word 10, BSD dont have, but Linux */
654 	uint32_t	rsvd4:29;
655 	uint32_t	rrq_immed:1;
656 	uint32_t	rrq_enable:1;
657 #endif
658 } CONFIG_LINK;
659 
660 
661 /* Structure for MB Command PART_SLIM (08) */
662 
663 typedef struct
664 {
665 #ifdef EMLXS_BIG_ENDIAN
666 	uint32_t		unused1:24;
667 	uint32_t		numRing:8;
668 #endif
669 #ifdef EMLXS_LITTLE_ENDIAN
670 	uint32_t		numRing:8;
671 	uint32_t		unused1:24;
672 #endif
673 	emlxs_ring_def_t	ringdef[4];
674 	uint32_t		hbainit;
675 } PART_SLIM_VAR;
676 
677 
678 /* Structure for MB Command CONFIG_RING (09) */
679 
680 typedef struct
681 {
682 #ifdef EMLXS_BIG_ENDIAN
683 	uint32_t	unused2:6;
684 	uint32_t	recvSeq:1;
685 	uint32_t	recvNotify:1;
686 	uint32_t	numMask:8;
687 	uint32_t	profile:8;
688 	uint32_t	unused1:4;
689 	uint32_t	ring:4;
690 #endif
691 #ifdef EMLXS_LITTLE_ENDIAN
692 	uint32_t	ring:4;
693 	uint32_t	unused1:4;
694 	uint32_t	profile:8;
695 	uint32_t	numMask:8;
696 	uint32_t	recvNotify:1;
697 	uint32_t	recvSeq:1;
698 	uint32_t	unused2:6;
699 #endif
700 #ifdef EMLXS_BIG_ENDIAN
701 	uint16_t	maxRespXchg;
702 	uint16_t	maxOrigXchg;
703 #endif
704 #ifdef EMLXS_LITTLE_ENDIAN
705 	uint16_t	maxOrigXchg;
706 	uint16_t	maxRespXchg;
707 #endif
708 	RR_REG		rrRegs[6];
709 } CONFIG_RING_VAR;
710 
711 
712 /* Structure for MB Command RESET_RING (10) */
713 
714 typedef struct
715 {
716 	uint32_t	ring_no;
717 } RESET_RING_VAR;
718 
719 
720 /* Structure for MB Command READ_CONFIG (11) */
721 /* Good for SLI2/3 only */
722 
723 typedef struct
724 {
725 #ifdef EMLXS_BIG_ENDIAN
726 	uint32_t	cr:1;
727 	uint32_t	ci:1;
728 	uint32_t	cr_delay:6;
729 	uint32_t	cr_count:8;
730 	uint32_t	InitBBC:8;
731 	uint32_t	MaxBBC:8;
732 #endif
733 #ifdef EMLXS_LITTLE_ENDIAN
734 	uint32_t	MaxBBC:8;
735 	uint32_t	InitBBC:8;
736 	uint32_t	cr_count:8;
737 	uint32_t	cr_delay:6;
738 	uint32_t	ci:1;
739 	uint32_t	cr:1;
740 #endif
741 #ifdef EMLXS_BIG_ENDIAN
742 	uint32_t	topology:8;
743 	uint32_t	myDid:24;
744 #endif
745 #ifdef EMLXS_LITTLE_ENDIAN
746 	uint32_t	myDid:24;
747 	uint32_t	topology:8;
748 #endif
749 	/* Defines for topology (defined previously) */
750 #ifdef EMLXS_BIG_ENDIAN
751 	uint32_t	AR:1;
752 	uint32_t	IR:1;
753 	uint32_t	rsvd1:29;
754 	uint32_t	ack0:1;
755 #endif
756 #ifdef EMLXS_LITTLE_ENDIAN
757 	uint32_t	ack0:1;
758 	uint32_t	rsvd1:29;
759 	uint32_t	IR:1;
760 	uint32_t	AR:1;
761 #endif
762 	uint32_t	edtov;
763 	uint32_t	arbtov;
764 	uint32_t	ratov;
765 	uint32_t	rttov;
766 	uint32_t	altov;
767 	uint32_t	lmt;
768 
769 #define	LMT_1GB_CAPABLE		0x0004
770 #define	LMT_2GB_CAPABLE		0x0008
771 #define	LMT_4GB_CAPABLE		0x0040
772 #define	LMT_8GB_CAPABLE		0x0080
773 #define	LMT_10GB_CAPABLE	0x0100
774 #define	LMT_16GB_CAPABLE	0x0200
775 #define	LMT_32GB_CAPABLE	0x0400
776 /* E2E supported on adapters >= 8GB */
777 #define	LMT_E2E_CAPABLE		(LMT_8GB_CAPABLE|LMT_10GB_CAPABLE)
778 
779 	uint32_t	rsvd2;
780 	uint32_t	rsvd3;
781 	uint32_t	max_xri;
782 	uint32_t	max_iocb;
783 	uint32_t	max_rpi;
784 	uint32_t	avail_xri;
785 	uint32_t	avail_iocb;
786 	uint32_t	avail_rpi;
787 	uint32_t	max_vpi;
788 	uint32_t	max_alpa;
789 	uint32_t	rsvd4;
790 	uint32_t	avail_vpi;
791 
792 } READ_CONFIG_VAR;
793 
794 
795 /* Structure for MB Command READ_CONFIG(0x11) */
796 /* Good for SLI4 only */
797 
798 typedef struct
799 {
800 #ifdef EMLXS_BIG_ENDIAN
801 	uint32_t	extents:1;	/* Word 1 */
802 	uint32_t	rsvd1:31;
803 
804 	uint32_t	topology:8;	/* Word 2 */
805 	uint32_t	ptv:1;
806 	uint32_t	tf:1;
807 	uint32_t	pt:2;
808 	uint32_t	:4;
809 	uint32_t	trunk:4;
810 	uint32_t	:3;
811 	uint32_t	ldv:1;
812 	uint32_t	link_type:2;
813 	uint32_t	link_number:6;
814 #endif
815 #ifdef EMLXS_LITTLE_ENDIAN
816 	uint32_t	rsvd1:31;	/* Word 1 */
817 	uint32_t	extents:1;
818 
819 	uint32_t	link_number:6;	/* Word 2 */
820 	uint32_t	link_type:2;
821 	uint32_t	ldv:1;
822 	uint32_t	:3;
823 	uint32_t	trunk:4;
824 	uint32_t	:4;
825 	uint32_t	pt:2;
826 	uint32_t	tf:1;
827 	uint32_t	ptv:1;
828 	uint32_t	topology:8;
829 #endif
830 	uint32_t	rsvd3;		/* Word 3 */
831 	uint32_t	edtov;		/* Word 4 E_D_TOV timer value */
832 	uint32_t	rsvd4;		/* Word 5 */
833 	uint32_t	ratov;		/* Word 6 R_A_TOV timer value */
834 	uint32_t	rsvd5;		/* Word 7 */
835 	uint32_t	rsvd6;		/* Word 8 */
836 	uint32_t	lmt;		/* Word 9 */
837 	uint32_t	rsvd8;		/* Word 10 */
838 	uint32_t	rsvd9;		/* Word 11 */
839 
840 #ifdef EMLXS_BIG_ENDIAN
841 	uint16_t	XRICount;	/* Word 12 */
842 	uint16_t	XRIBase;	/* Word 12 */
843 
844 	uint16_t	RPICount;	/* Word 13 */
845 	uint16_t	RPIBase;	/* Word 13 */
846 
847 	uint16_t	VPICount;	/* Word 14 */
848 	uint16_t	VPIBase;	/* Word 14 */
849 
850 	uint16_t	VFICount;	/* Word 15 */
851 	uint16_t	VFIBase;	/* Word 15 */
852 
853 	uint16_t	FCFICount;	/* Word 16 */
854 	uint16_t	rsvd10;		/* Word 16 */
855 
856 	uint16_t	EQCount;	/* Word 17 */
857 	uint16_t	RQCount;	/* Word 17 */
858 
859 	uint16_t	CQCount;	/* Word 18 */
860 	uint16_t	WQCount;	/* Word 18 */
861 #endif
862 #ifdef EMLXS_LITTLE_ENDIAN
863 	uint16_t	XRIBase;	/* Word 12 */
864 	uint16_t	XRICount;	/* Word 12 */
865 
866 	uint16_t	RPIBase;	/* Word 13 */
867 	uint16_t	RPICount;	/* Word 13 */
868 
869 	uint16_t	VPIBase;	/* Word 14 */
870 	uint16_t	VPICount;	/* Word 14 */
871 
872 	uint16_t	VFIBase;	/* Word 15 */
873 	uint16_t	VFICount;	/* Word 15 */
874 
875 	uint16_t	rsvd10;		/* Word 16 */
876 	uint16_t	FCFICount;	/* Word 16 */
877 
878 	uint16_t	RQCount;	/* Word 17 */
879 	uint16_t	EQCount;	/* Word 17 */
880 
881 	uint16_t	WQCount;	/* Word 18 */
882 	uint16_t	CQCount;	/* Word 18 */
883 #endif
884 
885 } READ_CONFIG4_VAR;
886 
887 /* Structure for MB Command READ_RCONFIG (12) */
888 
889 typedef struct
890 {
891 #ifdef EMLXS_BIG_ENDIAN
892 	uint32_t	rsvd2:7;
893 	uint32_t	recvNotify:1;
894 	uint32_t	numMask:8;
895 	uint32_t	profile:8;
896 	uint32_t	rsvd1:4;
897 	uint32_t	ring:4;
898 #endif
899 #ifdef EMLXS_LITTLE_ENDIAN
900 	uint32_t	ring:4;
901 	uint32_t	rsvd1:4;
902 	uint32_t	profile:8;
903 	uint32_t	numMask:8;
904 	uint32_t	recvNotify:1;
905 	uint32_t	rsvd2:7;
906 #endif
907 #ifdef EMLXS_BIG_ENDIAN
908 	uint16_t	maxResp;
909 	uint16_t	maxOrig;
910 #endif
911 #ifdef EMLXS_LITTLE_ENDIAN
912 	uint16_t	maxOrig;
913 	uint16_t	maxResp;
914 #endif
915 	RR_REG		rrRegs[6];
916 #ifdef EMLXS_BIG_ENDIAN
917 	uint16_t	cmdRingOffset;
918 	uint16_t	cmdEntryCnt;
919 	uint16_t	rspRingOffset;
920 	uint16_t	rspEntryCnt;
921 	uint16_t	nextCmdOffset;
922 	uint16_t	rsvd3;
923 	uint16_t	nextRspOffset;
924 	uint16_t	rsvd4;
925 #endif
926 #ifdef EMLXS_LITTLE_ENDIAN
927 	uint16_t	cmdEntryCnt;
928 	uint16_t	cmdRingOffset;
929 	uint16_t	rspEntryCnt;
930 	uint16_t	rspRingOffset;
931 	uint16_t	rsvd3;
932 	uint16_t	nextCmdOffset;
933 	uint16_t	rsvd4;
934 	uint16_t	nextRspOffset;
935 #endif
936 } READ_RCONF_VAR;
937 
938 
939 /* Structure for MB Command READ_SPARM (13) */
940 /* Structure for MB Command READ_SPARM64 (0x8D) */
941 /* Good for SLI2/3 and SLI4 */
942 
943 typedef struct
944 {
945 	uint32_t	rsvd1;
946 	uint32_t	rsvd2;
947 	union
948 	{
949 		ULP_BDE		sp;	/* This BDE points to SERV_PARM */
950 					/* structure */
951 		ULP_BDE64	sp64;
952 	} un;
953 	uint32_t	rsvd3;
954 
955 #ifdef EMLXS_BIG_ENDIAN
956 	uint16_t	portNameCnt;
957 	uint16_t	portNameOffset;
958 
959 	uint16_t	fabricNameCnt;
960 	uint16_t	fabricNameOffset;
961 
962 	uint16_t	lportNameCnt;
963 	uint16_t	lportNameOffset;
964 
965 	uint16_t	lfabricNameCnt;
966 	uint16_t	lfabricNameOffset;
967 
968 #endif
969 #ifdef EMLXS_LITTLE_ENDIAN
970 	uint16_t	portNameOffset;
971 	uint16_t	portNameCnt;
972 
973 	uint16_t	fabricNameOffset;
974 	uint16_t	fabricNameCnt;
975 
976 	uint16_t	lportNameOffset;
977 	uint16_t	lportNameCnt;
978 
979 	uint16_t	lfabricNameOffset;
980 	uint16_t	lfabricNameCnt;
981 
982 #endif
983 
984 } READ_SPARM_VAR;
985 
986 
987 /* Structure for MB Command READ_STATUS (14) */
988 /* Good for SLI2/3 and SLI4 */
989 
990 typedef struct
991 {
992 #ifdef EMLXS_BIG_ENDIAN
993 	uint32_t	rsvd1:31;
994 	uint32_t	clrCounters:1;
995 
996 	uint16_t	activeXriCnt;
997 	uint16_t	activeRpiCnt;
998 #endif
999 #ifdef EMLXS_LITTLE_ENDIAN
1000 	uint32_t	clrCounters:1;
1001 	uint32_t	rsvd1:31;
1002 
1003 	uint16_t	activeRpiCnt;
1004 	uint16_t	activeXriCnt;
1005 #endif
1006 	uint32_t	xmitByteCnt;
1007 	uint32_t	rcvByteCnt;
1008 	uint32_t	xmitFrameCnt;
1009 	uint32_t	rcvFrameCnt;
1010 	uint32_t	xmitSeqCnt;
1011 	uint32_t	rcvSeqCnt;
1012 	uint32_t	totalOrigExchanges;
1013 	uint32_t	totalRespExchanges;
1014 	uint32_t	rcvPbsyCnt;
1015 	uint32_t	rcvFbsyCnt;
1016 } READ_STATUS_VAR;
1017 
1018 
1019 /* Structure for MB Command READ_RPI (15) */
1020 /* Structure for MB Command READ_RPI64 (0x8F) */
1021 
1022 typedef struct
1023 {
1024 #ifdef EMLXS_BIG_ENDIAN
1025 	uint16_t	nextRpi;
1026 	uint16_t	reqRpi;
1027 	uint32_t	rsvd2:8;
1028 	uint32_t	DID:24;
1029 #endif
1030 #ifdef EMLXS_LITTLE_ENDIAN
1031 	uint16_t	reqRpi;
1032 	uint16_t	nextRpi;
1033 	uint32_t	DID:24;
1034 	uint32_t	rsvd2:8;
1035 #endif
1036 	union
1037 	{
1038 		ULP_BDE		sp;
1039 		ULP_BDE64	sp64;
1040 	} un;
1041 } READ_RPI_VAR;
1042 
1043 
1044 /* Structure for MB Command READ_XRI (16) */
1045 
1046 typedef struct
1047 {
1048 #ifdef EMLXS_BIG_ENDIAN
1049 	uint16_t	nextXri;
1050 	uint16_t	reqXri;
1051 	uint16_t	rsvd1;
1052 	uint16_t	rpi;
1053 	uint32_t	rsvd2:8;
1054 	uint32_t	DID:24;
1055 	uint32_t	rsvd3:8;
1056 	uint32_t	SID:24;
1057 	uint32_t	rsvd4;
1058 	uint8_t		seqId;
1059 	uint8_t		rsvd5;
1060 	uint16_t	seqCount;
1061 	uint16_t	oxId;
1062 	uint16_t	rxId;
1063 	uint32_t	rsvd6:30;
1064 	uint32_t	si:1;
1065 	uint32_t	exchOrig:1;
1066 #endif
1067 #ifdef EMLXS_LITTLE_ENDIAN
1068 	uint16_t	reqXri;
1069 	uint16_t	nextXri;
1070 	uint16_t	rpi;
1071 	uint16_t	rsvd1;
1072 	uint32_t	DID:24;
1073 	uint32_t	rsvd2:8;
1074 	uint32_t	SID:24;
1075 	uint32_t	rsvd3:8;
1076 	uint32_t	rsvd4;
1077 	uint16_t	seqCount;
1078 	uint8_t		rsvd5;
1079 	uint8_t		seqId;
1080 	uint16_t	rxId;
1081 	uint16_t	oxId;
1082 	uint32_t	exchOrig:1;
1083 	uint32_t	si:1;
1084 	uint32_t	rsvd6:30;
1085 #endif
1086 } READ_XRI_VAR;
1087 
1088 
1089 /* Structure for MB Command READ_REV (17) */
1090 /* Good for SLI2/3 only */
1091 
1092 typedef struct
1093 {
1094 #ifdef EMLXS_BIG_ENDIAN
1095 	uint32_t	cv:1;
1096 	uint32_t	rr:1;
1097 	uint32_t	co:1;
1098 	uint32_t	rp:1;
1099 	uint32_t	cv3:1;
1100 	uint32_t	rf3:1;
1101 	uint32_t	rsvd1:10;
1102 	uint32_t	offset:14;
1103 	uint32_t	rv:2;
1104 #endif
1105 #ifdef EMLXS_LITTLE_ENDIAN
1106 	uint32_t	rv:2;
1107 	uint32_t	offset:14;
1108 	uint32_t	rsvd1:10;
1109 	uint32_t	rf3:1;
1110 	uint32_t	cv3:1;
1111 	uint32_t	rp:1;
1112 	uint32_t	co:1;
1113 	uint32_t	rr:1;
1114 	uint32_t	cv:1;
1115 #endif
1116 	uint32_t	biuRev;
1117 	uint32_t	smRev;
1118 	union
1119 	{
1120 		uint32_t	smFwRev;
1121 		struct
1122 		{
1123 #ifdef EMLXS_BIG_ENDIAN
1124 			uint8_t		ProgType;
1125 			uint8_t		ProgId;
1126 			uint16_t	ProgVer:4;
1127 			uint16_t	ProgRev:4;
1128 			uint16_t	ProgFixLvl:2;
1129 			uint16_t	ProgDistType:2;
1130 			uint16_t	DistCnt:4;
1131 #endif
1132 #ifdef EMLXS_LITTLE_ENDIAN
1133 			uint16_t	DistCnt:4;
1134 			uint16_t	ProgDistType:2;
1135 			uint16_t	ProgFixLvl:2;
1136 			uint16_t	ProgRev:4;
1137 			uint16_t	ProgVer:4;
1138 			uint8_t		ProgId;
1139 			uint8_t		ProgType;
1140 #endif
1141 		} b;
1142 	} un;
1143 	uint32_t	endecRev;
1144 #ifdef EMLXS_BIG_ENDIAN
1145 	uint8_t		feaLevelHigh;
1146 	uint8_t		feaLevelLow;
1147 	uint8_t		fcphHigh;
1148 	uint8_t		fcphLow;
1149 #endif
1150 #ifdef EMLXS_LITTLE_ENDIAN
1151 	uint8_t		fcphLow;
1152 	uint8_t		fcphHigh;
1153 	uint8_t		feaLevelLow;
1154 	uint8_t		feaLevelHigh;
1155 #endif
1156 	uint32_t	postKernRev;
1157 	uint32_t	opFwRev;
1158 	uint8_t		opFwName[16];
1159 
1160 	uint32_t	sliFwRev1;
1161 	uint8_t		sliFwName1[16];
1162 	uint32_t	sliFwRev2;
1163 	uint8_t		sliFwName2[16];
1164 } READ_REV_VAR;
1165 
1166 /* Structure for MB Command READ_REV (17) */
1167 /* Good for SLI4 only */
1168 
1169 typedef struct
1170 {
1171 #ifdef EMLXS_BIG_ENDIAN
1172 	uint32_t	Rsvd3:2;
1173 	uint32_t	VPD:1;
1174 	uint32_t	rsvd2:6;
1175 	uint32_t	dcbxMode:2;
1176 	uint32_t	FCoE:1;
1177 	uint32_t	sliLevel:4;
1178 	uint32_t	rsvd1:16;
1179 #endif
1180 #ifdef EMLXS_LITTLE_ENDIAN
1181 	uint32_t	rsvd1:16;
1182 	uint32_t	sliLevel:4;
1183 	uint32_t	FCoE:1;
1184 	uint32_t	dcbxMode:2;
1185 	uint32_t	rsvd2:6;
1186 	uint32_t	VPD:1;
1187 	uint32_t	Rsvd3:2;
1188 #endif
1189 
1190 	uint32_t	HwRev1;
1191 	uint32_t	HwRev2;
1192 	uint32_t	Rsvd4;
1193 	uint32_t	HwRev3;
1194 
1195 #ifdef EMLXS_BIG_ENDIAN
1196 	uint8_t		feaLevelHigh;
1197 	uint8_t		feaLevelLow;
1198 	uint8_t		fcphHigh;
1199 	uint8_t		fcphLow;
1200 #endif
1201 #ifdef EMLXS_LITTLE_ENDIAN
1202 	uint8_t		fcphLow;
1203 	uint8_t		fcphHigh;
1204 	uint8_t		feaLevelLow;
1205 	uint8_t		feaLevelHigh;
1206 #endif
1207 
1208 	uint32_t	Redboot;
1209 
1210 	uint32_t	ARMFwId;
1211 	uint8_t		ARMFwName[16];
1212 
1213 	uint32_t	ULPFwId;
1214 	uint8_t		ULPFwName[16];
1215 
1216 	uint32_t	Rsvd6[30];
1217 
1218 	ULP_BDE64	VPDBde;
1219 
1220 	uint32_t	ReturnedVPDLength;
1221 
1222 } READ_REV4_VAR;
1223 
1224 #define	EMLXS_DCBX_MODE_CIN	0	/* Mapped to nonFIP mode */
1225 #define	EMLXS_DCBX_MODE_CEE	1	/* Mapped to FIP mode */
1226 
1227 /* Structure for MB Command READ_LINK_STAT (18) */
1228 /* Good for SLI2/3 and SLI4 */
1229 
1230 typedef struct
1231 {
1232 #ifdef EMLXS_BIG_ENDIAN
1233 	uint32_t	clof:1;		/* clear_overflow_flags */
1234 	uint32_t	clrc:1;		/* clear_all_counters */
1235 	uint32_t	resv0:8;
1236 	uint32_t	w21of:1;
1237 	uint32_t	w20of:1;
1238 	uint32_t	w19of:1;
1239 	uint32_t	w18of:1;
1240 	uint32_t	w17of:1;
1241 	uint32_t	w16of:1;
1242 	uint32_t	w15of:1;
1243 	uint32_t	w14of:1;
1244 	uint32_t	w13of:1;
1245 	uint32_t	w12of:1;
1246 	uint32_t	w11of:1;
1247 	uint32_t	w10of:1;
1248 	uint32_t	w09of:1;
1249 	uint32_t	w08of:1;
1250 	uint32_t	w07of:1;
1251 	uint32_t	w06of:1;
1252 	uint32_t	w05of:1;
1253 	uint32_t	w04of:1;
1254 	uint32_t	w03of:1;
1255 	uint32_t	w02of:1;	/* counter overflow flags */
1256 	uint32_t	gec:1;
1257 	uint32_t	rec:1;		/* req_ext_counters */
1258 #endif
1259 #ifdef EMLXS_LITTLE_ENDIAN
1260 	uint32_t	rec:1;		/* req_ext_counters */
1261 	uint32_t	gec:1;
1262 	uint32_t	w02of:1;	/* counter overflow flags */
1263 	uint32_t	w03of:1;
1264 	uint32_t	w04of:1;
1265 	uint32_t	w05of:1;
1266 	uint32_t	w06of:1;
1267 	uint32_t	w07of:1;
1268 	uint32_t	w08of:1;
1269 	uint32_t	w09of:1;
1270 	uint32_t	w10of:1;
1271 	uint32_t	w11of:1;
1272 	uint32_t	w12of:1;
1273 	uint32_t	w13of:1;
1274 	uint32_t	w14of:1;
1275 	uint32_t	w15of:1;
1276 	uint32_t	w16of:1;
1277 	uint32_t	w17of:1;
1278 	uint32_t	w18of:1;
1279 	uint32_t	w19of:1;
1280 	uint32_t	w20of:1;
1281 	uint32_t	w21of:1;
1282 	uint32_t	resv0:8;
1283 	uint32_t	clrc:1;		/* clear_all_counters */
1284 	uint32_t	clof:1;		/* clear_overflow_flags */
1285 #endif
1286 
1287 	uint32_t	linkFailureCnt;
1288 	uint32_t	lossSyncCnt;
1289 
1290 	uint32_t	lossSignalCnt;
1291 	uint32_t	primSeqErrCnt;
1292 	uint32_t	invalidXmitWord;
1293 	uint32_t	crcCnt;
1294 	uint32_t	primSeqTimeout;
1295 	uint32_t	elasticOverrun;
1296 	uint32_t	arbTimeout;
1297 
1298 	uint32_t	rxBufCredit;
1299 	uint32_t	rxBufCreditCur;
1300 
1301 	uint32_t	txBufCredit;
1302 	uint32_t	txBufCreditCur;
1303 
1304 	uint32_t	EOFaCnt;
1305 	uint32_t	EOFdtiCnt;
1306 	uint32_t	EOFniCnt;
1307 	uint32_t	SOFfCnt;
1308 	uint32_t	DropAERCnt;
1309 	uint32_t	DropRcv;
1310 	uint32_t	DropRcvXri;
1311 } READ_LNK_VAR;
1312 
1313 
1314 /* Structure for MB Command REG_LOGIN (19) */
1315 /* Structure for MB Command REG_LOGIN64 (0x93) */
1316 /* Structure for MB Command REG_RPI (0x93) */
1317 /* Good for SLI2/3 and SLI4 */
1318 
1319 typedef struct
1320 {
1321 #ifdef EMLXS_BIG_ENDIAN
1322 	uint16_t	rsvd1;
1323 	uint16_t	rpi;
1324 	uint32_t	CI:1;
1325 	uint32_t	rsvd2:1;
1326 	uint32_t	TERP:1;
1327 	uint32_t	rsvd3:4;
1328 	uint32_t	update:1;
1329 	uint32_t	did:24;
1330 #endif
1331 #ifdef EMLXS_LITTLE_ENDIAN
1332 	uint16_t	rpi;
1333 	uint16_t	rsvd1;
1334 	uint32_t	did:24;
1335 	uint32_t	update:1;
1336 	uint32_t	rsvd3:4;
1337 	uint32_t	TERP:1;
1338 	uint32_t	rsvd2:1;
1339 	uint32_t	CI:1;
1340 #endif
1341 	union
1342 	{
1343 		ULP_BDE		sp;
1344 		ULP_BDE64	sp64;
1345 	} un;
1346 
1347 #ifdef EMLXS_BIG_ENDIAN
1348 	uint16_t	rsvd6;
1349 	uint16_t	vpi;
1350 #endif
1351 #ifdef EMLXS_LITTLE_ENDIAN
1352 	uint16_t	vpi;
1353 	uint16_t	rsvd6;
1354 #endif
1355 } REG_LOGIN_VAR;
1356 
1357 /* Word 30 contents for REG_LOGIN */
1358 typedef union
1359 {
1360 	struct
1361 	{
1362 #ifdef EMLXS_BIG_ENDIAN
1363 		uint16_t	rsvd1:12;
1364 		uint16_t	class:4;
1365 		uint16_t	xri;
1366 #endif
1367 #ifdef EMLXS_LITTLE_ENDIAN
1368 		uint16_t	xri;
1369 		uint16_t	class:4;
1370 		uint16_t	rsvd1:12;
1371 #endif
1372 	} f;
1373 	uint32_t	word;
1374 } REG_WD30;
1375 
1376 
1377 /* Structure for MB Command UNREG_LOGIN (0x14) - SLI2/3 */
1378 /* Structure for MB Command UNREG_RPI (0x14) - SLI4 */
1379 
1380 typedef struct
1381 {
1382 #ifdef EMLXS_BIG_ENDIAN
1383 	uint16_t	ll:2;		/* SLI4 only */
1384 	uint16_t	rsvd1:14;
1385 	uint16_t	rpi;
1386 #endif
1387 #ifdef EMLXS_LITTLE_ENDIAN
1388 	uint16_t	rpi;
1389 	uint16_t	rsvd1:14;
1390 	uint16_t	ll:2;		/* SLI4 only */
1391 #endif
1392 
1393 	uint32_t	rsvd2;
1394 	uint32_t	rsvd3;
1395 	uint32_t	rsvd4;
1396 	uint32_t	rsvd5;
1397 #ifdef EMLXS_BIG_ENDIAN
1398 	uint16_t	rsvd6;
1399 	uint16_t	vpi;
1400 #endif
1401 #ifdef EMLXS_LITTLE_ENDIAN
1402 	uint16_t	vpi;
1403 	uint16_t	rsvd6;
1404 #endif
1405 } UNREG_LOGIN_VAR;
1406 
1407 /* Structure for MB Command REG_FCFI (0xA0) */
1408 /* Good for SLI4 only */
1409 
1410 typedef struct
1411 {
1412 #ifdef EMLXS_BIG_ENDIAN
1413 	uint16_t	FCFI;
1414 	uint16_t	InfoIndex;
1415 
1416 	uint16_t	RQId0;
1417 	uint16_t	RQId1;
1418 	uint16_t	RQId2;
1419 	uint16_t	RQId3;
1420 
1421 	uint8_t		Id0_type;
1422 	uint8_t		Id0_type_mask;
1423 	uint8_t		Id0_rctl;
1424 	uint8_t		Id0_rctl_mask;
1425 
1426 	uint8_t		Id1_type;
1427 	uint8_t		Id1_type_mask;
1428 	uint8_t		Id1_rctl;
1429 	uint8_t		Id1_rctl_mask;
1430 
1431 	uint8_t		Id2_type;
1432 	uint8_t		Id2_type_mask;
1433 	uint8_t		Id2_rctl;
1434 	uint8_t		Id2_rctl_mask;
1435 
1436 	uint8_t		Id3_type;
1437 	uint8_t		Id3_type_mask;
1438 	uint8_t		Id3_rctl;
1439 	uint8_t		Id3_rctl_mask;
1440 
1441 	uint32_t	Rsvd1: 17;
1442 	uint32_t	mam: 2;
1443 	uint32_t	vv: 1;
1444 	uint32_t	vlanTag: 12;
1445 #endif
1446 #ifdef EMLXS_LITTLE_ENDIAN
1447 	uint16_t	InfoIndex;
1448 	uint16_t	FCFI;
1449 
1450 	uint16_t	RQId1;
1451 	uint16_t	RQId0;
1452 	uint16_t	RQId3;
1453 	uint16_t	RQId2;
1454 
1455 	uint8_t		Id0_rctl_mask;
1456 	uint8_t		Id0_rctl;
1457 	uint8_t		Id0_type_mask;
1458 	uint8_t		Id0_type;
1459 
1460 	uint8_t		Id1_rctl_mask;
1461 	uint8_t		Id1_rctl;
1462 	uint8_t		Id1_type_mask;
1463 	uint8_t		Id1_type;
1464 
1465 	uint8_t		Id2_rctl_mask;
1466 	uint8_t		Id2_rctl;
1467 	uint8_t		Id2_type_mask;
1468 	uint8_t		Id2_type;
1469 
1470 	uint8_t		Id3_rctl_mask;
1471 	uint8_t		Id3_rctl;
1472 	uint8_t		Id3_type_mask;
1473 	uint8_t		Id3_type;
1474 
1475 	uint32_t	vlanTag: 12;
1476 	uint32_t	vv: 1;
1477 	uint32_t	mam: 2;
1478 	uint32_t	Rsvd1: 17;
1479 #endif
1480 
1481 }  REG_FCFI_VAR;
1482 
1483 /* Defines for mam */
1484 #define	EMLXS_REG_FCFI_MAM_SPMA	1	/* Server Provided MAC Address */
1485 #define	EMLXS_REG_FCFI_MAM_FPMA	2	/* Fabric Provided MAC Address */
1486 
1487 /* Structure for MB Command UNREG_FCFI (0xA2) */
1488 /* Good for SLI4 only */
1489 
1490 typedef struct
1491 {
1492 	uint32_t	Rsvd1;
1493 #ifdef EMLXS_BIG_ENDIAN
1494 	uint16_t	Rsvd2;
1495 	uint16_t	FCFI;
1496 #endif
1497 #ifdef EMLXS_LITTLE_ENDIAN
1498 	uint16_t	FCFI;
1499 	uint16_t	Rsvd2;
1500 #endif
1501 }  UNREG_FCFI_VAR;
1502 
1503 /* Structure for MB Command RESUME_RPI (0x9E) */
1504 /* Good for SLI4 only */
1505 
1506 typedef struct
1507 {
1508 #ifdef EMLXS_BIG_ENDIAN
1509 	uint16_t	Rsvd1;
1510 	uint16_t	RPI;
1511 
1512 	uint32_t	EventTag;
1513 	uint32_t	rsvd2[3];
1514 
1515 	uint16_t	VFI;
1516 	uint16_t	VPI;
1517 #endif
1518 #ifdef EMLXS_LITTLE_ENDIAN
1519 	uint16_t	RPI;
1520 	uint16_t	Rsvd1;
1521 
1522 	uint32_t	EventTag;
1523 	uint32_t	rsvd2[3];
1524 
1525 	uint16_t	VPI;
1526 	uint16_t	VFI;
1527 #endif
1528 
1529 }  RESUME_RPI_VAR;
1530 
1531 
1532 /* Structure for MB Command UNREG_D_ID (0x23) */
1533 
1534 typedef struct
1535 {
1536 	uint32_t	did;
1537 
1538 	uint32_t	rsvd2;
1539 	uint32_t	rsvd3;
1540 	uint32_t	rsvd4;
1541 	uint32_t	rsvd5;
1542 #ifdef EMLXS_BIG_ENDIAN
1543 	uint16_t	rsvd6;
1544 	uint16_t	vpi;
1545 #endif
1546 #ifdef EMLXS_LITTLE_ENDIAN
1547 	uint16_t	vpi;
1548 	uint16_t	rsvd6;
1549 #endif
1550 } UNREG_D_ID_VAR;
1551 
1552 
1553 /* Structure for MB Command READ_LA (21) */
1554 /* Structure for MB Command READ_LA64 (0x95) */
1555 
1556 typedef struct
1557 {
1558 	uint32_t	eventTag;	/* Event tag */
1559 #ifdef EMLXS_BIG_ENDIAN
1560 	uint32_t	rsvd2:19;
1561 	uint32_t	fa:1;
1562 	uint32_t	mm:1;
1563 	uint32_t	tc:1;
1564 	uint32_t	pb:1;
1565 	uint32_t	il:1;
1566 	uint32_t	attType:8;
1567 #endif
1568 #ifdef EMLXS_LITTLE_ENDIAN
1569 	uint32_t	attType:8;
1570 	uint32_t	il:1;
1571 	uint32_t	pb:1;
1572 	uint32_t	tc:1;
1573 	uint32_t	mm:1;
1574 	uint32_t	fa:1;
1575 	uint32_t	rsvd2:19;
1576 #endif
1577 #define	AT_RESERVED	0x00	/* Reserved - attType */
1578 #define	AT_LINK_UP	0x01	/* Link is up */
1579 #define	AT_LINK_DOWN	0x02	/* Link is down */
1580 #define	AT_NO_HARD_ALPA	0x03	/* SLI4 */
1581 
1582 #ifdef EMLXS_BIG_ENDIAN
1583 	uint8_t		granted_AL_PA;
1584 	uint8_t		lipAlPs;
1585 	uint8_t		lipType;
1586 	uint8_t		topology;
1587 #endif
1588 #ifdef EMLXS_LITTLE_ENDIAN
1589 	uint8_t		topology;
1590 	uint8_t		lipType;
1591 	uint8_t		lipAlPs;
1592 	uint8_t		granted_AL_PA;
1593 #endif
1594 
1595 	/* lipType */
1596 #define	LT_PORT_INIT	0x00	/* An L_PORT initing (F7, AL_PS) - lipType */
1597 #define	LT_PORT_ERR	0x01	/* Err @L_PORT rcv'er (F8, AL_PS) */
1598 #define	LT_RESET_APORT	0x02	/* Lip Reset of some other port */
1599 #define	LT_RESET_MYPORT	0x03	/* Lip Reset of my port */
1600 
1601 	/* topology */
1602 #define	TOPOLOGY_PT_PT	0x01	/* Topology is pt-pt / pt-fabric */
1603 #define	TOPOLOGY_LOOP	0x02	/* Topology is FC-AL (private) */
1604 
1605 	union
1606 	{
1607 		ULP_BDE		lilpBde;	/* This BDE points to a */
1608 						/* 128 byte buffer to store */
1609 						/* the LILP AL_PA position */
1610 						/* map into */
1611 		ULP_BDE64	lilpBde64;
1612 	} un;
1613 #ifdef EMLXS_BIG_ENDIAN
1614 	uint32_t	Dlu:1;
1615 	uint32_t	Dtf:1;
1616 	uint32_t	Drsvd2:14;
1617 	uint32_t	DlnkSpeed:8;
1618 	uint32_t	DnlPort:4;
1619 	uint32_t	Dtx:2;
1620 	uint32_t	Drx:2;
1621 #endif
1622 #ifdef EMLXS_LITTLE_ENDIAN
1623 	uint32_t	Drx:2;
1624 	uint32_t	Dtx:2;
1625 	uint32_t	DnlPort:4;
1626 	uint32_t	DlnkSpeed:8;
1627 	uint32_t	Drsvd2:14;
1628 	uint32_t	Dtf:1;
1629 	uint32_t	Dlu:1;
1630 #endif
1631 #ifdef EMLXS_BIG_ENDIAN
1632 	uint32_t	Ulu:1;
1633 	uint32_t	Utf:1;
1634 	uint32_t	Ursvd2:14;
1635 	uint32_t	UlnkSpeed:8;
1636 	uint32_t	UnlPort:4;
1637 	uint32_t	Utx:2;
1638 	uint32_t	Urx:2;
1639 #endif
1640 #ifdef EMLXS_LITTLE_ENDIAN
1641 	uint32_t	Urx:2;
1642 	uint32_t	Utx:2;
1643 	uint32_t	UnlPort:4;
1644 	uint32_t	UlnkSpeed:8;
1645 	uint32_t	Ursvd2:14;
1646 	uint32_t	Utf:1;
1647 	uint32_t	Ulu:1;
1648 #endif
1649 #define	LA_1GHZ_LINK   0x04	/* lnkSpeed */
1650 #define	LA_2GHZ_LINK   0x08	/* lnkSpeed */
1651 #define	LA_4GHZ_LINK   0x10	/* lnkSpeed */
1652 #define	LA_8GHZ_LINK   0x20	/* lnkSpeed */
1653 #define	LA_10GHZ_LINK  0x40	/* lnkSpeed */
1654 #define	LA_16GHZ_LINK  0x80	/* lnkSpeed */
1655 #define	LA_32GHZ_LINK  0x90	/* lnkSpeed */
1656 } READ_LA_VAR;
1657 
1658 
1659 /* Structure for MB Command CLEAR_LA (22) */
1660 
1661 typedef struct
1662 {
1663 	uint32_t	eventTag;	/* Event tag */
1664 	uint32_t	rsvd1;
1665 } CLEAR_LA_VAR;
1666 
1667 /* Structure for MB Command DUMP */
1668 /* Good for SLI2/3 only */
1669 
1670 typedef struct
1671 {
1672 #ifdef EMLXS_BIG_ENDIAN
1673 	uint32_t	rsvd:25;
1674 	uint32_t	ra:1;
1675 	uint32_t	co:1;
1676 	uint32_t	cv:1;
1677 	uint32_t	type:4;
1678 
1679 	uint32_t	entry_index:16;
1680 	uint32_t	region_id:16;
1681 #endif
1682 #ifdef EMLXS_LITTLE_ENDIAN
1683 	uint32_t	type:4;
1684 	uint32_t	cv:1;
1685 	uint32_t	co:1;
1686 	uint32_t	ra:1;
1687 	uint32_t	rsvd:25;
1688 
1689 	uint32_t	region_id:16;
1690 	uint32_t	entry_index:16;
1691 #endif
1692 	uint32_t	base_adr;
1693 	uint32_t	word_cnt;
1694 	uint32_t	resp_offset;
1695 } DUMP_VAR;
1696 
1697 /* Structure for MB Command DUMP */
1698 /* Good for SLI4 only */
1699 
1700 typedef struct
1701 {
1702 #ifdef EMLXS_BIG_ENDIAN
1703 	uint32_t	ppi:4;
1704 	uint32_t	phy_index:4;
1705 	uint32_t	rsvd:20;
1706 	uint32_t	type:4;
1707 
1708 	uint32_t	entry_index:16;
1709 	uint32_t	region_id:16;
1710 #endif
1711 #ifdef EMLXS_LITTLE_ENDIAN
1712 	uint32_t	type:4;
1713 	uint32_t	rsvd:20;
1714 	uint32_t	phy_index:4;
1715 	uint32_t	ppi:4;
1716 
1717 	uint32_t	region_id:16;
1718 	uint32_t	entry_index:16;
1719 #endif
1720 	uint32_t	available_cnt;
1721 	uint32_t	addrLow;
1722 	uint32_t	addrHigh;
1723 	uint32_t	rsp_cnt;
1724 } DUMP4_VAR;
1725 
1726 /*
1727  * Dump type
1728  */
1729 #define	DMP_MEM_REG	0x1
1730 #define	DMP_NV_PARAMS	0x2
1731 
1732 /*
1733  * Dump region ID
1734  */
1735 #define	NODE_CFG_A_REGION_ID	0
1736 #define	NODE_CFG_B_REGION_ID	1
1737 #define	NODE_CFG_C_REGION_ID	2
1738 #define	NODE_CFG_D_REGION_ID	3
1739 #define	WAKE_UP_PARMS_REGION_ID	4
1740 #define	DEF_PCI_CFG_REGION_ID	5
1741 #define	PCI_CFG_1_REGION_ID	6
1742 #define	PCI_CFG_2_REGION_ID	7
1743 #define	RSVD1_REGION_ID		8
1744 #define	RSVD2_REGION_ID		9
1745 #define	RSVD3_REGION_ID		10
1746 #define	RSVD4_REGION_ID		11
1747 #define	RSVD5_REGION_ID		12
1748 #define	RSVD6_REGION_ID		13
1749 #define	RSVD7_REGION_ID		14
1750 #define	DIAG_TRACE_REGION_ID	15
1751 #define	WWN_REGION_ID		16
1752 
1753 #define	DMP_VPD_REGION		14
1754 #define	DMP_VPD_SIZE		1024
1755 #define	DMP_VPD_DUMP_WCOUNT	24
1756 
1757 #define	DMP_FCOE_REGION		23
1758 #define	DMP_FCOE_DUMP_WCOUNT	256
1759 
1760 
1761 /* Structure for MB Command UPDATE_CFG */
1762 /* Good for SLI2/3 and SLI4 */
1763 
1764 typedef struct
1765 {
1766 #ifdef EMLXS_BIG_ENDIAN
1767 	uint32_t	rsvd2:16;
1768 	uint32_t	proc_type:8;
1769 	uint32_t	rsvd1:1;
1770 	uint32_t	Abit:1;
1771 	uint32_t	Obit:1;
1772 	uint32_t	Vbit:1;
1773 	uint32_t	req_type:4;
1774 #define	INIT_REGION	1
1775 #define	UPDATE_DATA	2
1776 #define	CLEAN_UP_CFG	3
1777 	uint32_t	entry_len:16;
1778 	uint32_t	region_id:16;
1779 #endif
1780 
1781 #ifdef EMLXS_LITTLE_ENDIAN
1782 	uint32_t	req_type:4;
1783 #define	INIT_REGION	1
1784 #define	UPDATE_DATA	2
1785 #define	CLEAN_UP_CFG	3
1786 	uint32_t	Vbit:1;
1787 	uint32_t	Obit:1;
1788 	uint32_t	Abit:1;
1789 	uint32_t	rsvd1:1;
1790 	uint32_t	proc_type:8;
1791 	uint32_t	rsvd2:16;
1792 
1793 	uint32_t	region_id:16;
1794 	uint32_t	entry_len:16;
1795 #endif
1796 
1797 	uint32_t	rsp_info;
1798 	uint32_t	byte_len;
1799 	uint32_t	cfg_data;
1800 } UPDATE_CFG_VAR;
1801 
1802 /* Structure for MB Command DEL_LD_ENTRY (29) */
1803 
1804 typedef struct
1805 {
1806 #ifdef EMLXS_LITTLE_ENDIAN
1807 	uint32_t	list_req:2;
1808 	uint32_t	list_rsp:2;
1809 	uint32_t	rsvd:28;
1810 #else
1811 	uint32_t	rsvd:28;
1812 	uint32_t	list_rsp:2;
1813 	uint32_t	list_req:2;
1814 #endif
1815 
1816 #define	FLASH_LOAD_LIST	1
1817 #define	RAM_LOAD_LIST	2
1818 #define	BOTH_LISTS	3
1819 
1820 	PROG_ID		prog_id;
1821 } DEL_LD_ENTRY_VAR;
1822 
1823 /* Structure for MB Command LOAD_AREA (81) */
1824 typedef struct
1825 {
1826 #ifdef EMLXS_LITTLE_ENDIAN
1827 	uint32_t	load_cmplt:1;
1828 	uint32_t	method:1;
1829 	uint32_t	rsvd1:1;
1830 	uint32_t	update_flash:1;
1831 	uint32_t	erase_or_prog:1;
1832 	uint32_t	version:1;
1833 	uint32_t	rsvd2:2;
1834 	uint32_t	progress:8;
1835 	uint32_t	step:8;
1836 	uint32_t	area_id:8;
1837 #else
1838 	uint32_t	area_id:8;
1839 	uint32_t	step:8;
1840 	uint32_t	progress:8;
1841 	uint32_t	rsvd2:2;
1842 	uint32_t	version:1;
1843 	uint32_t	erase_or_prog:1;
1844 	uint32_t	update_flash:1;
1845 	uint32_t	rsvd1:1;
1846 	uint32_t	method:1;
1847 	uint32_t	load_cmplt:1;
1848 #endif
1849 	uint32_t	dl_to_adr;
1850 	uint32_t	dl_len;
1851 	union
1852 	{
1853 		uint32_t	dl_from_slim_offset;
1854 		ULP_BDE		dl_from_bde;
1855 		ULP_BDE64	dl_from_bde64;
1856 		PROG_ID		prog_id;
1857 	} un;
1858 } LOAD_AREA_VAR;
1859 
1860 /* Structure for MB Command LOAD_EXP_ROM (9C) */
1861 typedef struct
1862 {
1863 #ifdef EMLXS_LITTLE_ENDIAN
1864 	uint32_t	rsvd1:8;
1865 	uint32_t	progress:8;
1866 	uint32_t	step:8;
1867 	uint32_t	rsvd2:8;
1868 #else
1869 	uint32_t	rsvd2:8;
1870 	uint32_t	step:8;
1871 	uint32_t	progress:8;
1872 	uint32_t	rsvd1:8;
1873 #endif
1874 	uint32_t	dl_to_adr;
1875 	uint32_t	rsvd3;
1876 	union
1877 	{
1878 		uint32_t	word[2];
1879 		PROG_ID		prog_id;
1880 	} un;
1881 } LOAD_EXP_ROM_VAR;
1882 
1883 
1884 /* Structure for MB Command CONFIG_HBQ (7C) */
1885 
1886 typedef struct
1887 {
1888 #ifdef EMLXS_BIG_ENDIAN
1889 	uint32_t	rsvd1:7;
1890 	uint32_t	recvNotify:1;	/* Receive Notification */
1891 	uint32_t	numMask:8;	/* # Mask Entries */
1892 	uint32_t	profile:8;	/* Selection Profile */
1893 	uint32_t	rsvd2:8;
1894 #endif
1895 #ifdef EMLXS_LITTLE_ENDIAN
1896 	uint32_t	rsvd2:8;
1897 	uint32_t	profile:8;	/* Selection Profile */
1898 	uint32_t	numMask:8;	/* # Mask Entries */
1899 	uint32_t	recvNotify:1;	/* Receive Notification */
1900 	uint32_t	rsvd1:7;
1901 #endif
1902 
1903 #ifdef EMLXS_BIG_ENDIAN
1904 	uint32_t	hbqId:16;
1905 	uint32_t	rsvd3:12;
1906 	uint32_t	ringMask:4;
1907 #endif
1908 #ifdef EMLXS_LITTLE_ENDIAN
1909 	uint32_t	ringMask:4;
1910 	uint32_t	rsvd3:12;
1911 	uint32_t	hbqId:16;
1912 #endif
1913 
1914 #ifdef EMLXS_BIG_ENDIAN
1915 	uint32_t	numEntries:16;
1916 	uint32_t	rsvd4:8;
1917 	uint32_t	headerLen:8;
1918 #endif
1919 #ifdef EMLXS_LITTLE_ENDIAN
1920 	uint32_t	headerLen:8;
1921 	uint32_t	rsvd4:8;
1922 	uint32_t	numEntries:16;
1923 #endif
1924 
1925 	uint32_t	hbqaddrLow;
1926 	uint32_t	hbqaddrHigh;
1927 
1928 #ifdef EMLXS_BIG_ENDIAN
1929 	uint32_t	rsvd5:31;
1930 	uint32_t	logEntry:1;
1931 #endif
1932 #ifdef EMLXS_LITTLE_ENDIAN
1933 	uint32_t	logEntry:1;
1934 	uint32_t	rsvd5:31;
1935 #endif
1936 
1937 	uint32_t	rsvd6;	/* w7 */
1938 	uint32_t	rsvd7;	/* w8 */
1939 	uint32_t	rsvd8;	/* w9 */
1940 
1941 	HBQ_MASK	hbqMasks[6];
1942 
1943 	union
1944 	{
1945 		uint32_t	allprofiles[12];
1946 
1947 		struct
1948 		{
1949 #ifdef EMLXS_BIG_ENDIAN
1950 			uint32_t	seqlenoff:16;
1951 			uint32_t	maxlen:16;
1952 #endif
1953 #ifdef EMLXS_LITTLE_ENDIAN
1954 			uint32_t	maxlen:16;
1955 			uint32_t	seqlenoff:16;
1956 #endif
1957 #ifdef EMLXS_BIG_ENDIAN
1958 			uint32_t	rsvd1:28;
1959 			uint32_t	seqlenbcnt:4;
1960 #endif
1961 #ifdef EMLXS_LITTLE_ENDIAN
1962 			uint32_t	seqlenbcnt:4;
1963 			uint32_t	rsvd1:28;
1964 #endif
1965 			uint32_t	rsvd[10];
1966 		} profile2;
1967 
1968 		struct
1969 		{
1970 #ifdef EMLXS_BIG_ENDIAN
1971 			uint32_t	seqlenoff:16;
1972 			uint32_t	maxlen:16;
1973 #endif
1974 #ifdef EMLXS_LITTLE_ENDIAN
1975 			uint32_t	maxlen:16;
1976 			uint32_t	seqlenoff:16;
1977 #endif
1978 #ifdef EMLXS_BIG_ENDIAN
1979 			uint32_t	cmdcodeoff:28;
1980 			uint32_t	rsvd1:12;
1981 			uint32_t	seqlenbcnt:4;
1982 #endif
1983 #ifdef EMLXS_LITTLE_ENDIAN
1984 			uint32_t	seqlenbcnt:4;
1985 			uint32_t	rsvd1:12;
1986 			uint32_t	cmdcodeoff:28;
1987 #endif
1988 			uint32_t	cmdmatch[8];
1989 
1990 			uint32_t	rsvd[2];
1991 		} profile3;
1992 
1993 		struct
1994 		{
1995 #ifdef EMLXS_BIG_ENDIAN
1996 			uint32_t	seqlenoff:16;
1997 			uint32_t	maxlen:16;
1998 #endif
1999 #ifdef EMLXS_LITTLE_ENDIAN
2000 			uint32_t	maxlen:16;
2001 			uint32_t	seqlenoff:16;
2002 #endif
2003 #ifdef EMLXS_BIG_ENDIAN
2004 			uint32_t	cmdcodeoff:28;
2005 			uint32_t	rsvd1:12;
2006 			uint32_t	seqlenbcnt:4;
2007 #endif
2008 #ifdef EMLXS_LITTLE_ENDIAN
2009 			uint32_t	seqlenbcnt:4;
2010 			uint32_t	rsvd1:12;
2011 			uint32_t	cmdcodeoff:28;
2012 #endif
2013 			uint32_t	cmdmatch[8];
2014 
2015 			uint32_t	rsvd[2];
2016 		} profile5;
2017 	} profiles;
2018 } CONFIG_HBQ_VAR;
2019 
2020 
2021 /* Structure for MB Command REG_VPI(0x96) */
2022 /* Good for SLI2/3 and SLI4 */
2023 
2024 typedef struct
2025 {
2026 #ifdef EMLXS_BIG_ENDIAN
2027 	uint32_t	rsvd1;
2028 	uint32_t	rsvd2:7;
2029 	uint32_t	upd:1;
2030 	uint32_t	sid:24;
2031 	uint32_t	portname[2];    /* N_PORT name */
2032 	uint32_t	rsvd5;
2033 	uint16_t	vfi;
2034 	uint16_t	vpi;
2035 #endif
2036 #ifdef EMLXS_LITTLE_ENDIAN
2037 	uint32_t	rsvd1;
2038 	uint32_t	sid:24;
2039 	uint32_t	upd:1;
2040 	uint32_t	rsvd2:7;
2041 	uint32_t	portname[2];    /* N_PORT name */
2042 	uint32_t	rsvd5;
2043 	uint16_t	vpi;
2044 	uint16_t	vfi;
2045 #endif
2046 } REG_VPI_VAR;
2047 
2048 /* Structure for MB Command INIT_VPI(0xA3) */
2049 /* Good for SLI4 only */
2050 
2051 typedef struct
2052 {
2053 #ifdef EMLXS_BIG_ENDIAN
2054 	uint16_t	vfi;
2055 	uint16_t	vpi;
2056 #endif
2057 #ifdef EMLXS_LITTLE_ENDIAN
2058 	uint16_t	vpi;
2059 	uint16_t	vfi;
2060 #endif
2061 } INIT_VPI_VAR;
2062 
2063 /* Structure for MB Command UNREG_VPI (0x97) */
2064 /* Good for SLI2/3 */
2065 
2066 typedef struct
2067 {
2068 	uint32_t	rsvd1;
2069 	uint32_t	rsvd2;
2070 	uint32_t	rsvd3;
2071 	uint32_t	rsvd4;
2072 	uint32_t	rsvd5;
2073 #ifdef EMLXS_BIG_ENDIAN
2074 	uint16_t	rsvd6;
2075 	uint16_t	vpi;
2076 #endif
2077 #ifdef EMLXS_LITTLE_ENDIAN
2078 	uint16_t	vpi;
2079 	uint16_t	rsvd6;
2080 #endif
2081 } UNREG_VPI_VAR;
2082 
2083 /* Structure for MB Command UNREG_VPI (0x97) */
2084 /* Good for SLI4 */
2085 
2086 typedef struct
2087 {
2088 	uint32_t	rsvd1;
2089 #ifdef EMLXS_BIG_ENDIAN
2090 	uint8_t		ii:2;
2091 	uint16_t	rsvd2:14;
2092 	uint16_t	index;
2093 #endif
2094 #ifdef EMLXS_LITTLE_ENDIAN
2095 	uint16_t	index;
2096 	uint16_t	rsvd2:14;
2097 	uint8_t		ii:2;
2098 #endif
2099 } UNREG_VPI_VAR4;
2100 
2101 /* Structure for MB Command REG_VFI(0x9F) */
2102 /* Good for SLI4 only */
2103 
2104 typedef struct
2105 {
2106 #ifdef EMLXS_BIG_ENDIAN
2107 	uint16_t	rsvd1:2;	/* Word 1 */
2108 	uint16_t	upd:1;
2109 	uint16_t	vp:1;
2110 	uint16_t	rsvd2:12;
2111 	uint16_t	vfi;
2112 	uint16_t	vpi;		/* Word 2 */
2113 	uint16_t	fcfi;
2114 
2115 	uint32_t	portname[2];    /* N_PORT name */
2116 
2117 	ULP_BDE64	bde;
2118 
2119 /* CHANGE with next firmware drop */
2120 	uint32_t	edtov;
2121 	uint32_t	ratov;
2122 
2123 	uint32_t	vfi_bbscn:4;
2124 	uint32_t	vfi_bbcr:1;
2125 	uint32_t	rsvd5:3;	/* Word 10 */
2126 	uint32_t	sid:24;
2127 #endif
2128 #ifdef EMLXS_LITTLE_ENDIAN
2129 	uint16_t	vfi;
2130 	uint16_t	rsvd2:12;
2131 	uint16_t	vp:1;
2132 	uint16_t	upd:1;
2133 	uint16_t	rsvd1:2;
2134 	uint16_t	fcfi;
2135 	uint16_t	vpi;
2136 
2137 	uint32_t	portname[2];    /* N_PORT name */
2138 
2139 	ULP_BDE64	bde;
2140 
2141 /* CHANGE with next firmware drop */
2142 	uint32_t	edtov;
2143 	uint32_t	ratov;
2144 
2145 	uint32_t	sid:24;		/* nport_id */
2146 	uint32_t	rsvd5:3;
2147 	uint32_t	vfi_bbcr:1;
2148 	uint32_t	vfi_bbscn:4;
2149 #endif
2150 } REG_VFI_VAR;
2151 
2152 /* Structure for MB Command INIT_VFI(0xA4) */
2153 /* Good for SLI4 only */
2154 
2155 typedef struct
2156 {
2157 #ifdef EMLXS_BIG_ENDIAN
2158 	uint32_t	vr:1;
2159 	uint32_t	vt:1;
2160 	uint32_t	vf:1;
2161 	uint32_t	rsvd1:13;
2162 	uint32_t	vfi:16;
2163 
2164 	uint16_t	rsvd2;
2165 	uint16_t	fcfi;
2166 
2167 	uint32_t	rsvd3:16;
2168 	uint32_t	pri:3;
2169 	uint32_t	vf_id:12;
2170 	uint32_t	rsvd4:1;
2171 
2172 	uint32_t	hop_count:8;
2173 	uint32_t	rsvd5:24;
2174 #endif
2175 #ifdef EMLXS_LITTLE_ENDIAN
2176 	uint32_t	vfi:16;
2177 	uint32_t	rsvd1:13;
2178 	uint32_t	vf:1;
2179 	uint32_t	vt:1;
2180 	uint32_t	vr:1;
2181 
2182 	uint16_t	fcfi;
2183 	uint16_t	rsvd2;
2184 
2185 	uint32_t	rsvd4:1;
2186 	uint32_t	vf_id:12;
2187 	uint32_t	pri:3;
2188 	uint32_t	rsvd3:16;
2189 
2190 	uint32_t	rsvd5:24;
2191 	uint32_t	hop_count:8;
2192 #endif
2193 } INIT_VFI_VAR;
2194 
2195 /* Structure for MB Command UNREG_VFI (0xA1) */
2196 /* Good for SLI4 only */
2197 
2198 typedef struct
2199 {
2200 #ifdef EMLXS_BIG_ENDIAN
2201 	uint32_t	rsvd1:3;
2202 	uint32_t	vp:1;
2203 	uint32_t	rsvd2:28;
2204 
2205 	uint16_t	vpi;
2206 	uint16_t	vfi;
2207 #endif
2208 #ifdef EMLXS_LITTLE_ENDIAN
2209 	uint32_t	rsvd2:28;
2210 	uint32_t	vp:1;
2211 	uint32_t	rsvd1:3;
2212 
2213 	uint16_t	vfi;
2214 	uint16_t	vpi;
2215 #endif
2216 } UNREG_VFI_VAR;
2217 
2218 
2219 
2220 typedef struct
2221 {
2222 #ifdef EMLXS_BIG_ENDIAN
2223 	uint32_t	read_log:1;
2224 	uint32_t	clear_log:1;
2225 	uint32_t	mbox_rsp:1;
2226 	uint32_t	resv:28;
2227 #endif
2228 #ifdef EMLXS_LITTLE_ENDIAN
2229 	uint32_t	resv:28;
2230 	uint32_t	mbox_rsp:1;
2231 	uint32_t	clear_log:1;
2232 	uint32_t	read_log:1;
2233 #endif
2234 
2235 	uint32_t	offset;
2236 
2237 	union
2238 	{
2239 		ULP_BDE		sp;
2240 		ULP_BDE64	sp64;
2241 	} un;
2242 } READ_EVT_LOG_VAR;
2243 
2244 typedef struct
2245 {
2246 
2247 #ifdef EMLXS_BIG_ENDIAN
2248 	uint16_t	split_log_next;
2249 	uint16_t	log_next;
2250 
2251 	uint32_t	size;
2252 
2253 	uint32_t	format:8;
2254 	uint32_t	resv2:22;
2255 	uint32_t	log_level:1;
2256 	uint32_t	split_log:1;
2257 #endif
2258 #ifdef EMLXS_LITTLE_ENDIAN
2259 	uint16_t	log_next;
2260 	uint16_t	split_log_next;
2261 
2262 	uint32_t	size;
2263 
2264 	uint32_t	split_log:1;
2265 	uint32_t	log_level:1;
2266 	uint32_t	resv2:22;
2267 	uint32_t	format:8;
2268 #endif
2269 
2270 	uint32_t	offset;
2271 } LOG_STATUS_VAR;
2272 
2273 
2274 /* Structure for MB Command CONFIG_PORT (0x88) */
2275 typedef struct
2276 {
2277 #ifdef EMLXS_BIG_ENDIAN
2278 	uint32_t	cBE:1;
2279 	uint32_t	cET:1;
2280 	uint32_t	cHpcb:1;
2281 	uint32_t	rMA:1;
2282 	uint32_t	sli_mode:4;
2283 	uint32_t	pcbLen:24;	/* bit 23:0 of memory based port */
2284 					/* config block */
2285 #endif
2286 #ifdef EMLXS_LITTLE_ENDIAN
2287 	uint32_t	pcbLen:24;	/* bit 23:0 of memory based port */
2288 					/* config block */
2289 	uint32_t	sli_mode:4;
2290 	uint32_t	rMA:1;
2291 	uint32_t	cHpcb:1;
2292 	uint32_t	cET:1;
2293 	uint32_t	cBE:1;
2294 #endif
2295 
2296 	uint32_t	pcbLow;		/* bit 31:0 of memory based port */
2297 					/* config block */
2298 	uint32_t	pcbHigh; 	/* bit 63:32 of memory based port */
2299 					/* config block */
2300 	uint32_t	hbainit[5];
2301 
2302 #ifdef EMLXS_BIG_ENDIAN
2303 	uint32_t	hps:1; /* Host pointers in SLIM */
2304 	uint32_t	rsvd:31;
2305 #endif
2306 #ifdef EMLXS_LITTLE_ENDIAN
2307 	uint32_t	rsvd:31;
2308 	uint32_t	hps:1; /* Host pointers in SLIM */
2309 #endif
2310 
2311 #ifdef EMLXS_BIG_ENDIAN
2312 	uint32_t	rsvd1:24;
2313 	uint32_t	cmv:1;		/* Configure Max VPIs */
2314 	uint32_t	ccrp:1;		/* Config Command Ring Polling */
2315 	uint32_t	csah:1;		/* Configure Synchronous Abort */
2316 					/* Handling */
2317 	uint32_t	chbs:1;		/* Cofigure Host Backing store */
2318 	uint32_t	cinb:1;		/* Enable Interrupt Notification */
2319 					/* Block */
2320 	uint32_t	cerbm:1;	/* Configure Enhanced Receive */
2321 					/* Buffer Management */
2322 	uint32_t	cmx:1;		/* Configure Max XRIs */
2323 	uint32_t	cmr:1;		/* Configure Max RPIs */
2324 #endif
2325 #ifdef EMLXS_LITTLE_ENDIAN
2326 	uint32_t	cmr:1;		/* Configure Max RPIs */
2327 	uint32_t	cmx:1;		/* Configure Max XRIs */
2328 	uint32_t	cerbm:1;	/* Configure Enhanced Receive */
2329 					/* Buffer Management */
2330 	uint32_t	cinb:1;		/* Enable Interrupt Notification */
2331 					/* Block */
2332 	uint32_t	chbs:1;		/* Cofigure Host Backing store */
2333 	uint32_t	csah:1;		/* Configure Synchronous Abort */
2334 					/* Handling */
2335 	uint32_t	ccrp:1;		/* Config Command Ring Polling */
2336 	uint32_t	cmv:1;		/* Configure Max VPIs */
2337 	uint32_t	rsvd1:24;
2338 #endif
2339 #ifdef EMLXS_BIG_ENDIAN
2340 	uint32_t	rsvd2:19;	/* Reserved */
2341 	uint32_t	gdss:1;		/* Configure Data Security SLI */
2342 	uint32_t	rsvd3:3;	/* Reserved */
2343 	uint32_t	gbg:1;		/* Grant BlockGuard */
2344 	uint32_t	gmv:1;		/* Grant Max VPIs */
2345 	uint32_t	gcrp:1;		/* Grant Command Ring Polling */
2346 	uint32_t	gsah:1;		/* Grant Synchronous Abort Handling */
2347 	uint32_t	ghbs:1;		/* Grant Host Backing Store */
2348 	uint32_t	ginb:1;		/* Grant Interrupt Notification Block */
2349 	uint32_t	gerbm:1;	/* Grant ERBM Request */
2350 	uint32_t	gmx:1;		/* Grant Max XRIs */
2351 	uint32_t	gmr:1;		/* Grant Max RPIs */
2352 #endif
2353 #ifdef EMLXS_LITTLE_ENDIAN
2354 	uint32_t	gmr:1;		/* Grant Max RPIs */
2355 	uint32_t	gmx:1;		/* Grant Max XRIs */
2356 	uint32_t	gerbm:1;	/* Grant ERBM Request */
2357 	uint32_t	ginb:1;		/* Grant Interrupt Notification Block */
2358 	uint32_t	ghbs:1;		/* Grant Host Backing Store */
2359 	uint32_t	gsah:1;		/* Grant Synchronous Abort Handling */
2360 	uint32_t	gcrp:1;		/* Grant Command Ring Polling */
2361 	uint32_t	gmv:1;		/* Grant Max VPIs */
2362 	uint32_t	gbg:1;		/* Grant BlockGuard */
2363 	uint32_t	rsvd3:3;	/* Reserved */
2364 	uint32_t	gdss:1;		/* Configure Data Security SLI */
2365 	uint32_t	rsvd2:19;	/* Reserved */
2366 #endif
2367 
2368 #ifdef EMLXS_BIG_ENDIAN
2369 	uint32_t	max_rpi:16;	/* Max RPIs Port should configure */
2370 	uint32_t	max_xri:16;	/* Max XRIs Port should configure */
2371 #endif
2372 #ifdef EMLXS_LITTLE_ENDIAN
2373 	uint32_t	max_xri:16;	/* Max XRIs Port should configure */
2374 	uint32_t	max_rpi:16;	/* Max RPIs Port should configure */
2375 #endif
2376 
2377 #ifdef EMLXS_BIG_ENDIAN
2378 	uint32_t	max_hbq:16;	/* Max HBQs Host expect to configure */
2379 	uint32_t	rsvd4:16;	/* Max HBQs Host expect to configure */
2380 #endif
2381 #ifdef EMLXS_LITTLE_ENDIAN
2382 	uint32_t	rsvd4:16;	/* Max HBQs Host expect to configure */
2383 	uint32_t	max_hbq:16;	/* Max HBQs Host expect to configure */
2384 #endif
2385 
2386 	uint32_t	rsvd5;		/* Reserved */
2387 
2388 #ifdef EMLXS_BIG_ENDIAN
2389 	uint32_t	rsvd6:16;	/* Reserved */
2390 	uint32_t	vpi_max:16;	/* Max number of virt N-Ports */
2391 #endif
2392 #ifdef EMLXS_LITTLE_ENDIAN
2393 	uint32_t	vpi_max:16;	/* Max number of virt N-Ports */
2394 	uint32_t	rsvd6:16;	/* Reserved */
2395 #endif
2396 } CONFIG_PORT_VAR;
2397 
2398 /* Structure for MB Command REQUEST_FEATURES (0x9D) */
2399 /* Good for SLI4 only */
2400 
2401 typedef struct
2402 {
2403 #ifdef EMLXS_BIG_ENDIAN
2404 	uint32_t	rsvd1:31;
2405 	uint32_t	QueryMode:1;
2406 #endif
2407 #ifdef EMLXS_LITTLE_ENDIAN
2408 	uint32_t	QueryMode:1;
2409 	uint32_t	rsvd1:31;
2410 #endif
2411 
2412 	uint32_t	featuresRequested;
2413 	uint32_t	featuresEnabled;
2414 
2415 } REQUEST_FEATURES_VAR;
2416 
2417 #define	SLI4_FEATURE_INHIBIT_AUTO_ABTS		0x0001
2418 #define	SLI4_FEATURE_NPIV			0x0002
2419 #define	SLI4_FEATURE_DIF			0x0004
2420 #define	SLI4_FEATURE_VIRTUAL_FABRICS		0x0008
2421 #define	SLI4_FEATURE_FCP_INITIATOR		0x0010
2422 #define	SLI4_FEATURE_FCP_TARGET			0x0020
2423 #define	SLI4_FEATURE_FCP_COMBO			0x0040
2424 #define	SLI4_FEATURE_RSVD1			0x0080
2425 #define	SLI4_FEATURE_RQD			0x0100
2426 #define	SLI4_FEATURE_INHIBIT_AUTO_ABTS_R	0x0200
2427 #define	SLI4_FEATURE_HIGH_LOGIN_MODE		0x0400
2428 #define	SLI4_FEATURE_PERF_HINT			0x0800
2429 
2430 
2431 /* SLI-2 Port Control Block */
2432 
2433 /* SLIM POINTER */
2434 #define	SLIMOFF	0x30	/* WORD */
2435 
2436 typedef struct _SLI2_RDSC
2437 {
2438 	uint32_t	cmdEntries;
2439 	uint32_t	cmdAddrLow;
2440 	uint32_t	cmdAddrHigh;
2441 
2442 	uint32_t	rspEntries;
2443 	uint32_t	rspAddrLow;
2444 	uint32_t	rspAddrHigh;
2445 } SLI2_RDSC;
2446 
2447 typedef struct _PCB
2448 {
2449 #ifdef EMLXS_BIG_ENDIAN
2450 	uint32_t	type:8;
2451 #define	TYPE_NATIVE_SLI2	0x01;
2452 	uint32_t	feature:8;
2453 #define	FEATURE_INITIAL_SLI2	0x01;
2454 	uint32_t	rsvd:12;
2455 	uint32_t	maxRing:4;
2456 #endif
2457 #ifdef EMLXS_LITTLE_ENDIAN
2458 	uint32_t	maxRing:4;
2459 	uint32_t	rsvd:12;
2460 	uint32_t	feature:8;
2461 #define	FEATURE_INITIAL_SLI2	0x01;
2462 	uint32_t	type:8;
2463 #define	TYPE_NATIVE_SLI2	0x01;
2464 #endif
2465 
2466 	uint32_t	mailBoxSize;
2467 	uint32_t	mbAddrLow;
2468 	uint32_t	mbAddrHigh;
2469 
2470 	uint32_t	hgpAddrLow;
2471 	uint32_t	hgpAddrHigh;
2472 
2473 	uint32_t	pgpAddrLow;
2474 	uint32_t	pgpAddrHigh;
2475 	SLI2_RDSC	rdsc[MAX_RINGS_AVAILABLE];
2476 } PCB;
2477 
2478 /* NEW_FEATURE */
2479 typedef struct
2480 {
2481 #ifdef EMLXS_BIG_ENDIAN
2482 	uint32_t	rsvd0:27;
2483 	uint32_t	discardFarp:1;
2484 	uint32_t	IPEnable:1;
2485 	uint32_t	nodeName:1;
2486 	uint32_t	portName:1;
2487 	uint32_t	filterEnable:1;
2488 #endif
2489 #ifdef EMLXS_LITTLE_ENDIAN
2490 	uint32_t	filterEnable:1;
2491 	uint32_t	portName:1;
2492 	uint32_t	nodeName:1;
2493 	uint32_t	IPEnable:1;
2494 	uint32_t	discardFarp:1;
2495 	uint32_t	rsvd:27;
2496 #endif
2497 	NAME_TYPE	portname;
2498 	NAME_TYPE	nodename;
2499 	uint32_t	rsvd1;
2500 	uint32_t	rsvd2;
2501 	uint32_t	rsvd3;
2502 	uint32_t	IPAddress;
2503 } CONFIG_FARP_VAR;
2504 
2505 
2506 /* NEW_FEATURE */
2507 typedef struct
2508 {
2509 #ifdef EMLXS_BIG_ENDIAN
2510 	uint32_t	defaultMessageNumber:16;
2511 	uint32_t	rsvd1:3;
2512 	uint32_t	nid:5;
2513 	uint32_t	rsvd2:5;
2514 	uint32_t	defaultPresent:1;
2515 	uint32_t	addAssociations:1;
2516 	uint32_t	reportAssociations:1;
2517 #endif
2518 #ifdef EMLXS_LITTLE_ENDIAN
2519 	uint32_t	reportAssociations:1;
2520 	uint32_t	addAssociations:1;
2521 	uint32_t	defaultPresent:1;
2522 	uint32_t	rsvd2:5;
2523 	uint32_t	nid:5;
2524 	uint32_t	rsvd1:3;
2525 	uint32_t	defaultMessageNumber:16;
2526 #endif
2527 	uint32_t	attConditions;
2528 	uint8_t		attentionId[16];
2529 	uint16_t	messageNumberByHA[32];
2530 	uint16_t	messageNumberByID[16];
2531 	uint32_t	rsvd3;
2532 } CONFIG_MSI_VAR;
2533 
2534 
2535 /* NEW_FEATURE */
2536 typedef struct
2537 {
2538 #ifdef EMLXS_BIG_ENDIAN
2539 	uint32_t	defaultMessageNumber:8;
2540 	uint32_t	rsvd1:11;
2541 	uint32_t	nid:5;
2542 	uint32_t	rsvd2:5;
2543 	uint32_t	defaultPresent:1;
2544 	uint32_t	addAssociations:1;
2545 	uint32_t	reportAssociations:1;
2546 #endif
2547 #ifdef EMLXS_LITTLE_ENDIAN
2548 	uint32_t	reportAssociations:1;
2549 	uint32_t	addAssociations:1;
2550 	uint32_t	defaultPresent:1;
2551 	uint32_t	rsvd2:5;
2552 	uint32_t	nid:5;
2553 	uint32_t	rsvd1:11;
2554 	uint32_t	defaultMessageNumber:8;
2555 #endif
2556 	uint32_t	attConditions1;
2557 	uint32_t	attConditions2;
2558 	uint8_t		attentionId[16];
2559 	uint8_t		messageNumberByHA[64];
2560 	uint8_t		messageNumberByID[16];
2561 	uint32_t	autoClearByHA1;
2562 	uint32_t	autoClearByHA2;
2563 	uint32_t	autoClearByID;
2564 	uint32_t	resv3;
2565 } CONFIG_MSIX_VAR;
2566 
2567 
2568 /* Union of all Mailbox Command types */
2569 
2570 typedef union
2571 {
2572 	uint32_t		varWords[31];
2573 	LOAD_SM_VAR		varLdSM;	/* cmd =  1 (LOAD_SM) */
2574 	READ_NV_VAR		varRDnvp;	/* cmd =  2 (READ_NVPARMS) */
2575 	WRITE_NV_VAR		varWTnvp;	/* cmd =  3 (WRITE_NVPARMS) */
2576 	BIU_DIAG_VAR		varBIUdiag;	/* cmd =  4 (RUN_BIU_DIAG) */
2577 	INIT_LINK_VAR		varInitLnk;	/* cmd =  5 (INIT_LINK) */
2578 	DOWN_LINK_VAR		varDwnLnk;	/* cmd =  6 (DOWN_LINK) */
2579 	CONFIG_LINK		varCfgLnk;	/* cmd =  7 (CONFIG_LINK) */
2580 	PART_SLIM_VAR		varSlim;	/* cmd =  8 (PART_SLIM) */
2581 	CONFIG_RING_VAR		varCfgRing;	/* cmd =  9 (CONFIG_RING) */
2582 	RESET_RING_VAR		varRstRing;	/* cmd = 10 (RESET_RING) */
2583 	READ_CONFIG_VAR		varRdConfig;	/* cmd = 11 (READ_CONFIG) */
2584 	READ_RCONF_VAR		varRdRConfig;	/* cmd = 12 (READ_RCONFIG) */
2585 	READ_SPARM_VAR		varRdSparm;	/* cmd = 13 (READ_SPARM(64)) */
2586 	READ_STATUS_VAR		varRdStatus;	/* cmd = 14 (READ_STATUS) */
2587 	READ_RPI_VAR		varRdRPI;	/* cmd = 15 (READ_RPI(64)) */
2588 	READ_XRI_VAR		varRdXRI;	/* cmd = 16 (READ_XRI) */
2589 	READ_REV_VAR		varRdRev;	/* cmd = 17 (READ_REV) */
2590 	READ_LNK_VAR		varRdLnk;	/* cmd = 18 (READ_LNK_STAT) */
2591 	REG_LOGIN_VAR		varRegLogin;	/* cmd = 19 (REG_LOGIN(64)) */
2592 	UNREG_LOGIN_VAR		varUnregLogin;	/* cmd = 20 (UNREG_LOGIN) */
2593 	READ_LA_VAR		varReadLA;	/* cmd = 21 (READ_LA(64)) */
2594 	CLEAR_LA_VAR		varClearLA;	/* cmd = 22 (CLEAR_LA) */
2595 	DUMP_VAR		varDmp;		/* Warm Start DUMP mbx cmd */
2596 	UPDATE_CFG_VAR		varUpdateCfg;	/* cmd = 0x1b Warm Start */
2597 						/* UPDATE_CFG cmd */
2598 	DEL_LD_ENTRY_VAR	varDelLdEntry;	/* cmd = 0x1d (DEL_LD_ENTRY) */
2599 	UNREG_D_ID_VAR		varUnregDID;	/* cmd = 0x23 (UNREG_D_ID) */
2600 	CONFIG_FARP_VAR		varCfgFarp;	/* cmd = 0x25 (CONFIG_FARP) */
2601 	CONFIG_MSI_VAR		varCfgMSI;	/* cmd = 0x90 (CONFIG_MSI) */
2602 	CONFIG_MSIX_VAR		varCfgMSIX;	/* cmd = 0x30 (CONFIG_MSIX) */
2603 	CONFIG_HBQ_VAR		varCfgHbq;	/* cmd = 0x7C (CONFIG_HBQ) */
2604 	LOAD_AREA_VAR		varLdArea;	/* cmd = 0x81 (LOAD_AREA) */
2605 	CONFIG_PORT_VAR		varCfgPort;	/* cmd = 0x88 (CONFIG_PORT) */
2606 	LOAD_EXP_ROM_VAR	varLdExpRom;	/* cmd = 0x9C (LOAD_XP_ROM) */
2607 	REG_VPI_VAR		varRegVpi;	/* cmd = 0x96 (REG_VPI) */
2608 	UNREG_VPI_VAR		varUnregVpi;	/* cmd = 0x97 (UNREG_VPI) */
2609 	READ_EVT_LOG_VAR	varRdEvtLog;	/* cmd = 0x38 (READ_EVT_LOG) */
2610 	LOG_STATUS_VAR		varLogStat;	/* cmd = 0x37 */
2611 
2612 } MAILVARIANTS;
2613 
2614 #define	MAILBOX_CMD_BSIZE	128
2615 #define	MAILBOX_CMD_WSIZE	32
2616 
2617 /*
2618  * SLI-2 specific structures
2619  */
2620 
2621 typedef struct _SLI1_DESC
2622 {
2623 	emlxs_rings_t	mbxCring[4];
2624 	uint32_t	mbxUnused[24];
2625 } SLI1_DESC; /* 128 bytes */
2626 
2627 typedef struct
2628 {
2629 	uint32_t	cmdPutInx;
2630 	uint32_t	rspGetInx;
2631 } HGP;
2632 
2633 typedef struct
2634 {
2635 	uint32_t	cmdGetInx;
2636 	uint32_t	rspPutInx;
2637 } PGP;
2638 
2639 typedef struct _SLI2_DESC
2640 {
2641 	HGP		host[4];
2642 	PGP		port[4];
2643 	uint32_t	HBQ_PortGetIdx[16];
2644 } SLI2_DESC; /* 128 bytes */
2645 
2646 typedef union
2647 {
2648 	SLI1_DESC	s1;	/* 32 words, 128 bytes */
2649 	SLI2_DESC	s2;	/* 32 words, 128 bytes */
2650 } SLI_VAR;
2651 
2652 typedef volatile struct
2653 {
2654 #ifdef EMLXS_BIG_ENDIAN
2655 	uint16_t	mbxStatus;
2656 	uint8_t		mbxCommand;
2657 	uint8_t		mbxReserved:6;
2658 	uint8_t		mbxHc:1;
2659 	uint8_t		mbxOwner:1;	/* Low order bit first word */
2660 #endif
2661 #ifdef EMLXS_LITTLE_ENDIAN
2662 	uint8_t		mbxOwner:1;	/* Low order bit first word */
2663 	uint8_t		mbxHc:1;
2664 	uint8_t		mbxReserved:6;
2665 	uint8_t		mbxCommand;
2666 	uint16_t	mbxStatus;
2667 #endif
2668 	MAILVARIANTS	un;		/* 124 bytes */
2669 	SLI_VAR		us;		/* 128 bytes */
2670 } MAILBOX;				/* 256 bytes */
2671 
2672 
2673 
2674 /* SLI4 IOCTL Mailbox */
2675 /* ALL SLI4 specific mbox commands have a standard request /response header */
2676 /* Word 0 is just like SLI 3 */
2677 
2678 typedef struct mbox_req_hdr
2679 {
2680 #ifdef EMLXS_BIG_ENDIAN
2681 	uint32_t	domain:8;		/* word 6 */
2682 	uint32_t	port:8;
2683 	uint32_t	subsystem:8;
2684 	uint32_t	opcode:8;
2685 
2686 	uint32_t	timeout;		/* word 7 */
2687 
2688 	uint32_t	req_length;		/* word 8 */
2689 
2690 	uint32_t	reserved1:24;		/* word 9 */
2691 	uint32_t	version:8;		/* word 9 */
2692 #endif
2693 #ifdef EMLXS_LITTLE_ENDIAN
2694 	uint32_t	opcode:8;
2695 	uint32_t	subsystem:8;
2696 	uint32_t	port:8;
2697 	uint32_t	domain:8;		/* word 6 */
2698 
2699 	uint32_t	timeout;		/* word 7 */
2700 
2701 	uint32_t	req_length;		/* word 8 */
2702 
2703 	uint32_t	version:8;		/* word 9 */
2704 	uint32_t	reserved1:24;		/* word 9 */
2705 #endif
2706 
2707 } mbox_req_hdr_t;
2708 
2709 
2710 typedef struct mbox_req_hdr2
2711 {
2712 #ifdef EMLXS_BIG_ENDIAN
2713 	uint32_t	vf_number:16;		/* word 6 */
2714 	uint32_t	subsystem:8;
2715 	uint32_t	opcode:8;
2716 
2717 	uint32_t	timeout;		/* word 7 */
2718 
2719 	uint32_t	req_length;		/* word 8 */
2720 
2721 	uint32_t	vh_number:6;		/* word 9 */
2722 	uint32_t	pf_number:10;
2723 	uint32_t	reserved1:8;
2724 	uint32_t	version:8;
2725 #endif
2726 #ifdef EMLXS_LITTLE_ENDIAN
2727 	uint32_t	opcode:8;
2728 	uint32_t	subsystem:8;
2729 	uint32_t	vf_number:16;		/* word 6 */
2730 
2731 	uint32_t	timeout;		/* word 7 */
2732 
2733 	uint32_t	req_length;		/* word 8 */
2734 
2735 	uint32_t	version:8;
2736 	uint32_t	reserved1:8;
2737 	uint32_t	pf_number:10;
2738 	uint32_t	vh_number:6;		/* word 9 */
2739 #endif
2740 
2741 } mbox_req_hdr2_t;
2742 
2743 typedef struct mbox_rsp_hdr
2744 {
2745 #ifdef EMLXS_BIG_ENDIAN
2746 	uint32_t	domain:8;		/* word 6 */
2747 	uint32_t	reserved1:8;
2748 	uint32_t	subsystem:8;
2749 	uint32_t	opcode:8;
2750 
2751 	uint32_t	reserved2:16;		/* word 7 */
2752 	uint32_t	extra_status:8;
2753 	uint32_t	status:8;
2754 #endif
2755 #ifdef EMLXS_LITTLE_ENDIAN
2756 	uint32_t	opcode:8;
2757 	uint32_t	subsystem:8;
2758 	uint32_t	reserved1:8;
2759 	uint32_t	domain:8;		/* word 6 */
2760 
2761 	uint32_t	status:8;
2762 	uint32_t	extra_status:8;
2763 	uint32_t	reserved2:16;		/* word 7 */
2764 #endif
2765 	uint32_t	rsp_length;		/* word 8 */
2766 	uint32_t	allocated_length;	/* word 9 */
2767 } mbox_rsp_hdr_t;
2768 
2769 #define	MBX_RSP_STATUS_SUCCESS		0x00
2770 #define	MBX_RSP_STATUS_FAILED		0x01
2771 #define	MBX_RSP_STATUS_ILLEGAL_REQ	0x02
2772 #define	MBX_RSP_STATUS_ILLEGAL_FIELD	0x03
2773 #define	MBX_RSP_STATUS_FCF_IN_USE	0x3A
2774 #define	MBX_RSP_STATUS_NO_FCF		0x43
2775 
2776 #define	MGMT_ADDI_STATUS_INCOMPATIBLE	0xA2
2777 
2778 typedef struct be_req_hdr
2779 {
2780 #ifdef EMLXS_BIG_ENDIAN
2781 	uint32_t	special:8;		/* word 1 */
2782 	uint32_t	reserved2:16;		/* word 1 */
2783 	uint32_t	sge_cnt:5;		/* word 1 */
2784 	uint32_t	reserved1:2;		/* word 1 */
2785 	uint32_t	embedded:1;		/* word 1 */
2786 #endif
2787 #ifdef EMLXS_LITTLE_ENDIAN
2788 	uint32_t	embedded:1;		/* word 1 */
2789 	uint32_t	reserved1:2;		/* word 1 */
2790 	uint32_t	sge_cnt:5;		/* word 1 */
2791 	uint32_t	reserved2:16;		/* word 1 */
2792 	uint32_t	special:8;		/* word 1 */
2793 #endif
2794 	uint32_t	payload_length;		/* word 2 */
2795 	uint32_t	tag_low;		/* word 3 */
2796 	uint32_t	tag_hi;			/* word 4 */
2797 	uint32_t	reserved3;		/* word 5 */
2798 	union
2799 	{
2800 		mbox_req_hdr_t	hdr_req;
2801 		mbox_req_hdr2_t hdr_req2;
2802 		mbox_rsp_hdr_t	hdr_rsp;
2803 	} un_hdr;
2804 } be_req_hdr_t;
2805 
2806 #define	EMLXS_MAX_NONEMBED_SIZE		(1024 * 64)
2807 
2808 /* SLI_CONFIG Mailbox commands */
2809 
2810 #define	IOCTL_SUBSYSTEM_COMMON			0x01
2811 #define	IOCTL_SUBSYSTEM_LOWLEVEL		0x0B
2812 #define	IOCTL_SUBSYSTEM_FCOE			0x0C
2813 #define	IOCTL_SUBSYSTEM_DCBX			0x10
2814 
2815 #define	COMMON_OPCODE_READ_FLASHROM		0x06
2816 #define	COMMON_OPCODE_WRITE_FLASHROM		0x07
2817 #define	COMMON_OPCODE_CQ_CREATE			0x0C
2818 #define	COMMON_OPCODE_EQ_CREATE			0x0D
2819 #define	COMMON_OPCODE_MQ_CREATE 		0x15
2820 #define	COMMON_OPCODE_GET_CNTL_ATTRIB		0x20
2821 #define	COMMON_OPCODE_NOP			0x21
2822 #define	COMMON_OPCODE_QUERY_FIRMWARE_CONFIG	0x3A
2823 #define	COMMON_OPCODE_RESET			0x3D
2824 #define	COMMON_OPCODE_SET_PHYSICAL_LINK_CFG_V1	0x3E
2825 
2826 #define	COMMON_OPCODE_GET_BOOT_CFG		0x42
2827 #define	COMMON_OPCODE_SET_BOOT_CFG		0x43
2828 #define	COMMON_OPCODE_MANAGE_FAT		0x44
2829 #define	COMMON_OPCODE_GET_PHYSICAL_LINK_CFG_V1	0x47
2830 #define	COMMON_OPCODE_GET_PORT_NAME		0x4D
2831 
2832 #define	COMMON_OPCODE_MQ_CREATE_EXT		0x5A
2833 #define	COMMON_OPCODE_GET_VPD_DATA		0x5B
2834 #define	COMMON_OPCODE_GET_PHY_DETAILS		0x66
2835 #define	COMMON_OPCODE_SEND_ACTIVATION		0x73
2836 #define	COMMON_OPCODE_RESET_LICENSES		0x74
2837 #define	COMMON_OPCODE_GET_CNTL_ADDL_ATTRIB	0x79
2838 
2839 #define	COMMON_OPCODE_GET_EXTENTS_INFO		0x9A
2840 #define	COMMON_OPCODE_GET_EXTENTS		0x9B
2841 #define	COMMON_OPCODE_ALLOC_EXTENTS		0x9C
2842 #define	COMMON_OPCODE_DEALLOC_EXTENTS		0x9D
2843 
2844 #define	COMMON_OPCODE_GET_PROFILE_CAPS		0xA1
2845 #define	COMMON_OPCODE_GET_MR_PROFILE_CAPS	0xA2
2846 #define	COMMON_OPCODE_SET_MR_PROFILE_CAPS	0xA3
2847 #define	COMMON_OPCODE_GET_PROFILE_CFG		0xA4
2848 #define	COMMON_OPCODE_SET_PROFILE_CFG		0xA5
2849 #define	COMMON_OPCODE_GET_PROFILE_LIST		0xA6
2850 #define	COMMON_OPCODE_GET_ACTIVE_PROFILE	0xA7
2851 #define	COMMON_OPCODE_SET_ACTIVE_PROFILE	0xA8
2852 #define	COMMON_OPCODE_SET_FACTORY_PROFILE_CFG	0xA9
2853 
2854 #define	COMMON_OPCODE_READ_OBJ			0xAB
2855 #define	COMMON_OPCODE_WRITE_OBJ			0xAC
2856 #define	COMMON_OPCODE_READ_OBJ_LIST		0xAD
2857 #define	COMMON_OPCODE_DELETE_OBJ		0xAE
2858 #define	COMMON_OPCODE_GET_SLI4_PARAMS		0xB5
2859 #define	COMMON_OPCODE_SET_FEATURES		0xBF
2860 #define	COMMON_OPCODE_GET_RECONFIG_LINK_INFO	0xC9
2861 #define	COMMON_OPCODE_SET_RECONFIG_LINK_ID	0xCA
2862 
2863 #define	LOWLEVEL_OPCODE_GPIO_RDWR		0x30
2864 
2865 #define	FCOE_OPCODE_WQ_CREATE			0x01
2866 #define	FCOE_OPCODE_CFG_POST_SGL_PAGES		0x03
2867 #define	FCOE_OPCODE_RQ_CREATE			0x05
2868 #define	FCOE_OPCODE_READ_FCF_TABLE		0x08
2869 #define	FCOE_OPCODE_ADD_FCF_TABLE		0x09
2870 #define	FCOE_OPCODE_DELETE_FCF_TABLE		0x0A
2871 #define	FCOE_OPCODE_POST_HDR_TEMPLATES		0x0B
2872 #define	FCOE_OPCODE_REDISCOVER_FCF_TABLE	0x10
2873 #define	FCOE_OPCODE_SET_FCLINK_SETTINGS		0x21
2874 
2875 #define	DCBX_OPCODE_GET_DCBX_MODE		0x04
2876 #define	DCBX_OPCODE_SET_DCBX_MODE		0x05
2877 
2878 typedef	struct
2879 {
2880 	struct
2881 	{
2882 		uint32_t opcode;
2883 #define	MGMT_FLASHROM_OPCODE_FLASH		1
2884 #define	MGMT_FLASHROM_OPCODE_SAVE		2
2885 #define	MGMT_FLASHROM_OPCODE_CLEAR		3
2886 #define	MGMT_FLASHROM_OPCODE_REPORT		4
2887 #define	MGMT_FLASHROM_OPCODE_INFO		5
2888 #define	MGMT_FLASHROM_OPCODE_CRC		6
2889 #define	MGMT_FLASHROM_OPCODE_OFFSET_FLASH	7
2890 #define	MGMT_FLASHROM_OPCODE_OFFSET_SAVE	8
2891 #define	MGMT_PHY_FLASHROM_OPCODE_FLASH		9
2892 #define	MGMT_PHY_FLASHROM_OPCODE_SAVE		10
2893 
2894 		uint32_t optype;
2895 #define	MGMT_FLASHROM_OPTYPE_ISCSI_FIRMWARE	0
2896 #define	MGMT_FLASHROM_OPTYPE_REDBOOT		1
2897 #define	MGMT_FLASHROM_OPTYPE_ISCSI_BIOS		2
2898 #define	MGMT_FLASHROM_OPTYPE_PXE_BIOS		3
2899 #define	MGMT_FLASHROM_OPTYPE_CTRLS		4
2900 #define	MGMT_FLASHROM_OPTYPE_CFG_IPSEC		5
2901 #define	MGMT_FLASHROM_OPTYPE_CFG_INI		6
2902 #define	MGMT_FLASHROM_OPTYPE_ROM_OFFSET		7
2903 #define	MGMT_FLASHROM_OPTYPE_FCOE_BIOS		8
2904 #define	MGMT_FLASHROM_OPTYPE_ISCSI_BACKUP	9
2905 #define	MGMT_FLASHROM_OPTYPE_FCOE_FIRMWARE	10
2906 #define	MGMT_FLASHROM_OPTYPE_FCOE_BACKUP	11
2907 #define	MGMT_FLASHROM_OPTYPE_CTRLP		12
2908 #define	MGMT_FLASHROM_OPTYPE_NCSI_FIRMWARE	13
2909 #define	MGMT_FLASHROM_OPTYPE_CFG_NIC		14
2910 #define	MGMT_FLASHROM_OPTYPE_CFG_DCBX		15
2911 #define	MGMT_FLASHROM_OPTYPE_CFG_PXE_BIOS	16
2912 #define	MGMT_FLASHROM_OPTYPE_CFG_ALL		17
2913 #define	MGMT_FLASHROM_OPTYPE_PHY_FIRMWARE	0xff /* Driver defined */
2914 
2915 		uint32_t data_buffer_size; /* Align to 4KB */
2916 		uint32_t offset;
2917 		uint32_t data_buffer; /* image starts here */
2918 
2919 	} params;
2920 
2921 } IOCTL_COMMON_FLASHROM;
2922 
2923 
2924 typedef	struct
2925 {
2926 	union
2927 	{
2928 		struct
2929 		{
2930 			uint32_t rsvd;
2931 		} request;
2932 
2933 
2934 		struct
2935 		{
2936 #ifdef EMLXS_BIG_ENDIAN
2937 			uint16_t interface_type;
2938 			uint16_t phy_type;
2939 #endif
2940 #ifdef EMLXS_LITTLE_ENDIAN
2941 			uint16_t phy_type;
2942 			uint16_t interface_type;
2943 #endif
2944 
2945 /* phy_type */
2946 #define	PHY_XAUI		0x0
2947 #define	PHY_AEL_2020		0x1 /* eluris/Netlogic */
2948 #define	PHY_LSI_BRCM1		0x2 /* Peak pre-production board */
2949 #define	PHY_LSI_BRCM2		0x3 /* Peak production board */
2950 #define	PHY_SOLARFLARE		0x4 /* Dell recommended */
2951 #define	PHY_AMCC_QT2025		0x5 /* AMCC PHY */
2952 #define	PHY_AMCC_QT2225		0x6 /* AMCC PHY */
2953 #define	PHY_BRCM_5931		0x7 /* Broadcom Phy used by HP LOM */
2954 #define	PHY_BE3_INTERNAL_10GB	0x8 /* Internal 10GbPHY in BE3 */
2955 #define	PHY_BE3_INTERNAL_1GB	0x9 /* Internal 1Gb PHY in BE3 */
2956 #define	PHY_TN_2022		0xa /* Teranetics dual port 65nm PHY */
2957 #define	PHY_MARVELL_88E1340	0xb /* Marvel 1G PHY */
2958 #define	PHY_MARVELL_88E1322	0xc /* Marvel 1G PHY */
2959 #define	PHY_TN_8022		0xd /* Teranetics dual port 40nm PHY */
2960 #define	PHY_TYPE_NOT_SUPPORTED
2961 
2962 /* interface_type */
2963 #define	CX4_10GB_TYPE		0x0
2964 #define	XFP_10GB_TYPE		0x1
2965 #define	SFP_1GB_TYPE		0x2
2966 #define	SFP_PLUS_10GB_TYPE	0x3
2967 #define	KR_10GB_TYPE		0x4
2968 #define	KX4_10GB_TYPE		0x5
2969 #define	BASET_10GB_TYPE		0x6 /* 10G BaseT */
2970 #define	BASET_1000_TYPE		0x7 /* 1000 BaseT */
2971 #define	BASEX_1000_TYPE		0x8 /* 1000 BaseX */
2972 #define	SGMII_TYPE		0x9
2973 #define	INTERFACE_10GB_DISABLED	0xff /* Interface type not supported */
2974 
2975 			uint32_t misc_params;
2976 			uint32_t rsvd[4];
2977 		} response;
2978 
2979 	} params;
2980 
2981 } IOCTL_COMMON_GET_PHY_DETAILS;
2982 
2983 
2984 typedef	struct
2985 {
2986 	union
2987 	{
2988 		struct
2989 		{
2990 			uint32_t rsvd;
2991 		} request;
2992 
2993 
2994 		struct
2995 		{
2996 #ifdef EMLXS_BIG_ENDIAN
2997 			uint8_t port3_name;
2998 			uint8_t port2_name;
2999 			uint8_t port1_name;
3000 			uint8_t port0_name;
3001 #endif
3002 #ifdef EMLXS_LITTLE_ENDIAN
3003 			uint8_t port0_name;
3004 			uint8_t port1_name;
3005 			uint8_t port2_name;
3006 			uint8_t port3_name;
3007 #endif
3008 		} response;
3009 
3010 	} params;
3011 
3012 } IOCTL_COMMON_GET_PORT_NAME;
3013 
3014 
3015 typedef	struct
3016 {
3017 	union
3018 	{
3019 		struct
3020 		{
3021 #ifdef EMLXS_BIG_ENDIAN
3022 			uint32_t rsvd:30;
3023 			uint32_t pt:2;
3024 #endif
3025 #ifdef EMLXS_LITTLE_ENDIAN
3026 			uint32_t pt:2;
3027 			uint32_t rsvd:30;
3028 #endif
3029 #define	PORT_TYPE_GIGE		0
3030 #define	PORT_TYPE_FC		1
3031 		} request;
3032 
3033 
3034 		struct
3035 		{
3036 #ifdef EMLXS_BIG_ENDIAN
3037 			uint8_t port3_name;
3038 			uint8_t port2_name;
3039 			uint8_t port1_name;
3040 			uint8_t port0_name;
3041 #endif
3042 #ifdef EMLXS_LITTLE_ENDIAN
3043 			uint8_t port0_name;
3044 			uint8_t port1_name;
3045 			uint8_t port2_name;
3046 			uint8_t port3_name;
3047 #endif
3048 		} response;
3049 
3050 	} params;
3051 
3052 } IOCTL_COMMON_GET_PORT_NAME_V1;
3053 
3054 
3055 typedef	struct
3056 {
3057 	union
3058 	{
3059 		struct
3060 		{
3061 			uint32_t fat_operation;
3062 #define	RETRIEVE_FAT		0
3063 #define	QUERY_FAT		1
3064 #define	CLEAR_FAT		2
3065 
3066 			uint32_t read_log_offset;
3067 			uint32_t read_log_length;
3068 			uint32_t data_buffer_size;
3069 			uint32_t data_buffer;
3070 		} request;
3071 
3072 		struct
3073 		{
3074 			uint32_t log_size;
3075 			uint32_t read_log_length;
3076 			uint32_t rsvd0;
3077 			uint32_t rsvd1;
3078 			uint32_t data_buffer;
3079 		} response;
3080 
3081 	} params;
3082 
3083 } IOCTL_COMMON_MANAGE_FAT;
3084 
3085 
3086 typedef	struct
3087 {
3088 	union
3089 	{
3090 		struct
3091 		{
3092 #ifdef EMLXS_BIG_ENDIAN
3093 			uint32_t EOF:1; /* word 4 */
3094 			uint32_t rsvd0:7;
3095 			uint32_t desired_write_length:24;
3096 #endif
3097 #ifdef EMLXS_LITTLE_ENDIAN
3098 			uint32_t desired_write_length:24;
3099 			uint32_t rsvd0:7;
3100 			uint32_t EOF:1;  /* word 4 */
3101 #endif
3102 			uint32_t write_offset;  /* word 5 */
3103 			char object_name[(4 * 26)];   /* word 6 - 31 */
3104 			uint32_t buffer_desc_count; /* word 32 */
3105 
3106 #ifdef EMLXS_BIG_ENDIAN
3107 			uint32_t rsvd:8; /* word 33 */
3108 			uint32_t buffer_length:24;
3109 #endif
3110 #ifdef EMLXS_LITTLE_ENDIAN
3111 			uint32_t buffer_length:24;
3112 			uint32_t rsvd:8; /* word 33 */
3113 #endif
3114 			uint32_t buffer_addrlo; /* word 34 */
3115 			uint32_t buffer_addrhi; /* word 35 */
3116 		} request;
3117 
3118 		struct
3119 		{
3120 			uint32_t actual_write_length;
3121 
3122 #ifdef EMLXS_BIG_ENDIAN
3123 			uint32_t rsvd:24;
3124 			uint32_t change_status:8;
3125 #endif
3126 #ifdef EMLXS_LITTLE_ENDIAN
3127 			uint32_t change_status:8;
3128 			uint32_t rsvd:24;
3129 #endif
3130 #define	CS_NO_RESET		0
3131 #define	CS_REBOOT_RQD		1
3132 #define	CS_FW_RESET_RQD		2
3133 #define	CS_PROTO_RESET_RQD	3
3134 		} response;
3135 
3136 	} params;
3137 
3138 } IOCTL_COMMON_WRITE_OBJECT;
3139 
3140 
3141 typedef	struct
3142 {
3143 	union
3144 	{
3145 		struct
3146 		{
3147 #ifdef EMLXS_BIG_ENDIAN
3148 			uint32_t descriptor_offset:16; /* word 4 */
3149 			uint32_t descriptor_count:16;
3150 #endif
3151 #ifdef EMLXS_LITTLE_ENDIAN
3152 			uint32_t descriptor_count:16;
3153 			uint32_t descriptor_offset:16; /* word 4 */
3154 #endif
3155 			uint32_t reserved;  /* word 5 */
3156 			char object_name[(4 * 26)];   /* word 6 - 31 */
3157 			uint32_t buffer_desc_count; /* word 32 */
3158 
3159 #ifdef EMLXS_BIG_ENDIAN
3160 			uint32_t rsvd:8; /* word 33 */
3161 			uint32_t buffer_length:24;
3162 #endif
3163 #ifdef EMLXS_LITTLE_ENDIAN
3164 			uint32_t buffer_length:24;
3165 			uint32_t rsvd:8; /* word 33 */
3166 #endif
3167 			uint32_t buffer_addrlo; /* word 34 */
3168 			uint32_t buffer_addrhi; /* word 35 */
3169 		} request;
3170 
3171 		struct
3172 		{
3173 #ifdef EMLXS_BIG_ENDIAN
3174 			uint32_t reserved:16;
3175 			uint32_t actual_descriptor_count:16;
3176 #endif
3177 #ifdef EMLXS_LITTLE_ENDIAN
3178 			uint32_t actual_descriptor_count:16;
3179 			uint32_t reserved:16;
3180 #endif
3181 		} response;
3182 
3183 	} params;
3184 
3185 } IOCTL_COMMON_READ_OBJECT_LIST;
3186 
3187 
3188 typedef	struct
3189 {
3190 	union
3191 	{
3192 		struct
3193 		{
3194 #ifdef EMLXS_BIG_ENDIAN
3195 			uint32_t reserved:16; /* word 4 */
3196 			uint32_t boot_instance:8;
3197 			uint32_t boot_status:8;
3198 #endif
3199 #ifdef EMLXS_LITTLE_ENDIAN
3200 			uint32_t boot_status:8;
3201 			uint32_t boot_instance:8;
3202 			uint32_t reserved:16; /* word 4 */
3203 #endif
3204 		} request;
3205 
3206 		struct
3207 		{
3208 #ifdef EMLXS_BIG_ENDIAN
3209 			uint32_t reserved:16; /* word 4 */
3210 			uint32_t boot_instance:8;
3211 			uint32_t boot_status:8;
3212 #endif
3213 #ifdef EMLXS_LITTLE_ENDIAN
3214 			uint32_t boot_status:8;
3215 			uint32_t boot_instance:8;
3216 			uint32_t reserved:16; /* word 4 */
3217 #endif
3218 		} response;
3219 
3220 	} params;
3221 
3222 } IOCTL_COMMON_BOOT_CFG;
3223 
3224 
3225 /* IOCTL_COMMON_QUERY_FIRMWARE_CONFIG */
3226 typedef struct _BE_FW_CFG
3227 {
3228 	uint32_t	BEConfigNumber;
3229 	uint32_t	ASICRevision;
3230 	uint32_t	PhysicalPort;
3231 	uint32_t	FunctionMode;
3232 	uint32_t	ULPMode;
3233 
3234 } BE_FW_CFG;
3235 
3236 typedef	struct _IOCTL_COMMON_QUERY_FIRMWARE_CONFIG
3237 {
3238 	union
3239 	{
3240 		struct
3241 		{
3242 			uint32_t	rsvd0;
3243 		} request;
3244 
3245 		BE_FW_CFG	response;
3246 
3247 	}	params;
3248 
3249 } IOCTL_COMMON_QUERY_FIRMWARE_CONFIG;
3250 
3251 /* IOCTL_LOWLEVEL_GPIO_RDWR */
3252 typedef struct _IOCTL_LOWLEVEL_GPIO_RDWR
3253 {
3254 	union
3255 	{
3256 		struct
3257 		{
3258 			uint32_t	GpioAction;
3259 #define	LOWLEVEL_GPIO_ACT_READ		0
3260 #define	LOWLEVEL_GPIO_ACT_WRITE	1
3261 #define	LOWLEVEL_GPIO_ACT_RDSENSE	2
3262 #define	LOWLEVEL_GPIO_ACT_STSENSE	3
3263 
3264 			uint32_t	LogicalPin;
3265 			uint32_t	PinValue;
3266 #define	LOWLEVEL_GPIO_STSENSE_IN	0
3267 #define	LOWLEVEL_GPIO_STSENSE_OUT	1
3268 
3269 			uint32_t	OutputValue;
3270 		} request;
3271 
3272 		struct
3273 		{
3274 			uint32_t	PinValue;
3275 		} response;
3276 	} params;
3277 } IOCTL_LOWLEVEL_GPIO_RDWR;
3278 
3279 /* IOCTL_FCOE_READ_FCF_TABLE */
3280 typedef struct
3281 {
3282 	uint32_t	max_recv_size;
3283 	uint32_t	fka_adv_period;
3284 	uint32_t	fip_priority;
3285 
3286 #ifdef EMLXS_BIG_ENDIAN
3287 	uint8_t		fcf_mac_address_hi[4];
3288 
3289 	uint8_t		mac_address_provider;
3290 	uint8_t		fcf_available;
3291 	uint8_t		fcf_mac_address_low[2];
3292 
3293 	uint8_t		fabric_name_identifier[8];
3294 
3295 	uint8_t		fcf_sol:1;
3296 	uint8_t		rsvd0:5;
3297 	uint8_t		fcf_fc:1;
3298 	uint8_t		fcf_valid:1;
3299 	uint8_t		fc_map[3];
3300 
3301 	uint16_t	fcf_state;
3302 	uint16_t	fcf_index;
3303 #endif
3304 #ifdef EMLXS_LITTLE_ENDIAN
3305 	uint8_t		fcf_mac_address_hi[4];
3306 
3307 	uint8_t		fcf_mac_address_low[2];
3308 	uint8_t		fcf_available;
3309 	uint8_t		mac_address_provider;
3310 
3311 	uint8_t		fabric_name_identifier[8];
3312 
3313 	uint8_t		fc_map[3];
3314 	uint8_t		fcf_valid:1;
3315 	uint8_t		fcf_fc:1;
3316 	uint8_t		rsvd0:5;
3317 	uint8_t		fcf_sol:1;
3318 
3319 	uint16_t	fcf_index;
3320 	uint16_t	fcf_state;
3321 #endif
3322 
3323 	uint8_t		vlan_bitmap[512];
3324 	uint8_t		switch_name_identifier[8];
3325 
3326 } FCF_RECORD_t;
3327 
3328 #define	EMLXS_FCOE_MAX_RCV_SZ	0x800
3329 
3330 /* defines for mac_address_provider */
3331 #define	EMLXS_MAM_BOTH	0	/* Both SPMA and FPMA */
3332 #define	EMLXS_MAM_FPMA	1	/* Fabric Provided MAC Address */
3333 #define	EMLXS_MAM_SPMA	2	/* Server Provided MAC Address */
3334 
3335 typedef struct
3336 {
3337 	union
3338 	{
3339 		struct
3340 		{
3341 #ifdef EMLXS_BIG_ENDIAN
3342 			uint16_t	rsvd0;
3343 			uint16_t	fcf_index;
3344 #endif
3345 #ifdef EMLXS_LITTLE_ENDIAN
3346 			uint16_t	fcf_index;
3347 			uint16_t	rsvd0;
3348 #endif
3349 
3350 		} request;
3351 
3352 		struct
3353 		{
3354 			uint32_t	event_tag;
3355 #ifdef EMLXS_BIG_ENDIAN
3356 			uint16_t	rsvd0;
3357 			uint16_t	next_valid_fcf_index;
3358 #endif
3359 #ifdef EMLXS_LITTLE_ENDIAN
3360 			uint16_t	next_valid_fcf_index;
3361 			uint16_t	rsvd0;
3362 #endif
3363 			FCF_RECORD_t fcf_entry[1];
3364 
3365 		} response;
3366 
3367 	} params;
3368 
3369 } IOCTL_FCOE_READ_FCF_TABLE;
3370 
3371 
3372 /* IOCTL_FCOE_ADD_FCF_TABLE */
3373 typedef struct
3374 {
3375 	union
3376 	{
3377 		struct
3378 		{
3379 #ifdef EMLXS_BIG_ENDIAN
3380 			uint16_t	rsvd0;
3381 			uint16_t	fcf_index;
3382 #endif
3383 #ifdef EMLXS_LITTLE_ENDIAN
3384 			uint16_t	fcf_index;
3385 			uint16_t	rsvd0;
3386 #endif
3387 			FCF_RECORD_t fcf_entry;
3388 
3389 		} request;
3390 	} params;
3391 
3392 } IOCTL_FCOE_ADD_FCF_TABLE;
3393 
3394 
3395 /* IOCTL_FCOE_DELETE_FCF_TABLE */
3396 typedef struct
3397 {
3398 	union
3399 	{
3400 		struct
3401 		{
3402 #ifdef EMLXS_BIG_ENDIAN
3403 			uint16_t	fcf_indexes[1];
3404 			uint16_t	fcf_count;
3405 #endif
3406 #ifdef EMLXS_LITTLE_ENDIAN
3407 			uint16_t	fcf_count;
3408 			uint16_t	fcf_indexes[1];
3409 #endif
3410 
3411 		} request;
3412 	} params;
3413 
3414 } IOCTL_FCOE_DELETE_FCF_TABLE;
3415 
3416 
3417 /* IOCTL_FCOE_REDISCOVER_FCF_TABLE */
3418 typedef struct
3419 {
3420 	union
3421 	{
3422 		struct
3423 		{
3424 #ifdef EMLXS_BIG_ENDIAN
3425 			uint16_t	rsvd0;
3426 			uint16_t	fcf_count;
3427 #endif
3428 #ifdef EMLXS_LITTLE_ENDIAN
3429 			uint16_t	fcf_count;
3430 			uint16_t	rsvd0;
3431 #endif
3432 			uint32_t	rsvd1;
3433 			uint16_t	fcf_index[1];
3434 
3435 		} request;
3436 	} params;
3437 
3438 } IOCTL_FCOE_REDISCOVER_FCF_TABLE;
3439 
3440 
3441 #define	FCOE_FCF_MAC0	0x0E
3442 #define	FCOE_FCF_MAC1	0xFC
3443 #define	FCOE_FCF_MAC2	0x00
3444 #define	FCOE_FCF_MAC3	0xFF
3445 #define	FCOE_FCF_MAC4	0xFF
3446 #define	FCOE_FCF_MAC5	0xFE
3447 
3448 #define	FCOE_FCF_MAP0	0x0E
3449 #define	FCOE_FCF_MAP1	0xFC
3450 #define	FCOE_FCF_MAP2	0x00
3451 
3452 #define	MGMT_STATUS_FCF_IN_USE	0x3a
3453 
3454 /* IOCTL_COMMON_NOP */
3455 typedef	struct _IOCTL_COMMON_NOP
3456 {
3457 	union
3458 	{
3459 		struct
3460 		{
3461 			uint64_t	context;
3462 		} request;
3463 
3464 		struct
3465 		{
3466 			uint64_t	context;
3467 		} response;
3468 
3469 	} params;
3470 
3471 } IOCTL_COMMON_NOP;
3472 
3473 
3474 /*	Context for EQ create	*/
3475 typedef	struct _EQ_CONTEXT
3476 {
3477 #ifdef EMLXS_BIG_ENDIAN
3478 	uint32_t	Size:1;
3479 	uint32_t	Rsvd2:1;
3480 	uint32_t	Valid:1;
3481 	uint32_t	AutoValid:1;
3482 	uint32_t	Rsvd1:28;
3483 
3484 	uint32_t	Armed:1;
3485 	uint32_t	Rsvd4:2;
3486 	uint32_t	Count:3;
3487 	uint32_t	Rsvd3:26;
3488 
3489 	uint32_t	Rsvd6:9;
3490 	uint32_t	DelayMult:10;
3491 	uint32_t	Rsvd5:13;
3492 #endif
3493 #ifdef EMLXS_LITTLE_ENDIAN
3494 	uint32_t	Rsvd1:28;
3495 	uint32_t	AutoValid:1;
3496 	uint32_t	Valid:1;
3497 	uint32_t	Rsvd2:1;
3498 	uint32_t	Size:1;
3499 
3500 	uint32_t	Rsvd3:26;
3501 	uint32_t	Count:3;
3502 	uint32_t	Rsvd4:2;
3503 	uint32_t	Armed:1;
3504 
3505 	uint32_t	Rsvd5:13;
3506 	uint32_t	DelayMult:10;
3507 	uint32_t	Rsvd6:9;
3508 #endif
3509 
3510 	uint32_t	Rsvd7;
3511 
3512 } EQ_CONTEXT;
3513 
3514 
3515 /* define for Count field */
3516 #define	EQ_ELEMENT_COUNT_1024	2
3517 #define	EQ_ELEMENT_COUNT_2048	3
3518 #define	EQ_ELEMENT_COUNT_4096	4
3519 
3520 /* define for Size field */
3521 #define	EQ_ELEMENT_SIZE_4	0
3522 #define	EQ_ELEMENT_SIZE_16	1
3523 
3524 /* define for DelayMullt - used for interrupt coalescing */
3525 #define	EQ_DELAY_MULT		64
3526 
3527 /*	Context for CQ create	*/
3528 typedef	struct _CQ_CONTEXT
3529 {
3530 #ifdef EMLXS_BIG_ENDIAN
3531 	uint32_t	Eventable:1;
3532 	uint32_t	Rsvd3:1;
3533 	uint32_t	Valid:1;
3534 	uint32_t	Count:2;
3535 	uint32_t	Rsvd2:12;
3536 	uint32_t	NoDelay:1;
3537 	uint32_t	CoalesceWM:2;
3538 	uint32_t	Rsvd1:12;
3539 
3540 	uint32_t	Armed:1;
3541 	uint32_t	Rsvd5:1;
3542 	uint32_t	EQId:8;
3543 	uint32_t	Rsvd4:22;
3544 
3545 	uint32_t	Rsvd6;
3546 #endif
3547 #ifdef EMLXS_LITTLE_ENDIAN
3548 	uint32_t	Rsvd1:12;
3549 	uint32_t	CoalesceWM:2;
3550 	uint32_t	NoDelay:1;
3551 	uint32_t	Rsvd2:12;
3552 	uint32_t	Count:2;
3553 	uint32_t	Valid:1;
3554 	uint32_t	Rsvd3:1;
3555 	uint32_t	Eventable:1;
3556 
3557 	uint32_t	Rsvd4:22;
3558 	uint32_t	EQId:8;
3559 	uint32_t	Rsvd5:1;
3560 	uint32_t	Armed:1;
3561 
3562 	uint32_t	Rsvd6;
3563 #endif
3564 
3565 	uint32_t	Rsvd7;
3566 
3567 } CQ_CONTEXT;
3568 
3569 typedef	struct _CQ_CONTEXT_V2
3570 {
3571 #ifdef EMLXS_BIG_ENDIAN
3572 	uint32_t	Eventable:1;
3573 	uint32_t	Rsvd3:1;
3574 	uint32_t	Valid:1;
3575 	uint32_t	CqeCnt:2;
3576 	uint32_t	CqeSize:2;
3577 	uint32_t	Rsvd2:9;
3578 	uint32_t	AutoValid:1;
3579 	uint32_t	NoDelay:1;
3580 	uint32_t	CoalesceWM:2;
3581 	uint32_t	Rsvd1:12;
3582 
3583 	uint32_t	Armed:1;
3584 	uint32_t	Rsvd4:15;
3585 	uint32_t	EQId:16;
3586 
3587 	uint32_t	Rsvd5:16;
3588 	uint32_t	Count1:16;
3589 #endif
3590 #ifdef EMLXS_LITTLE_ENDIAN
3591 	uint32_t	Rsvd1:12;
3592 	uint32_t	CoalesceWM:2;
3593 	uint32_t	NoDelay:1;
3594 	uint32_t	AutoValid:1;
3595 	uint32_t	Rsvd2:9;
3596 	uint32_t	CqeSize:2;
3597 	uint32_t	CqeCnt:2;
3598 	uint32_t	Valid:1;
3599 	uint32_t	Rsvd3:1;
3600 	uint32_t	Eventable:1;
3601 
3602 	uint32_t	EQId:16;
3603 	uint32_t	Rsvd4:15;
3604 	uint32_t	Armed:1;
3605 
3606 	uint32_t	Count1:16;
3607 	uint32_t	Rsvd5:16;
3608 #endif
3609 
3610 	uint32_t	Rsvd7;
3611 
3612 } CQ_CONTEXT_V2;
3613 
3614 /* CqeSize */
3615 #define	CQE_SIZE_16_BYTES	0
3616 #define	CQE_SIZE_32_BYTES	1
3617 
3618 /* define for Count field */
3619 #define	CQ_ELEMENT_COUNT_256	0
3620 #define	CQ_ELEMENT_COUNT_512	1
3621 #define	CQ_ELEMENT_COUNT_1024	2
3622 #define	CQ_ELEMENT_COUNT_SPECIFIED	3
3623 
3624 /*	Context for MQ create	*/
3625 typedef	struct _MQ_CONTEXT
3626 {
3627 #ifdef EMLXS_BIG_ENDIAN
3628 	uint32_t	CQId:10;
3629 	uint32_t	Rsvd2:2;
3630 	uint32_t	Size:4;
3631 	uint32_t	Rsvd1:16;
3632 
3633 	uint32_t	Valid:1;
3634 	uint32_t	Rsvd3:31;
3635 
3636 	uint32_t	Rsvd4:21;
3637 	uint32_t	ACQId:10;
3638 	uint32_t	ACQV:1;
3639 #endif
3640 #ifdef EMLXS_LITTLE_ENDIAN
3641 	uint32_t	Rsvd1:16;
3642 	uint32_t	Size:4;
3643 	uint32_t	Rsvd2:2;
3644 	uint32_t	CQId:10;
3645 
3646 	uint32_t	Rsvd3:31;
3647 	uint32_t	Valid:1;
3648 
3649 	uint32_t	ACQV:1;
3650 	uint32_t	ACQId:10;
3651 	uint32_t	Rsvd4:21;
3652 #endif
3653 
3654 	uint32_t	Rsvd5;
3655 
3656 } MQ_CONTEXT;
3657 
3658 
3659 typedef	struct _MQ_CONTEXT_V1
3660 {
3661 #ifdef EMLXS_BIG_ENDIAN
3662 	uint32_t	Rsvd2:12;
3663 	uint32_t	Size:4;
3664 	uint32_t	ACQId:16;
3665 
3666 	uint32_t	Valid:1;
3667 	uint32_t	Rsvd3:31;
3668 
3669 	uint32_t	Rsvd4:31;
3670 	uint32_t	ACQV:1;
3671 #endif
3672 #ifdef EMLXS_LITTLE_ENDIAN
3673 	uint32_t	ACQId:16;
3674 	uint32_t	Size:4;
3675 	uint32_t	Rsvd2:12;
3676 
3677 	uint32_t	Rsvd3:31;
3678 	uint32_t	Valid:1;
3679 
3680 	uint32_t	ACQV:1;
3681 	uint32_t	Rsvd4:31;
3682 #endif
3683 
3684 	uint32_t	Rsvd5;
3685 
3686 } MQ_CONTEXT_V1;
3687 
3688 
3689 /* define for Size field */
3690 #define	MQ_ELEMENT_COUNT_16 0x05
3691 
3692 /*	Context for RQ create	*/
3693 typedef	struct _RQ_CONTEXT
3694 {
3695 #ifdef EMLXS_BIG_ENDIAN
3696 	uint32_t	Rsvd2:12;
3697 	uint32_t	RqeCnt:4;
3698 	uint32_t	Rsvd1:16;
3699 
3700 	uint32_t	Rsvd3;
3701 
3702 	uint32_t	CQId:16;
3703 	uint32_t	BufferSize:16;
3704 #endif
3705 #ifdef EMLXS_LITTLE_ENDIAN
3706 	uint32_t	Rsvd1:16;
3707 	uint32_t	RqeCnt:4;
3708 	uint32_t	Rsvd2:12;
3709 
3710 	uint32_t	Rsvd3;
3711 
3712 	uint32_t	BufferSize:16;
3713 	uint32_t	CQId:16;
3714 #endif
3715 
3716 	uint32_t  Rsvd5;
3717 
3718 } RQ_CONTEXT;
3719 
3720 typedef	struct _RQ_CONTEXT_V1
3721 {
3722 #ifdef EMLXS_BIG_ENDIAN
3723 	uint32_t	RqeCnt:16;
3724 	uint32_t	Rsvd1:4;
3725 	uint32_t	RqeSize:4;
3726 	uint32_t	PageSize:8;
3727 
3728 	uint32_t	Rsvd2;
3729 
3730 	uint32_t	CQId:16;
3731 	uint32_t	Rsvd:16;
3732 #endif
3733 #ifdef EMLXS_LITTLE_ENDIAN
3734 	uint32_t	PageSize:8;
3735 	uint32_t	RqeSize:4;
3736 	uint32_t	Rsvd1:4;
3737 	uint32_t	RqeCnt:16;
3738 
3739 	uint32_t	Rsvd2;
3740 
3741 	uint32_t	Rsvd:16;
3742 	uint32_t	CQId:16;
3743 #endif
3744 
3745 	uint32_t	BufferSize;
3746 
3747 } RQ_CONTEXT_V1;
3748 
3749 /* RqeSize */
3750 #define	RQE_SIZE_8_BYTES	0x02
3751 #define	RQE_SIZE_16_BYTES	0x03
3752 #define	RQE_SIZE_32_BYTES	0x04
3753 #define	RQE_SIZE_64_BYTES	0x05
3754 #define	RQE_SIZE_128_BYTES	0x06
3755 
3756 /* RQ PageSize */
3757 #define	RQ_PAGE_SIZE_4K		0x01
3758 #define	RQ_PAGE_SIZE_8K		0x02
3759 #define	RQ_PAGE_SIZE_16K	0x04
3760 #define	RQ_PAGE_SIZE_32K	0x08
3761 #define	RQ_PAGE_SIZE_64K	0x10
3762 
3763 
3764 /* IOCTL_COMMON_EQ_CREATE */
3765 typedef	struct
3766 {
3767 	union
3768 	{
3769 		struct
3770 		{
3771 #ifdef EMLXS_BIG_ENDIAN
3772 			uint16_t	Rsvd1;
3773 			uint16_t	NumPages;
3774 #endif
3775 #ifdef EMLXS_LITTLE_ENDIAN
3776 			uint16_t	NumPages;
3777 			uint16_t	Rsvd1;
3778 #endif
3779 			EQ_CONTEXT	EQContext;
3780 			BE_PHYS_ADDR	Pages[8];
3781 		} request;
3782 
3783 		struct
3784 		{
3785 #ifdef EMLXS_BIG_ENDIAN
3786 			uint16_t	MsiIndex; /* V1 only */
3787 			uint16_t	EQId;
3788 #endif
3789 #ifdef EMLXS_LITTLE_ENDIAN
3790 			uint16_t	EQId;
3791 			uint16_t	MsiIndex; /* V1 only */
3792 #endif
3793 		} response;
3794 	} params;
3795 
3796 } IOCTL_COMMON_EQ_CREATE;
3797 
3798 
3799 typedef	struct
3800 {
3801 #ifdef EMLXS_BIG_ENDIAN
3802 		uint32_t	Rsvd1:24;		/* Word 0 */
3803 		uint32_t	ProtocolType:8;
3804 
3805 		uint32_t	Rsvd3:3;		/* Word 1 */
3806 		uint32_t	SliHint2:5;
3807 		uint32_t	SliHint1:8;
3808 		uint32_t	IfType:4;
3809 		uint32_t	SliFamily:4;
3810 		uint32_t	Revision:4;
3811 		uint32_t	Rsvd2:3;
3812 		uint32_t	FT:1;
3813 
3814 		uint32_t	EqAV:1;			/* Word 2 */
3815 		uint32_t	EqRsvd3:3;
3816 		uint32_t	EqeCntMethod:4;
3817 		uint32_t	EqPageSize:8;
3818 		uint32_t	EqRsvd2:4;
3819 		uint32_t	EqeSize:4;
3820 		uint32_t	EqRsvd1:4;
3821 		uint32_t	EqPageCnt:4;
3822 
3823 		uint32_t	EqRsvd4:16;		/* Word 3 */
3824 		uint32_t	EqeCntMask:16;
3825 
3826 		uint32_t	CqAV:1;			/* Word 4 */
3827 		uint32_t	CqRsvd3:3;
3828 		uint32_t	CqeCntMethod:4;
3829 		uint32_t	CqPageSize:8;
3830 		uint32_t	CQV:2;
3831 		uint32_t	CqRsvd2:2;
3832 		uint32_t	CqeSize:4;
3833 		uint32_t	CqRsvd1:4;
3834 		uint32_t	CqPageCnt:4;
3835 
3836 		uint32_t	CqRsvd4:16;		/* Word 5 */
3837 		uint32_t	CqeCntMask:16;
3838 
3839 		uint32_t	MqRsvd2:4;		/* Word 6 */
3840 		uint32_t	MqeCntMethod:4;
3841 		uint32_t	MqPageSize:8;
3842 		uint32_t	MQV:2;
3843 		uint32_t	MqRsvd1:10;
3844 		uint32_t	MqPageCnt:4;
3845 
3846 		uint32_t	MqRsvd3:16;		/* Word 7 */
3847 		uint32_t	MqeCntMask:16;
3848 
3849 		uint32_t	WqRsvd3:4;		/* Word 8 */
3850 		uint32_t	WqeCntMethod:4;
3851 		uint32_t	WqPageSize:8;
3852 		uint32_t	WQV:2;
3853 		uint32_t	WqeRsvd2:2;
3854 		uint32_t	WqeSize:4;
3855 		uint32_t	WqRsvd1:4;
3856 		uint32_t	WqPageCnt:4;
3857 
3858 		uint32_t	WqRsvd4:16;		/* Word 9 */
3859 		uint32_t	WqeCntMask:16;
3860 
3861 		uint32_t	RqRsvd3:4;		/* Word 10 */
3862 		uint32_t	RqeCntMethod:4;
3863 		uint32_t	RqPageSize:8;
3864 		uint32_t	RQV:2;
3865 		uint32_t	RqeRsvd2:2;
3866 		uint32_t	RqeSize:4;
3867 		uint32_t	RqRsvd1:4;
3868 		uint32_t	RqPageCnt:4;
3869 
3870 		uint32_t	RqDbWin:4;		/* Word 11 */
3871 		uint32_t	RqRsvd4:12;
3872 		uint32_t	RqeCntMask:16;
3873 
3874 		uint32_t	Loopback:4;		/* Word 12 */
3875 		uint32_t	agxf :1;
3876 		uint32_t	lc :1;
3877 		uint32_t	oas :1;
3878 		uint32_t	:1;
3879 		uint32_t	tsmm :1;
3880 		uint32_t	timm :1;
3881 		uint32_t	sglc :1;
3882 		uint32_t	rxri :1;
3883 		uint32_t	ipr :1;
3884 		uint32_t	hlm :1;
3885 		uint32_t	rxc :1;
3886 		uint32_t	boundary_4ga:1;
3887 		uint32_t	PHWQ:1;
3888 		uint32_t	PHON:1;
3889 		uint32_t	PHOFF:1;
3890 		uint32_t	TRIR:1;
3891 		uint32_t	TRTY:1;
3892 		uint32_t	TCCA:1;
3893 		uint32_t	MWQE:1;
3894 		uint32_t	ASSI:1;
3895 		uint32_t	TERP:1;
3896 		uint32_t	TGT:1;
3897 		uint32_t	AREG:1;
3898 		uint32_t	FBRR:1;
3899 		uint32_t	SGLR:1;
3900 		uint32_t	HDRR:1;
3901 		uint32_t	EXT:1;
3902 		uint32_t	FCOE:1;
3903 
3904 		uint32_t	SgeLength;		/* Word 13 */
3905 
3906 		uint32_t	SglRsvd2:8;		/* Word 14 */
3907 		uint32_t	SglAlign:8;
3908 		uint32_t	SglPageSize:8;
3909 		uint32_t	SglRsvd1:4;
3910 		uint32_t	SglPageCnt:4;
3911 
3912 		uint32_t	Rsvd5:16;		/* Word 15 */
3913 		uint32_t	MinRqSize:16;
3914 
3915 		uint32_t	MaxRqSize;		/* Word 16 */
3916 
3917 		uint32_t	RPIMax:16;
3918 		uint32_t	XRIMax:16;		/* Word 17 */
3919 
3920 		uint32_t	VFIMax:16;
3921 		uint32_t	VPIMax:16;		/* Word 18 */
3922 
3923 		uint32_t	:11;
3924 		uint32_t	pbde :1;		/* Word 19 */
3925 		uint32_t	:6;
3926 		uint32_t	pvl:1;
3927 		uint32_t	nsler :1;
3928 		uint32_t	:1;
3929 		uint32_t	bv1s :1;
3930 		uint32_t	nosr :1;
3931 		uint32_t	eqdr :1;
3932 		uint32_t	:1;
3933 		uint32_t	xpsgl :1;
3934 		uint32_t	:1;
3935 		uint32_t	xibi :1;
3936 		uint32_t	nvme :1;
3937 		uint32_t	:1;
3938 		uint32_t	mds_diags :1;
3939 		uint32_t	ext_embed_cb :1;
3940 
3941 		uint32_t	frag_num_field_size:16;
3942 		uint32_t	frag_num_field_offset:16;
3943 		uint32_t	sgl_index_field_size:16;
3944 		uint32_t	sgl_index_field_offset:16;
3945 #endif
3946 #ifdef EMLXS_LITTLE_ENDIAN
3947 		uint32_t	ProtocolType:8;		/* Word 0 */
3948 		uint32_t	Rsvd1:24;
3949 
3950 		uint32_t	FT:1;			/* Word 1 */
3951 		uint32_t	Rsvd2:3;
3952 		uint32_t	Revision:4;
3953 		uint32_t	SliFamily:4;
3954 		uint32_t	IfType:4;
3955 		uint32_t	SliHint1:8;
3956 		uint32_t	SliHint2:5;
3957 		uint32_t	Rsvd3:3;
3958 
3959 		uint32_t	EqPageCnt:4;		/* Word 2 */
3960 		uint32_t	EqRsvd1:4;
3961 		uint32_t	EqeSize:4;
3962 		uint32_t	EqRsvd2:4;
3963 		uint32_t	EqPageSize:8;
3964 		uint32_t	EqeCntMethod:4;
3965 		uint32_t	EqRsvd3:3;
3966 		uint32_t	EqAV:1;			/* auto valid */
3967 
3968 		uint32_t	EqeCntMask:16;		/* Word 3 */
3969 		uint32_t	EqRsvd4:16;
3970 
3971 		uint32_t	CqPageCnt:4;		/* Word 4 */
3972 		uint32_t	CqRsvd1:4;
3973 		uint32_t	CqeSize:4;
3974 		uint32_t	CqRsvd2:2;
3975 		uint32_t	CQV:2;			/* queue version */
3976 		uint32_t	CqPageSize:8;
3977 		uint32_t	CqeCntMethod:4;
3978 		uint32_t	CqRsvd3:3;
3979 		uint32_t	CqAV:1;			/* auto valid */
3980 
3981 		uint32_t	CqeCntMask:16;		/* Word 5 */
3982 		uint32_t	CqRsvd4:16;
3983 
3984 		uint32_t	MqPageCnt:4;		/* Word 6 */
3985 		uint32_t	MqRsvd1:10;
3986 		uint32_t	MQV:2;			/* queue version */
3987 		uint32_t	MqPageSize:8;
3988 		uint32_t	MqeCntMethod:4;
3989 		uint32_t	MqRsvd2:4;
3990 
3991 		uint32_t	MqeCntMask:16;		/* Word 7 */
3992 		uint32_t	MqRsvd3:16;
3993 
3994 		uint32_t	WqPageCnt:4;		/* Word 8 */
3995 		uint32_t	WqRsvd1:4;
3996 		uint32_t	WqeSize:4;
3997 		uint32_t	WqeRsvd2:2;
3998 		uint32_t	WQV:2;
3999 		uint32_t	WqPageSize:8;
4000 		uint32_t	WqeCntMethod:4;
4001 		uint32_t	WqRsvd3:4;
4002 
4003 		uint32_t	WqeCntMask:16;		/* Word 9 */
4004 		uint32_t	WqRsvd4:16;
4005 
4006 		uint32_t	RqPageCnt:4;		/* Word 10 */
4007 		uint32_t	RqRsvd1:4;
4008 		uint32_t	RqeSize:4;
4009 		uint32_t	RqeRsvd2:2;
4010 		uint32_t	RQV:2;			/* queue version */
4011 		uint32_t	RqPageSize:8;
4012 		uint32_t	RqeCntMethod:4;
4013 		uint32_t	RqRsvd3:4;
4014 
4015 		uint32_t	RqeCntMask:16;		/* Word 11 */
4016 		uint32_t	RqRsvd4:12;
4017 		uint32_t	RqDbWin:4;
4018 
4019 		uint32_t	FCOE:1;			/* Word 12 */
4020 		uint32_t	EXT:1;
4021 		uint32_t	HDRR:1;			/* hdr_template_req */
4022 		uint32_t	SGLR:1;			/* sgl_pre_reg_requi */
4023 		uint32_t	FBRR:1;
4024 		uint32_t	AREG:1;			/* auto_reg */
4025 		uint32_t	TGT:1;
4026 		uint32_t	TERP:1;
4027 		uint32_t	ASSI:1;
4028 		uint32_t	MWQE:1;
4029 		uint32_t	TCCA:1;
4030 		uint32_t	TRTY:1;
4031 		uint32_t	TRIR:1;
4032 		uint32_t	PHOFF:1;
4033 		uint32_t	PHON:1;			/* perf_hint */
4034 		uint32_t	PHWQ:1; 		/* perf_wq_id_assoc */
4035 
4036 		uint32_t	boundary_4ga:1;
4037 		uint32_t	rxc:1;
4038 		uint32_t	hlm:1;
4039 		uint32_t	ipr:1;
4040 		uint32_t	rxri:1;
4041 		uint32_t	sglc:1;  /* skyhawk SGL chaining_capable */
4042 		uint32_t	timm:1;  /* t10_dif_inline_capable */
4043 		uint32_t	tsmm:1;  /* t10_dif_separate_capable */
4044 		uint32_t	:1;
4045 		uint32_t	oas:1;   /* OAS is supported */
4046 		uint32_t	lc:1;
4047 		uint32_t	agxf:1;			/* auto_xfer_rdy */
4048 
4049 		uint32_t	Loopback:4;
4050 
4051 		uint32_t	SgeLength;		/* Word 13 */
4052 
4053 		uint32_t	SglPageCnt:4;		/* Word 14 */
4054 		uint32_t	SglRsvd1:4;
4055 		uint32_t	SglPageSize:8;
4056 		uint32_t	SglAlign:8;
4057 		uint32_t	SglRsvd2:8;
4058 
4059 		uint32_t	MinRqSize:16;		/* Word 15 */
4060 		uint32_t	Rsvd5:16;
4061 
4062 		uint32_t	MaxRqSize;		/* Word 16 */
4063 
4064 		uint32_t	XRIMax:16;		/* Word 17 */
4065 		uint32_t	RPIMax:16;
4066 
4067 		uint32_t	VPIMax:16;		/* Word 18 */
4068 		uint32_t	VFIMax:16;
4069 
4070 		uint32_t	ext_embed_cb:1;		/* Word 19 */
4071 		uint32_t	mds_diags:1;
4072 		uint32_t	:1;
4073 		uint32_t	nvme:1;
4074 		uint32_t	xibi:1;
4075 		uint32_t	:1;
4076 		uint32_t	xpsgl:1;
4077 		uint32_t	:1;
4078 		uint32_t	eqdr:1;
4079 		uint32_t	nosr:1;
4080 		uint32_t	bv1s:1;
4081 		uint32_t	:1;
4082 		uint32_t	nsler:1;
4083 		uint32_t	pvl:1;
4084 		uint32_t	:6;
4085 		uint32_t	pbde:1;
4086 		uint32_t	:11;
4087 
4088 		uint32_t	frag_num_field_offset:16, /* Word 20 */
4089 				frag_num_field_size:16;
4090 		uint32_t	sgl_index_field_offset:16, /* Word 21 */
4091 				sgl_index_field_size:16;
4092 #endif
4093 		uint32_t	chain_sge_initial_value_lo;  /* Word 22 */
4094 		uint32_t	chain_sge_initial_value_hi;  /* Word 23 */
4095 
4096 		/* frag_field_offset, frag_field_size */
4097 		uint32_t	word24;
4098 
4099 		/* sgl_field_offset, sgl_field_size */
4100 		uint32_t	word25;
4101 		uint32_t	word26; /* Chain SGE initial value LOW  */
4102 		uint32_t	word27; /* Chain SGE initial value HIGH */
4103 } sli_params_t;
4104 
4105 /* SliFamily values */
4106 #define	SLI_FAMILY_BE2		0x0
4107 #define	SLI_FAMILY_BE3		0x1
4108 #define	SLI_FAMILY_LANCER_A	0xA
4109 #define	SLI_FAMILY_LANCER_B	0xB
4110 
4111 
4112 
4113 /* IOCTL_COMMON_SLI4_PARAMS */
4114 typedef	struct
4115 {
4116 	union
4117 	{
4118 		struct
4119 		{
4120 			uint32_t	Rsvd1;
4121 		} request;
4122 
4123 		struct
4124 		{
4125 			sli_params_t param;
4126 		} response;
4127 	} params;
4128 
4129 } IOCTL_COMMON_SLI4_PARAMS;
4130 
4131 
4132 #define	MAX_EXTENTS		16 /* 1 to 104 */
4133 
4134 /* IOCTL_COMMON_EXTENTS */
4135 typedef	struct
4136 {
4137 	union
4138 	{
4139 		struct
4140 		{
4141 #ifdef EMLXS_BIG_ENDIAN
4142 			uint16_t	RscCnt;
4143 			uint16_t	RscType;
4144 #endif
4145 #ifdef EMLXS_LITTLE_ENDIAN
4146 			uint16_t	RscType;
4147 			uint16_t	RscCnt;
4148 #endif
4149 		} request;
4150 
4151 		struct
4152 		{
4153 #ifdef EMLXS_BIG_ENDIAN
4154 			uint16_t	ExtentSize;
4155 			uint16_t	ExtentCnt;
4156 #endif
4157 #ifdef EMLXS_LITTLE_ENDIAN
4158 			uint16_t	ExtentCnt;
4159 			uint16_t	ExtentSize;
4160 #endif
4161 
4162 			uint16_t	RscId[MAX_EXTENTS];
4163 
4164 		} response;
4165 	} params;
4166 
4167 } IOCTL_COMMON_EXTENTS;
4168 
4169 /* RscType */
4170 #define	RSC_TYPE_FCOE_VFI	0x20
4171 #define	RSC_TYPE_FCOE_VPI	0x21
4172 #define	RSC_TYPE_FCOE_RPI	0x22
4173 #define	RSC_TYPE_FCOE_XRI	0x23
4174 
4175 
4176 
4177 /* IOCTL_COMMON_CQ_CREATE */
4178 typedef	struct
4179 {
4180 	union
4181 	{
4182 		struct
4183 		{
4184 #ifdef EMLXS_BIG_ENDIAN
4185 			uint16_t	Rsvd1;
4186 			uint16_t	NumPages;
4187 #endif
4188 #ifdef EMLXS_LITTLE_ENDIAN
4189 			uint16_t	NumPages;
4190 			uint16_t	Rsvd1;
4191 #endif
4192 			CQ_CONTEXT	CQContext;
4193 			BE_PHYS_ADDR	Pages[4];
4194 		} request;
4195 
4196 		struct
4197 		{
4198 #ifdef EMLXS_BIG_ENDIAN
4199 			uint16_t	Rsvd1;
4200 			uint16_t	CQId;
4201 #endif
4202 #ifdef EMLXS_LITTLE_ENDIAN
4203 			uint16_t	CQId;
4204 			uint16_t	Rsvd1;
4205 #endif
4206 		} response;
4207 	} params;
4208 
4209 } IOCTL_COMMON_CQ_CREATE;
4210 
4211 
4212 /* IOCTL_COMMON_CQ_CREATE_V2 */
4213 typedef	struct
4214 {
4215 	union
4216 	{
4217 		struct
4218 		{
4219 #ifdef EMLXS_BIG_ENDIAN
4220 			uint8_t		Rsvd1;
4221 			uint8_t		PageSize;
4222 			uint16_t	NumPages;
4223 #endif
4224 #ifdef EMLXS_LITTLE_ENDIAN
4225 			uint16_t	NumPages;
4226 			uint8_t		PageSize;
4227 			uint8_t		Rsvd1;
4228 #endif
4229 			CQ_CONTEXT_V2	CQContext;
4230 			BE_PHYS_ADDR	Pages[8];
4231 		} request;
4232 
4233 		struct
4234 		{
4235 #ifdef EMLXS_BIG_ENDIAN
4236 			uint16_t	Rsvd1;
4237 			uint16_t	CQId;
4238 #endif
4239 #ifdef EMLXS_LITTLE_ENDIAN
4240 			uint16_t	CQId;
4241 			uint16_t	Rsvd1;
4242 #endif
4243 		} response;
4244 	} params;
4245 
4246 } IOCTL_COMMON_CQ_CREATE_V2;
4247 
4248 #define	CQ_PAGE_SIZE_4K		0x01
4249 #define	CQ_PAGE_SIZE_8K		0x02
4250 #define	CQ_PAGE_SIZE_16K	0x04
4251 #define	CQ_PAGE_SIZE_32K	0x08
4252 #define	CQ_PAGE_SIZE_64K	0x10
4253 
4254 
4255 
4256 /* IOCTL_COMMON_MQ_CREATE */
4257 typedef	struct
4258 {
4259 	union
4260 	{
4261 		struct
4262 		{
4263 #ifdef EMLXS_BIG_ENDIAN
4264 			uint16_t	Rsvd1;
4265 			uint16_t	NumPages;
4266 #endif
4267 #ifdef EMLXS_LITTLE_ENDIAN
4268 			uint16_t	NumPages;
4269 			uint16_t	Rsvd1;
4270 #endif
4271 			MQ_CONTEXT	MQContext;
4272 			BE_PHYS_ADDR	Pages[8];
4273 		} request;
4274 
4275 		struct
4276 		{
4277 #ifdef EMLXS_BIG_ENDIAN
4278 			uint16_t	Rsvd1;
4279 			uint16_t	MQId;
4280 #endif
4281 #ifdef EMLXS_LITTLE_ENDIAN
4282 			uint16_t	MQId;
4283 			uint16_t	Rsvd1;
4284 #endif
4285 		} response;
4286 	} params;
4287 
4288 } IOCTL_COMMON_MQ_CREATE;
4289 
4290 
4291 /* IOCTL_COMMON_MQ_CREATE_EXT */
4292 typedef	struct
4293 {
4294 	union
4295 	{
4296 		struct
4297 		{
4298 #ifdef EMLXS_BIG_ENDIAN
4299 			uint16_t	rsvd0;
4300 			uint16_t	num_pages;
4301 #endif
4302 #ifdef EMLXS_LITTLE_ENDIAN
4303 			uint16_t	num_pages;
4304 			uint16_t	rsvd0;
4305 #endif
4306 			uint32_t	async_event_bitmap;
4307 
4308 #define	ASYNC_LINK_EVENT	0x00000002
4309 #define	ASYNC_FCF_EVENT		0x00000004
4310 #define	ASYNC_DCBX_EVENT	0x00000008
4311 #define	ASYNC_iSCSI_EVENT	0x00000010
4312 #define	ASYNC_GROUP5_EVENT	0x00000020
4313 #define	ASYNC_FC_EVENT		0x00010000
4314 #define	ASYNC_PORT_EVENT	0x00020000
4315 #define	ASYNC_VF_EVENT		0x00040000
4316 #define	ASYNC_MR_EVENT		0x00080000
4317 
4318 			MQ_CONTEXT	context;
4319 			BE_PHYS_ADDR	pages[8];
4320 		} request;
4321 
4322 		struct
4323 		{
4324 #ifdef EMLXS_BIG_ENDIAN
4325 			uint16_t	rsvd0;
4326 			uint16_t	MQId;
4327 #endif
4328 #ifdef EMLXS_LITTLE_ENDIAN
4329 			uint16_t	MQId;
4330 			uint16_t	rsvd0;
4331 #endif
4332 		} response;
4333 
4334 	} params;
4335 
4336 } IOCTL_COMMON_MQ_CREATE_EXT;
4337 
4338 
4339 /* IOCTL_COMMON_MQ_CREATE_EXT_V1 */
4340 typedef	struct
4341 {
4342 	union
4343 	{
4344 		struct
4345 		{
4346 #ifdef EMLXS_BIG_ENDIAN
4347 			uint16_t	CQId;
4348 			uint16_t	num_pages;
4349 #endif
4350 #ifdef EMLXS_LITTLE_ENDIAN
4351 			uint16_t	num_pages;
4352 			uint16_t	CQId;
4353 #endif
4354 			uint32_t	async_event_bitmap;
4355 
4356 			MQ_CONTEXT_V1	context;
4357 			BE_PHYS_ADDR	pages[8];
4358 		} request;
4359 
4360 		struct
4361 		{
4362 #ifdef EMLXS_BIG_ENDIAN
4363 			uint16_t	rsvd0;
4364 			uint16_t	MQId;
4365 #endif
4366 #ifdef EMLXS_LITTLE_ENDIAN
4367 			uint16_t	MQId;
4368 			uint16_t	rsvd0;
4369 #endif
4370 		} response;
4371 
4372 	} params;
4373 
4374 } IOCTL_COMMON_MQ_CREATE_EXT_V1;
4375 
4376 
4377 /* IOCTL_FCOE_RQ_CREATE */
4378 typedef	struct
4379 {
4380 	union
4381 	{
4382 		struct
4383 		{
4384 #ifdef EMLXS_BIG_ENDIAN
4385 			uint16_t	Rsvd0;
4386 			uint16_t	NumPages;
4387 #endif
4388 #ifdef EMLXS_LITTLE_ENDIAN
4389 			uint16_t	NumPages;
4390 			uint16_t	Rsvd0;
4391 #endif
4392 			RQ_CONTEXT	RQContext;
4393 			BE_PHYS_ADDR	Pages[8];
4394 		} request;
4395 
4396 		struct
4397 		{
4398 #ifdef EMLXS_BIG_ENDIAN
4399 			uint16_t	Rsvd1;
4400 			uint16_t	RQId;
4401 #endif
4402 #ifdef EMLXS_LITTLE_ENDIAN
4403 			uint16_t	RQId;
4404 			uint16_t	Rsvd1;
4405 #endif
4406 		} response;
4407 
4408 	} params;
4409 
4410 } IOCTL_FCOE_RQ_CREATE;
4411 
4412 
4413 /* IOCTL_FCOE_RQ_CREATE_V1 */
4414 typedef	struct
4415 {
4416 	union
4417 	{
4418 		struct
4419 		{
4420 #ifdef EMLXS_BIG_ENDIAN
4421 			uint32_t 	DNB:1;
4422 			uint32_t 	DFD:1;
4423 			uint32_t 	DIM:1;
4424 			uint32_t	Rsvd0:13;
4425 			uint32_t	NumPages:16;
4426 #endif
4427 #ifdef EMLXS_LITTLE_ENDIAN
4428 			uint32_t	NumPages:16;
4429 			uint32_t	Rsvd0:13;
4430 			uint32_t 	DIM:1;
4431 			uint32_t 	DFD:1;
4432 			uint32_t 	DNB:1;
4433 #endif
4434 			RQ_CONTEXT_V1	RQContext;
4435 			BE_PHYS_ADDR	Pages[8];
4436 		} request;
4437 
4438 		struct
4439 		{
4440 #ifdef EMLXS_BIG_ENDIAN
4441 			uint16_t	Rsvd1;
4442 			uint16_t	RQId;
4443 #endif
4444 #ifdef EMLXS_LITTLE_ENDIAN
4445 			uint16_t	RQId;
4446 			uint16_t	Rsvd1;
4447 #endif
4448 		} response;
4449 
4450 	} params;
4451 
4452 } IOCTL_FCOE_RQ_CREATE_V1;
4453 
4454 
4455 /* IOCTL_FCOE_WQ_CREATE */
4456 typedef	struct
4457 {
4458 	union
4459 	{
4460 		struct
4461 		{
4462 #ifdef EMLXS_BIG_ENDIAN
4463 			uint16_t	CQId;
4464 			uint16_t	NumPages;
4465 #endif
4466 #ifdef EMLXS_LITTLE_ENDIAN
4467 			uint16_t	NumPages;
4468 			uint16_t	CQId;
4469 #endif
4470 			BE_PHYS_ADDR	Pages[4];
4471 		} request;
4472 
4473 		struct
4474 		{
4475 #ifdef EMLXS_BIG_ENDIAN
4476 			uint16_t	Rsvd0;
4477 			uint16_t	WQId;
4478 #endif
4479 #ifdef EMLXS_LITTLE_ENDIAN
4480 			uint16_t	WQId;
4481 			uint16_t	Rsvd0;
4482 #endif
4483 		} response;
4484 
4485 	} params;
4486 
4487 } IOCTL_FCOE_WQ_CREATE;
4488 
4489 
4490 /* IOCTL_FCOE_WQ_CREATE_V1 */
4491 typedef	struct
4492 {
4493 	union
4494 	{
4495 		struct
4496 		{
4497 #ifdef EMLXS_BIG_ENDIAN
4498 			uint16_t	CQId;
4499 			uint16_t	NumPages;
4500 
4501 			uint32_t	WqeCnt:16;
4502 			uint32_t	Rsvd1:4;
4503 			uint32_t	WqeSize:4;
4504 			uint32_t	PageSize:8;
4505 #endif
4506 #ifdef EMLXS_LITTLE_ENDIAN
4507 			uint16_t	NumPages;
4508 			uint16_t	CQId;
4509 
4510 			uint32_t	PageSize:8;
4511 			uint32_t	WqeSize:4;
4512 			uint32_t	Rsvd1:4;
4513 			uint32_t	WqeCnt:16;
4514 #endif
4515 			uint32_t	Rsvd:2;
4516 			BE_PHYS_ADDR	Pages[4];
4517 		} request;
4518 
4519 		struct
4520 		{
4521 #ifdef EMLXS_BIG_ENDIAN
4522 			uint16_t	Rsvd0;
4523 			uint16_t	WQId;
4524 #endif
4525 #ifdef EMLXS_LITTLE_ENDIAN
4526 			uint16_t	WQId;
4527 			uint16_t	Rsvd0;
4528 #endif
4529 		} response;
4530 
4531 	} params;
4532 
4533 } IOCTL_FCOE_WQ_CREATE_V1;
4534 
4535 /* WqeSize */
4536 #define	WQE_SIZE_64_BYTES	0x05
4537 #define	WQE_SIZE_128_BYTES	0x06
4538 
4539 /* PageSize */
4540 #define	WQ_PAGE_SIZE_4K		0x01
4541 #define	WQ_PAGE_SIZE_8K		0x02
4542 #define	WQ_PAGE_SIZE_16K	0x04
4543 #define	WQ_PAGE_SIZE_32K	0x08
4544 #define	WQ_PAGE_SIZE_64K	0x10
4545 
4546 
4547 
4548 /* IOCTL_FCOE_CFG_POST_SGL_PAGES */
4549 typedef	struct _FCOE_SGL_PAGES
4550 {
4551 	BE_PHYS_ADDR	sgl_page0;	/* 1st page per XRI */
4552 	BE_PHYS_ADDR	sgl_page1;	/* 2nd page per XRI */
4553 
4554 } FCOE_SGL_PAGES;
4555 
4556 typedef	struct
4557 {
4558 	union
4559 	{
4560 		struct
4561 		{
4562 #ifdef EMLXS_BIG_ENDIAN
4563 			uint16_t	xri_count;
4564 			uint16_t	xri_start;
4565 #endif
4566 #ifdef EMLXS_LITTLE_ENDIAN
4567 			uint16_t	xri_start;
4568 			uint16_t	xri_count;
4569 #endif
4570 			FCOE_SGL_PAGES	pages[1];
4571 		} request;
4572 
4573 		struct
4574 		{
4575 			uint32_t	rsvd0;
4576 		} response;
4577 
4578 	} params;
4579 
4580 	uint32_t	rsvd0[2];
4581 
4582 } IOCTL_FCOE_CFG_POST_SGL_PAGES;
4583 
4584 
4585 /* IOCTL_FCOE_POST_HDR_TEMPLATES */
4586 typedef struct _IOCTL_FCOE_POST_HDR_TEMPLATES
4587 {
4588 	union
4589 	{
4590 		struct
4591 		{
4592 #ifdef EMLXS_BIG_ENDIAN
4593 			uint16_t	num_pages;
4594 			uint16_t	rpi_offset;
4595 #endif
4596 #ifdef EMLXS_LITTLE_ENDIAN
4597 			uint16_t	rpi_offset;
4598 			uint16_t	num_pages;
4599 #endif
4600 			BE_PHYS_ADDR	pages[32];
4601 
4602 		}request;
4603 
4604 	}params;
4605 
4606 } IOCTL_FCOE_POST_HDR_TEMPLATES;
4607 
4608 
4609 
4610 #define	EMLXS_IOCTL_DCBX_MODE_CEE	0	/* Mapped to FIP mode */
4611 #define	EMLXS_IOCTL_DCBX_MODE_CIN	1	/* Mapped to nonFIP mode */
4612 
4613 /* IOCTL_DCBX_GET_DCBX_MODE */
4614 typedef struct _IOCTL_DCBX_GET_DCBX_MODE
4615 {
4616 	union
4617 	{
4618 		struct
4619 		{
4620 #ifdef EMLXS_BIG_ENDIAN
4621 			uint8_t		rsvd0[3];
4622 			uint8_t		port_num;
4623 #endif
4624 #ifdef EMLXS_LITTLE_ENDIAN
4625 			uint8_t		port_num;
4626 			uint8_t		rsvd0[3];
4627 #endif
4628 		} request;
4629 
4630 		struct
4631 		{
4632 #ifdef EMLXS_BIG_ENDIAN
4633 			uint8_t		rsvd1[3];
4634 			uint8_t		dcbx_mode;
4635 #endif
4636 #ifdef EMLXS_LITTLE_ENDIAN
4637 			uint8_t		dcbx_mode;
4638 			uint8_t		rsvd1[3];
4639 #endif
4640 		} response;
4641 
4642 	} params;
4643 
4644 } IOCTL_DCBX_GET_DCBX_MODE;
4645 
4646 
4647 /* IOCTL_DCBX_SET_DCBX_MODE */
4648 typedef struct _IOCTL_DCBX_SET_DCBX_MODE
4649 {
4650 	union
4651 	{
4652 		struct
4653 		{
4654 #ifdef EMLXS_BIG_ENDIAN
4655 			uint8_t		rsvd0[2];
4656 			uint8_t		dcbx_mode;
4657 			uint8_t		port_num;
4658 #endif
4659 #ifdef EMLXS_LITTLE_ENDIAN
4660 			uint8_t		port_num;
4661 			uint8_t		dcbx_mode;
4662 			uint8_t		rsvd0[2];
4663 #endif
4664 		} request;
4665 
4666 		struct
4667 		{
4668 			uint32_t	rsvd1;
4669 		} response;
4670 
4671 	} params;
4672 
4673 } IOCTL_DCBX_SET_DCBX_MODE;
4674 
4675 
4676 /* IOCTL_COMMON_GET_CNTL_ATTRIB */
4677 typedef	struct
4678 {
4679 	char		flashrom_version_string[32];
4680 	char		manufacturer_name[32];
4681 	char		rsvd0[28];
4682 	uint32_t	default_extended_timeout;
4683 	char		controller_model_number[32];
4684 	char		controller_description[64];
4685 	char		controller_serial_number[32];
4686 	char		ip_version_string[32];
4687 	char		firmware_version_string[32];
4688 	char		bios_version_string[32];
4689 	char		redboot_version_string[32];
4690 	char		driver_version_string[32];
4691 	char		fw_on_flash_version_string[32];
4692 	uint32_t	functionalities_supported;
4693 	uint16_t	max_cdblength;
4694 	uint8_t		asic_revision;
4695 	uint8_t		generational_guid[16];
4696 	uint8_t		hba_port_count;
4697 	uint16_t	default_link_down_timeout;
4698 	uint8_t		iscsi_ver_min_max;
4699 	uint8_t		multifunction_device;
4700 	uint8_t		cache_valid;
4701 	uint8_t		hba_status;
4702 	uint8_t		max_domains_supported;
4703 	uint8_t		phy_port;
4704 	uint32_t	firmware_post_status;
4705 	uint32_t	hba_mtu[2];
4706 
4707 } MGMT_HBA_ATTRIB;
4708 
4709 typedef	struct
4710 {
4711 	MGMT_HBA_ATTRIB		hba_attribs;
4712 	uint16_t		pci_vendor_id;
4713 	uint16_t		pci_device_id;
4714 	uint16_t		pci_sub_vendor_id;
4715 	uint16_t		pci_sub_system_id;
4716 	uint8_t			pci_bus_number;
4717 	uint8_t			pci_device_number;
4718 	uint8_t			pci_function_number;
4719 	uint8_t			interface_type;
4720 	uint64_t		unique_identifier;
4721 
4722 } MGMT_CONTROLLER_ATTRIB;
4723 
4724 typedef	struct
4725 {
4726 	union
4727 	{
4728 		struct
4729 		{
4730 			uint32_t rsvd0;
4731 		} request;
4732 
4733 		struct
4734 		{
4735 			MGMT_CONTROLLER_ATTRIB cntl_attributes_info;
4736 		} response;
4737 
4738 	} params;
4739 
4740 } IOCTL_COMMON_GET_CNTL_ATTRIB;
4741 
4742 
4743 typedef	union
4744 {
4745 	IOCTL_COMMON_NOP		NOPVar;
4746 	IOCTL_FCOE_WQ_CREATE		WQCreateVar;
4747 	IOCTL_FCOE_WQ_CREATE_V1		WQCreateVar1;
4748 	IOCTL_FCOE_RQ_CREATE		RQCreateVar;
4749 	IOCTL_FCOE_RQ_CREATE_V1		RQCreateVar1;
4750 	IOCTL_COMMON_EQ_CREATE		EQCreateVar;
4751 	IOCTL_COMMON_CQ_CREATE		CQCreateVar;
4752 	IOCTL_COMMON_CQ_CREATE_V2	CQCreateVar2;
4753 	IOCTL_COMMON_MQ_CREATE		MQCreateVar;
4754 	IOCTL_COMMON_MQ_CREATE_EXT	MQCreateExtVar;
4755 	IOCTL_COMMON_MQ_CREATE_EXT_V1	MQCreateExtVar1;
4756 	IOCTL_FCOE_CFG_POST_SGL_PAGES	PostSGLVar;
4757 	IOCTL_COMMON_GET_CNTL_ATTRIB	GetCntlAttributesVar;
4758 	IOCTL_FCOE_READ_FCF_TABLE	ReadFCFTableVar;
4759 	IOCTL_FCOE_ADD_FCF_TABLE	AddFCFTableVar;
4760 	IOCTL_FCOE_REDISCOVER_FCF_TABLE	RediscoverFCFTableVar;
4761 	IOCTL_COMMON_FLASHROM		FlashRomVar;
4762 	IOCTL_COMMON_MANAGE_FAT		FATVar;
4763 	IOCTL_DCBX_GET_DCBX_MODE	GetDCBX;
4764 	IOCTL_DCBX_SET_DCBX_MODE	SetDCBX;
4765 	IOCTL_COMMON_SLI4_PARAMS	Sli4ParamVar;
4766 	IOCTL_COMMON_EXTENTS		ExtentsVar;
4767 	IOCTL_COMMON_GET_PHY_DETAILS	PHYDetailsVar;
4768 	IOCTL_COMMON_GET_PORT_NAME	PortNameVar;
4769 	IOCTL_COMMON_GET_PORT_NAME_V1	PortNameVar1;
4770 	IOCTL_COMMON_WRITE_OBJECT	WriteObjVar;
4771 	IOCTL_COMMON_BOOT_CFG		BootCfgVar;
4772 
4773 } IOCTL_VARIANTS;
4774 
4775 /* Structure for MB Command SLI_CONFIG(0x9b) */
4776 /* Good for SLI4 only */
4777 
4778 typedef struct
4779 {
4780 	be_req_hdr_t	be;
4781 	BE_PHYS_ADDR	payload;
4782 } SLI_CONFIG_VAR;
4783 
4784 #define	IOCTL_HEADER_SZ	(4 * sizeof (uint32_t))
4785 
4786 
4787 typedef union
4788 {
4789 	uint32_t		varWords[63];
4790 	READ_NV_VAR		varRDnvp;	/* cmd = x02 (READ_NVPARMS) */
4791 	INIT_LINK_VAR		varInitLnk;	/* cmd = x05 (INIT_LINK) */
4792 	CONFIG_LINK		varCfgLnk;	/* cmd = x07 (CONFIG_LINK) */
4793 	READ_REV4_VAR		varRdRev4;	/* cmd = x11 (READ_REV) */
4794 	READ_LNK_VAR		varRdLnk;	/* cmd = x12 (READ_LNK_STAT) */
4795 	DUMP4_VAR		varDmp4;	/* cmd = x17 (DUMP) */
4796 	UPDATE_CFG_VAR		varUpdateCfg;	/* cmd = x1b (update Cfg) */
4797 	BIU_DIAG_VAR		varBIUdiag;	/* cmd = x84 (RUN_BIU_DIAG64) */
4798 	READ_SPARM_VAR		varRdSparm;	/* cmd = x8D (READ_SPARM64) */
4799 	REG_FCFI_VAR		varRegFCFI;	/* cmd = xA0 (REG_FCFI) */
4800 	UNREG_FCFI_VAR		varUnRegFCFI;	/* cmd = xA2 (UNREG_FCFI) */
4801 	READ_LA_VAR		varReadLA;	/* cmd = x95 (READ_LA64) */
4802 	READ_CONFIG4_VAR	varRdConfig4;	/* cmd = x0B (READ_CONFIG) */
4803 	RESUME_RPI_VAR		varResumeRPI;	/* cmd = x9E (RESUME_RPI) */
4804 	REG_LOGIN_VAR		varRegLogin;	/* cmd = x93 (REG_RPI) */
4805 	UNREG_LOGIN_VAR		varUnregLogin;	/* cmd = x14 (UNREG_RPI) */
4806 	REG_VPI_VAR		varRegVPI4;	/* cmd = x96 (REG_VPI) */
4807 	UNREG_VPI_VAR4		varUnRegVPI4;	/* cmd = x97 (UNREG_VPI) */
4808 	REG_VFI_VAR		varRegVFI4;	/* cmd = x9F (REG_VFI) */
4809 	UNREG_VFI_VAR		varUnRegVFI4;	/* cmd = xA1 (UNREG_VFI) */
4810 	REQUEST_FEATURES_VAR	varReqFeatures;	/* cmd = x9D (REQ_FEATURES) */
4811 	SLI_CONFIG_VAR		varSLIConfig;	/* cmd = x9B (SLI_CONFIG) */
4812 	INIT_VPI_VAR		varInitVPI4;	/* cmd = xA3 (INIT_VPI) */
4813 	INIT_VFI_VAR		varInitVFI4;	/* cmd = xA4 (INIT_VFI) */
4814 
4815 } MAILVARIANTS4;		/* Used for SLI-4 */
4816 
4817 #define	MAILBOX_CMD_SLI4_BSIZE	256
4818 #define	MAILBOX_CMD_SLI4_WSIZE	64
4819 
4820 #define	MAILBOX_CMD_MAX_BSIZE	256
4821 #define	MAILBOX_CMD_MAX_WSIZE	64
4822 
4823 
4824 typedef volatile struct
4825 {
4826 #ifdef EMLXS_BIG_ENDIAN
4827 	uint16_t	mbxStatus;
4828 	uint8_t		mbxCommand;
4829 	uint8_t		mbxReserved:6;
4830 	uint8_t		mbxHc:1;
4831 	uint8_t		mbxOwner:1;	/* Low order bit first word */
4832 #endif
4833 #ifdef EMLXS_LITTLE_ENDIAN
4834 	uint8_t		mbxOwner:1;	/* Low order bit first word */
4835 	uint8_t		mbxHc:1;
4836 	uint8_t		mbxReserved:6;
4837 	uint8_t		mbxCommand;
4838 	uint16_t	mbxStatus;
4839 #endif
4840 	MAILVARIANTS4	un;		/* 252 bytes */
4841 } MAILBOX4;				/* Used for SLI-4 */
4842 
4843 /*
4844  * End Structure Definitions for Mailbox Commands
4845  */
4846 
4847 
4848 typedef struct emlxs_mbq
4849 {
4850 	volatile uint32_t	mbox[MAILBOX_CMD_MAX_WSIZE];
4851 	struct emlxs_mbq	*next;
4852 
4853 	/* Defferred handling pointers */
4854 	void			*nonembed;	/* ptr to data buffer */
4855 						/* structure */
4856 	void			*bp;		/* ptr to data buffer */
4857 						/* structure */
4858 	void			*sbp;		/* ptr to emlxs_buf_t */
4859 						/* structure */
4860 	void			*ubp;		/* ptr to fc_unsol_buf_t */
4861 						/* structure */
4862 	void			*iocbq;		/* ptr to IOCBQ structure */
4863 	void			*context;	/* ptr to mbox context data */
4864 	void			*port;		/* Sending port */
4865 	uint32_t		flag;
4866 
4867 #define	MBQ_POOL_ALLOCATED	0x00000001
4868 #define	MBQ_PASSTHRU		0x00000002
4869 #define	MBQ_EMBEDDED		0x00000004
4870 #define	MBQ_BOOTSTRAP		0x00000008
4871 #define	MBQ_COMPLETED		0x00010000	/* Used for MBX_SLEEP */
4872 #define	MBQ_INIT_MASK		0x0000ffff
4873 
4874 #ifdef MBOX_EXT_SUPPORT
4875 	uint8_t			*extbuf;	/* ptr to mailbox ext buffer */
4876 	uint32_t		extsize;	/* size of mailbox ext buffer */
4877 #endif /* MBOX_EXT_SUPPORT */
4878 	uint32_t		(*mbox_cmpl)();
4879 } emlxs_mbq_t;
4880 typedef emlxs_mbq_t MAILBOXQ;
4881 
4882 
4883 /* We currently do not support IOCBs in SLI1 mode */
4884 typedef struct
4885 {
4886 	MAILBOX		mbx;
4887 #ifdef MBOX_EXT_SUPPORT
4888 	uint8_t		mbxExt[MBOX_EXTENSION_SIZE];
4889 #endif /* MBOX_EXT_SUPPORT */
4890 	uint8_t		pad[(SLI_SLIM1_SIZE -
4891 				(sizeof (MAILBOX) + MBOX_EXTENSION_SIZE))];
4892 } SLIM1;
4893 
4894 
4895 typedef struct
4896 {
4897 	MAILBOX		mbx;
4898 #ifdef MBOX_EXT_SUPPORT
4899 	uint8_t		mbxExt[MBOX_EXTENSION_SIZE];
4900 #endif /* MBOX_EXT_SUPPORT */
4901 	PCB		pcb;
4902 	uint8_t		IOCBs[SLI_IOCB_MAX_SIZE];
4903 } SLIM2;
4904 
4905 
4906 /* def for new 2MB Flash (Pegasus ...) */
4907 #define	MBX_LOAD_AREA		0x81
4908 #define	MBX_LOAD_EXP_ROM	0x9C
4909 
4910 #define	FILE_TYPE_AWC		0xE1A01001
4911 #define	FILE_TYPE_DWC		0xE1A02002
4912 #define	FILE_TYPE_BWC		0xE1A03003
4913 
4914 #define	AREA_ID_MASK		0xFFFFFF0F
4915 #define	AREA_ID_AWC		0x00000001
4916 #define	AREA_ID_DWC		0x00000002
4917 #define	AREA_ID_BWC		0x00000003
4918 
4919 #define	CMD_START_ERASE		1
4920 #define	CMD_CONTINUE_ERASE	2
4921 #define	CMD_DOWNLOAD		3
4922 #define	CMD_END_DOWNLOAD	4
4923 
4924 #define	RSP_ERASE_STARTED	1
4925 #define	RSP_ERASE_COMPLETE	2
4926 #define	RSP_DOWNLOAD_MORE	3
4927 #define	RSP_DOWNLOAD_DONE	4
4928 
4929 #define	EROM_CMD_FIND_IMAGE	8
4930 #define	EROM_CMD_CONTINUE_ERASE	9
4931 #define	EROM_CMD_COPY		10
4932 
4933 #define	EROM_RSP_ERASE_STARTED	8
4934 #define	EROM_RSP_ERASE_COMPLETE	9
4935 #define	EROM_RSP_COPY_MORE	10
4936 #define	EROM_RSP_COPY_DONE	11
4937 
4938 #define	ALLext			1
4939 #define	DWCext			2
4940 #define	BWCext			3
4941 
4942 #define	NO_ALL			0
4943 #define	ALL_WITHOUT_BWC		1
4944 #define	ALL_WITH_BWC		2
4945 
4946 #define	KERNEL_START_ADDRESS	0x000000
4947 #define	DOWNLOAD_START_ADDRESS	0x040000
4948 #define	EXP_ROM_START_ADDRESS	0x180000
4949 #define	SCRATCH_START_ADDRESS	0x1C0000
4950 #define	CONFIG_START_ADDRESS	0x1E0000
4951 
4952 
4953 typedef struct SliAifHdr
4954 {
4955 	uint32_t	CompressBr;
4956 	uint32_t	RelocBr;
4957 	uint32_t	ZinitBr;
4958 	uint32_t	EntryBr;
4959 	uint32_t	Area_ID;
4960 	uint32_t	RoSize;
4961 	uint32_t	RwSize;
4962 	uint32_t	DbgSize;
4963 	uint32_t	ZinitSize;
4964 	uint32_t	DbgType;
4965 	uint32_t	ImageBase;
4966 	uint32_t	Area_Size;
4967 	uint32_t	AddressMode;
4968 	uint32_t	DataBase;
4969 	uint32_t	AVersion;
4970 	uint32_t	Spare2;
4971 	uint32_t	DebugSwi;
4972 	uint32_t	ZinitCode[15];
4973 } AIF_HDR, *PAIF_HDR;
4974 
4975 typedef struct ImageHdr
4976 {
4977 	uint32_t	BlockSize;
4978 	PROG_ID		Id;
4979 	uint32_t	Flags;
4980 	uint32_t	EntryAdr;
4981 	uint32_t	InitAdr;
4982 	uint32_t	ExitAdr;
4983 	uint32_t	ImageBase;
4984 	uint32_t	ImageSize;
4985 	uint32_t	ZinitSize;
4986 	uint32_t	RelocSize;
4987 	uint32_t	HdrCks;
4988 } IMAGE_HDR, *PIMAGE_HDR;
4989 
4990 
4991 
4992 typedef struct
4993 {
4994 	PROG_ID		prog_id;
4995 #ifdef EMLXS_BIG_ENDIAN
4996 	uint32_t	pci_cfg_rsvd:27;
4997 	uint32_t	use_hdw_def:1;
4998 	uint32_t	pci_cfg_sel:3;
4999 	uint32_t	pci_cfg_lookup_sel:1;
5000 #endif
5001 #ifdef EMLXS_LITTLE_ENDIAN
5002 	uint32_t	pci_cfg_lookup_sel:1;
5003 	uint32_t	pci_cfg_sel:3;
5004 	uint32_t	use_hdw_def:1;
5005 	uint32_t	pci_cfg_rsvd:27;
5006 #endif
5007 	union
5008 	{
5009 		PROG_ID		boot_bios_id;
5010 		uint32_t	boot_bios_wd[2];
5011 	} u0;
5012 	PROG_ID		sli1_prog_id;
5013 	PROG_ID		sli2_prog_id;
5014 	PROG_ID		sli3_prog_id;
5015 	PROG_ID		sli4_prog_id;
5016 	union
5017 	{
5018 		PROG_ID		EROM_prog_id;
5019 		uint32_t	EROM_prog_wd[2];
5020 	} u1;
5021 } WAKE_UP_PARMS, *PWAKE_UP_PARMS;
5022 
5023 
5024 #define	PROG_DESCR_STR_LEN	24
5025 #define	MAX_LOAD_ENTRY		32
5026 
5027 typedef struct
5028 {
5029 	uint32_t	next;
5030 	uint32_t	prev;
5031 	uint32_t	start_adr;
5032 	uint32_t	len;
5033 	union
5034 	{
5035 		PROG_ID		id;
5036 		uint32_t	wd[2];
5037 	} un;
5038 	uint8_t		prog_descr[PROG_DESCR_STR_LEN];
5039 } LOAD_ENTRY;
5040 
5041 typedef struct
5042 {
5043 	uint32_t	head;
5044 	uint32_t	tail;
5045 	uint32_t	entry_cnt;
5046 	LOAD_ENTRY	load_entry[MAX_LOAD_ENTRY];
5047 } LOAD_LIST;
5048 
5049 #ifdef	__cplusplus
5050 }
5051 #endif
5052 
5053 #endif	/* _EMLXS_MBOX_H */
5054