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Searched refs:DP_TP_CTL (Results 1 – 3 of 3) sorted by relevance

/gfx-drm/usr/src/uts/intel/io/i915/
H A Dintel_ddi.c206 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
249 I915_WRITE(DP_TP_CTL(PORT_E), in hsw_fdi_link_train()
264 temp = I915_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
268 POSTING_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
1083 val = I915_READ(DP_TP_CTL(port)); in intel_ddi_post_disable()
1086 I915_WRITE(DP_TP_CTL(port), val); in intel_ddi_post_disable()
1214 val = I915_READ(DP_TP_CTL(port)); in intel_ddi_prepare_link_retrain()
1217 I915_WRITE(DP_TP_CTL(port), val); in intel_ddi_prepare_link_retrain()
1218 POSTING_READ(DP_TP_CTL(port)); in intel_ddi_prepare_link_retrain()
1228 I915_WRITE(DP_TP_CTL(port), val); in intel_ddi_prepare_link_retrain()
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H A Dintel_dp.c1926 uint32_t temp = I915_READ(DP_TP_CTL(port)); in intel_dp_set_link_train()
1949 I915_WRITE(DP_TP_CTL(port), temp); in intel_dp_set_link_train()
2021 val = I915_READ(DP_TP_CTL(port)); in intel_dp_set_idle_link_train()
2024 I915_WRITE(DP_TP_CTL(port), val); in intel_dp_set_idle_link_train()
H A Di915_reg.h4875 #define DP_TP_CTL(port) _PORT(port, DP_TP_CTL_A, DP_TP_CTL_B) macro