1 /****************************************************************************
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  *
21  * Copyright 2014 QLogic Corporation
22  * The contents of this file are subject to the terms of the
23  * QLogic End User License (the "License").
24  * You may not use this file except in compliance with the License.
25  *
26  * You can obtain a copy of the License at
27  * http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/
28  * QLogic_End_User_Software_License.txt
29  * See the License for the specific language governing permissions
30  * and limitations under the License.
31  *
32  *
33  * Name:        nvm_map.h
34  *
35  * Description: Everest NVRAM map
36  *
37  * Created:     05/03/2006 eilong
38  *
39  * $Date: 2014/07/16 $       $Revision: #111 $
40  ****************************************************************************/
41 
42 #ifndef NVM_MAP_H
43 #define NVM_MAP_H
44 
45 #include "mcp_shmem.h"
46 #if !defined(MFW) && !defined(VMWARE)
47 #include "types.h"
48 #include "invm_cfg.h"
49 #define __FAR__ /*Need to define this as NULL, as it is defined in preboot make file*/
50 #include "fcb_nvm.h"
51 #endif
52 
53 #define CRC_MAGIC_VALUE                     0xDEBB20E3
54 #define CRC32_POLYNOMIAL                    0xEDB88320
55 
56 
57 /****************************************************************************
58  * Boot Strap Region                                                        *
59  ****************************************************************************/
60 typedef struct _bootstrap_region_t
61 {
62     u32_t magic_value;          /* a pattern not likely to occur randomly */
63         #define NVM_MAGIC_VALUE                             0x669955aa
64     u32_t sram_start_addr;      /* where to locate boot code (byte addr) */
65         #define NVM_DEFAULT_SRAM_ADDR                       0x08000010
66     u32_t code_len;             /* boot code length (in dwords) */
67     u32_t code_start_addr;      /* location of code on media (media byte addr) */
68     u32_t crc;                  /* 32-bit CRC */
69 } bootstrap_region_t;
70 
71 #if !defined(MFW) && !defined(VMWARE)
72 typedef struct {
73     NVM_ISCSI_CFG_BLOCK_V2 iscsi_cfg[4];
74     NVM_FCB_CFG_BLOCK fcoe_cfg[4];
75 } shadow_image_t;
76 #else
77 typedef struct {
78     u8_t iscsi_cfg[4][0x800];
79     u8_t fcoe_cfg[4][0x400];
80 } shadow_image_t;
81 #endif
82 
83 /****************************************************************************
84  * Directories Region                                                       *
85  ****************************************************************************/
86 typedef struct _code_entry_t
87 {
88     u32_t sram_start_addr;      /* Relative to the execution CPU, see code image
89                                    agent in code_attribute field */
90     u32_t code_attribute;
91         #define CODE_IMAGE_TYPE_MASK                        0xf0800003
92 
93         /* Images which are stored in extended dir have bit 0 set to 1 */
94         #define CODE_IMAGE_IN_EXTENDED_DIR_MASK             0x00000001
95 
96         #define CODE_IMAGE_TYPE_BC2                         0x00000000
97         #define CODE_IMAGE_TYPE_MBA                         0x10000000
98         #define CODE_IMAGE_TYPE_NC_SI_CMN                   0x20000000
99         #define CODE_IMAGE_TYPE_MODULES_PN                  0x30000000
100         #define CODE_IMAGE_TYPE_IPMI                        0x40000000
101         #define CODE_IMAGE_TYPE_ISCSI_BOOT_CFG2             0x50000000
102         #define CODE_IMAGE_TYPE_NC_SI_EVEREST               0x60000000
103         #define CODE_IMAGE_TYPE_L2T                         0x70000000
104         #define CODE_IMAGE_TYPE_L2C                         0x80000000
105         #define CODE_IMAGE_TYPE_L2X                         0x90000000
106         #define CODE_IMAGE_TYPE_L2U                         0xa0000000
107         #define CODE_IMAGE_TYPE_ISCSI_BOOT_CPRG             0xb0000000
108         #define CODE_IMAGE_TYPE_ISCSI_BOOT_CFG              0xc0000000
109         #define CODE_IMAGE_TYPE_ISCSI_BOOT                  0xd0000000
110         #define CODE_IMAGE_TYPE_FCOE_BOOT_CFG               0x10000001
111         #define CODE_IMAGE_TYPE_FCOE_BOOT                   0x20000001
112         #define CODE_IMAGE_TYPE_FCOE_BOOT_CFG2              0x30000001
113         #define CODE_IMAGE_TYPE_FCOE_BOOT_CPRG_EVRST        0x40000001
114         #define CODE_IMAGE_TYPE_NIC_PARTITION_CFG           0x50000001
115         #define CODE_IMAGE_TYPE_FCOE_BOOT_CFG3              0x60000001
116         #define CODE_IMAGE_TYPE_FCOE_BOOT_CFG4              0x70000001
117         #define CODE_IMAGE_TYPE_ISCSI_BOOT_CFG3             0x80000001
118         #define CODE_IMAGE_TYPE_ISCSI_BOOT_CFG4             0x90000001
119         #define CODE_IMAGE_TYPE_BOOT_CFG_SHADOW             0x10800001
120         #define CODE_IMAGE_TYPE_VPD                         0xa0000001
121         #define CODE_IMAGE_TYPE_E3_WC                       0xb0000001
122         #define CODE_IMAGE_TYPE_E3_PCIE                     0xc0000001
123         #define CODE_IMAGE_VNTAG_DATA                       0xd0000001
124         #define CODE_IMAGE_TYPE_SWIM1                       0xe0000001
125         #define CODE_IMAGE_TYPE_SWIM2                       0xf0000001
126         #define CODE_IMAGE_TYPE_SWIM3                       0x10000003
127         #define CODE_IMAGE_TYPE_MFW1                        0x20000003 /* Replace BC1 */
128         #define CODE_IMAGE_TYPE_MFW2                        0x30000003 /* Replace BC2 + NCSI */
129         #define CODE_IMAGE_TYPE_SWIM4                       0x40000003
130         #define CODE_IMAGE_TYPE_SWIM5                       0x50000003
131         #define CODE_IMAGE_TYPE_SWIM6                       0x60000003
132         #define CODE_IMAGE_TYPE_SWIM7                       0x70000003
133         #define CODE_IMAGE_TYPE_SWIM8                       0x80000003
134         #define CODE_IMAGE_TYPE_MFW2_A                      0x90000003
135         #define CODE_IMAGE_TYPE_OCNVM                       0xa0000003 /*ocnvm*/
136         #define CODE_IMAGE_VNTAG_PROFILES_DATA              0xd0000003
137         #define CODE_IMAGE_NVM_CFG_EXTENDED_SHARED          0xe0000003
138         #define CODE_IMAGE_TYPE_E3_WCV2                     0xf0000003 /*wc_v2*/
139         #define CODE_IMAGE_TYPE_E3_PCIEV2                   0x00800003 /*pcie_v2*/
140 
141         #define CODE_IMAGE_TYPE_CCM                         0x90800003
142 
143         /* for shaddow SWIMs feature */
144         #define CODE_IMAGE_TYPE_SWIM1_B                     0x10800003
145         #define CODE_IMAGE_TYPE_SWIM2_B                     0x20800003
146         #define CODE_IMAGE_TYPE_SWIM3_B                     0x30800003
147         #define CODE_IMAGE_TYPE_SWIM4_B                     0x40800003
148         #define CODE_IMAGE_TYPE_SWIM5_B                     0x50800003
149         #define CODE_IMAGE_TYPE_SWIM6_B                     0x60800003
150         #define CODE_IMAGE_TYPE_SWIM7_B                     0x70800003
151         #define CODE_IMAGE_TYPE_SWIM8_B                     0x80800003
152 
153         #define CODE_IMAGE_TYPE_CCM                         0x90800003
154         #define CODE_IMAGE_TYPE_HW_SET                      0xa0800003
155         #define CODE_IMAGE_TYPE_USR_BLK                     0xb0000003
156         #define CODE_IMAGE_TYPE_ISCSI_PERS                  0xc0000003
157 
158         /* next few groups of image: 0x90800003 -- 0xf0800003
159                                      0x00800001 -- 0xf0800001*/
160 
161         #define CODE_IMAGE_TYPE_EXTENDED_DIR                0xe0000000
162         #define CODE_IMAGE_TYPE_MAX                         0xf0000000
163         #define CODE_IMAGE_TYPE_BC1                         CODE_IMAGE_TYPE_MAX
164 
165         #define CODE_IMAGE_AGENT_TYPE_MASK                  0x0f000000
166         #define CODE_IMAGE_AGENT_NONE                       0x00000000
167         #define CODE_IMAGE_AGENT_HOST                       0x01000000
168         #define CODE_IMAGE_AGENT_MCP                        0x02000000
169         #define CODE_IMAGE_AGENT_TSTORM                     0x03000000
170         #define CODE_IMAGE_AGENT_CSTORM                     0x04000000
171         #define CODE_IMAGE_AGENT_XSTORM                     0x05000000
172         #define CODE_IMAGE_AGENT_USTORM                     0x06000000
173         #define CODE_IMAGE_AGENT_E3WC                       0x07000000
174         #define CODE_IMAGE_AGENT_E3PCIE                     0x08000000
175         #define CODE_IMAGE_AGENT_HOST_BCV                   0x09000000
176         #define CODE_IMAGE_TYPE_BDN                         0xc0800003
177 
178         #define CODE_IMAGE_LENGTH_MASK                      0x007ffffc
179 
180     u32_t nvm_start_addr;
181 } code_entry_t;
182 
183 #define CODE_ENTRY_MAX                      16
184 #define CODE_ENTRY_EXTENDED_DIR_IDX         15
185 #define MAX_IMAGES_IN_EXTENDED_DIR          64
186 #define MAX_SPARE_NUM_LENGTH                20
187 
188 /* version since which shadow feature is supported */
189 #define MFW_SHADOW_FEATURE_SUPPORTED_MAJOR 7
190 #define MFW_SHADOW_FEATURE_SUPPORTED_MINOR 0
191 #define MFW_SHADOW_FEATURE_SUPPORTED_BUILD 24
192 
193 typedef struct _dir_t
194 {
195     code_entry_t code[CODE_ENTRY_MAX];
196     u32_t unused[5];            /* Must be all zeroes */
197     u8_t spare_part_num[MAX_SPARE_NUM_LENGTH];
198                                 /* Similar to the part number in VPD */
199     u32_t crc;
200 } dir_t;
201 
202 /****************************************************************************
203  * Manufacturing Information Region                                         *
204  ****************************************************************************/
205 typedef struct _manuf_info_t
206 {                                                     /* NVM Offset  (size) */
207     u32_t length;                                     /* 0x100 */
208         #define MANUF_INFO_FORMAT_REV_ID                    ('A'<<24)
209         #define MANUF_INFO_FORMAT_REV_MASK                  0xff000000
210         #define MANUF_INFO_LENGTH_MASK                      0x0000ffff
211         #define MANUF_INFO_LENGTH                           0x00000000
212 
213     shared_hw_cfg_t shared_hw_config;                 /* 0x104      (0x128) */
214     port_hw_cfg_t port_hw_config[PORT_MAX];           /* 0x12c(400*2=0x320) */
215     u32_t crc;                                        /* 0x44c */
216 
217 } manuf_info_t;
218 
219 
220 /****************************************************************************
221  * Features Information Region                                              *
222  ****************************************************************************/
223 typedef struct _feature_info_t
224 {
225     shared_feat_cfg_t shared_feature_config;          /* 0x450 */
226     port_feat_cfg_t port_feature_config[PORT_MAX];    /* 0x454 (116*2=0xe8) */
227     u32_t crc;                                        /* 0x53c */
228 
229 } feature_info_t;
230 
231 
232 /****************************************************************************
233  * VPD Region                                                               *
234  ****************************************************************************/
235 
236 #define MAX_VPD_R_LENGTH                    128
237 #define MAX_VPD_W_LENGTH                    128
238 
239 typedef struct media_vpd_read_t
240 {
241     u8_t data[MAX_VPD_R_LENGTH];
242 } media_vpd_read_t;
243 
244 typedef struct media_vpd_write_t
245 {
246     u8_t data[MAX_VPD_W_LENGTH];
247 } media_vpd_write_t;
248 
249 typedef struct media_vpd_t
250 {
251     media_vpd_read_t vpd_r;                           /* 0x540 */
252     media_vpd_write_t vpd_w;                          /* 0x5c0 */
253 } media_vpd_t;
254 
255 /****************************************************************************
256  * License Region                                                           *
257  ****************************************************************************/
258 
259 #define SHARED_SECRET_BYTE_CNT              20
260 #define OEM_OPAQUE_DATA_BYTE_CNT            32
261 #define MAC_ADDRESS_ALIGNED_BYTE_CNT        8
262 
263 /* Upgrade License Region */
264 #define UPGRADE_KEY_COUNT                   1
265 
266 typedef struct _upgrade_key_info_t
267 {
268     u32_t key_available;
269         #define KEY_AVAILABLE_UPGRADE_KEY_0                 0x1
270     license_key_t upgrade_key[UPGRADE_KEY_COUNT];
271     u8_t hwkey_mac[MAC_ADDRESS_ALIGNED_BYTE_CNT];                       /* Phony MAC address for HW key
272                                                                            (SVID followed by MAC addr) */
273     u8_t oem_opaque[OEM_OPAQUE_DATA_BYTE_CNT];                          /* Used via BMAPI */
274     u32_t crc;
275 } upgrade_key_info_t;
276 
277 /* Manufacturing License Region */
278 typedef struct _manuf_key_info_t
279 {
280     u32_t revision;
281         #define LICENSE_REV_A                               'A'
282         #define LICENSE_REV_MASK                            0x0000ffff
283         #define LICENSE_SIGNATURE_MASK                      0xffff0000
284         #define LICENSE_SIGNATURE                           0x4c4b0000  /* LK */
285 
286     u8_t shared_secret[SHARED_SECRET_BYTE_CNT];                         /* Customer dependent */
287         #define SSECRET_ENCODED_32BIT_VALUE                 0x5a5a5a5a
288         #define SSECRET_ENCODED_8BIT_VALUE                  0x5a
289     license_key_t manuf_key;
290     u8_t oem_opaque[OEM_OPAQUE_DATA_BYTE_CNT];                          /* Used via BMAPI */
291     u32_t crc;
292 } manuf_key_info_t;
293 
294 /****************************************************************************
295  * NVRAM FULL MAP                                                           *
296  ****************************************************************************/
297 typedef struct _nvm_image_t
298 {                                                     /* NVM Offset  (size) */
299     bootstrap_region_t bootstrap;                     /* 0x0         (0x14) */
300     dir_t              dir;                           /* 0x14        (0xec) */
301     manuf_info_t       manuf_info;                    /* 0x100      (0x350) */
302     feature_info_t     feature_info;                  /* 0x450       (0xf0) */
303     media_vpd_t        vpd;                           /* 0x540      (0x100) */
304     upgrade_key_info_t upgrade_key_info[PORT_MAX];    /* 0x640 (100*2=0xc8) */
305     manuf_key_info_t   manuf_key_info[PORT_MAX];      /* 0x708 (112*2=0xe0) */
306 } nvm_image_t;                                        /* 0x7e8 */
307 
308 #define NVM_OFFSET(f)                  ((u32_t)((int_ptr_t)(&(((nvm_image_t*)0)->f))))
309 
310 
311 /* This struct defines the additional NVM configuration parameters needed for PATH 1 in E2 */
312 
313 typedef struct _path1_nvm_image_t
314 {                                                     /* NVM Offset  (size) */
315     manuf_info_t       manuf_info;                    /* 0x7e8      (0x350) */
316     feature_info_t     feature_info;                  /* 0xb38       (0xf0) */
317 } path1_nvm_image_t;                                  /* 0xdd0 */
318 
319 #define PATH1_NVM_OFFSET(f)            (sizeof(nvm_image_t) + __builtin_offsetof(path1_nvm_image_t, f))
320 
321 #define NVM_OFFSET_PATH(field,path) \
322         ((u32_t)((path == 0) ? (NVM_OFFSET(field)) : (PATH1_NVM_OFFSET(field))))
323 
324 
325 /****************************************/
326 /***      NVM RETAIN section          ***/
327 /****************************************/
328 // Max nvm retain bitmap size is currently set to the size of manuf_info
329 // To be to preserve manuf_info in a dword resolution, we need sizeof(manuf_info_t) >> 2
330 // To represent each dword in bit, divide by 32 ( >>5), and add 1 to round up.
331 #define NVM_RETAIN_BEGIN                0
332 #define NVM_RETAIN_END                  (PATH1_NVM_OFFSET(feature_info) + sizeof(feature_info_t))
333 #define NVM_RETAIN_ADDR_TO_ARR_IDX(addr) ((addr) >> 7)
334 #define NVM_RETAIN_ADDR_TO_DW_BIT(addr) (1<<(((addr) >> 2) & 0x1f))
335 #define NVM_RETAIN_BITMAP_SIZE          (NVM_RETAIN_ADDR_TO_ARR_IDX(NVM_RETAIN_END) + 1)
336 
337 
338 /*******************************************************/
339 /* These structs define the modules image block in NVM */
340 /*******************************************************/
341 #define SFF_VENDOR_NAME_LEN                 16
342 #define SFF_VENDOR_OUI_LEN                  3
343 #define SFF_VENDOR_PN_LEN                   16
344 
345 typedef struct _module_info_t
346 {
347     u32_t ctrl_flags;
348 	#define MODULE_INFO_FLAG_CHECK_VENDOR_NAME          (1 << 0)
349 	#define MODULE_INFO_FLAG_CHECK_VENDOR_OUI           (1 << 1)
350 	#define MODULE_INFO_FLAG_CHECK_VENDOR_PN            (1 << 2)
351 	#define MODULE_INFO_FLAG_CHECK_BRANDING             (1 << 3)
352 
353     char vendor_name[SFF_VENDOR_NAME_LEN];
354     u8_t vendor_oui[SFF_VENDOR_OUI_LEN];
355     u8_t reserved;
356     char vendor_pn[SFF_VENDOR_PN_LEN];
357 } module_info_t;
358 
359 typedef struct _module_image_t
360 {
361     u32_t format_version;
362 	#define MODULE_IMAGE_VERSION_1        1
363     /* With branding */
364 	#define MODULE_IMAGE_VERSION_2        2 /* With branding */
365     u32_t no_modules;
366     /* This array length depends on the no_modules */
367     module_info_t modules[1];
368 } module_image_t;
369 
370 
371 typedef struct _vpd_image_t
372 {
373     u32_t       format_revision;
374         #define VPD_IMAGE_VERSION        1
375 
376     /* This array length depends on the number of VPD fields */
377     u8_t        vpd_data[1];
378 
379 } vpd_image_t;
380 
381 
382 typedef struct _extended_dir_image_t
383 {
384     u32_t no_images;                        /* Number of images included in
385                                                 the extended dir image */
386 
387     u32_t total_byte_cnt;                   /* Total byte_cnt of all images
388                                                included in the extended dir */
389 
390     code_entry_t extended_dir_images[MAX_IMAGES_IN_EXTENDED_DIR];
391                                             /* Array of images information
392                                                within extended dir image */
393 } extended_dir_image_t;
394 
395 
396 #define MAC_PARTITION_FORMAT_VERSION 1
397 
398 struct macp_gbl_cfg {
399         /* Reserved bits: 0-0 */
400         #define MACP_GBL_CFG_FORMAT_VER_MASK                          0x000000FF
401         #define MACP_GBL_CFG_FORMAT_VER_SHIFT                         0
402 
403 
404         u32 gbl_cfg;
405         #define MACP_GBL_CFG_GBL_CFG_MASK                             0x0000FF00
406         #define MACP_GBL_CFG_GBL_CFG_SHIFT                            8
407         #define MACP_GBL_CFG_GBL_CFG_DISABLED                         0x00000000
408         #define MACP_GBL_CFG_GBL_CFG_ENABLED                          0x00000100
409 
410 };
411 
412 struct macp_port_cfg {
413 
414         u32 port_cfg;
415         #define MACP_PORT_CFG_FLOW_CTRL_MASK                          0x000000FF
416         #define MACP_PORT_CFG_FLOW_CTRL_SHIFT                         0
417         #define MACP_PORT_CFG_FLOW_CTRL_AUTO                          0x00000000
418         #define MACP_PORT_CFG_FLOW_CTRL_TX_ONLY                       0x00000001
419         #define MACP_PORT_CFG_FLOW_CTRL_RX_ONLY                       0x00000002
420         #define MACP_PORT_CFG_FLOW_CTRL_BOTH                          0x00000003
421         #define MACP_PORT_CFG_FLOW_CTRL_NONE                          0x00000004
422 
423         #define MACP_PORT_CFG_PHY_LINK_SPD_MASK                       0x0000FF00
424         #define MACP_PORT_CFG_PHY_LINK_SPD_SHIFT                      8
425         #define MACP_PORT_CFG_PHY_LINK_SPD_1G                         0x00000000
426         #define MACP_PORT_CFG_PHY_LINK_SPD_2_DOT_5G                   0x00000100
427         #define MACP_PORT_CFG_PHY_LINK_SPD_10G                        0x00000200
428         #define MACP_PORT_CFG_PHY_LINK_SPD_20G                        0x00000400
429 
430         #define MACP_PORT_CFG_NUM_PARTITIONS_MASK                     0x00FF0000
431         #define MACP_PORT_CFG_NUM_PARTITIONS_SHIFT                    16
432 
433 
434         u32 Reserved0[2];
435 };
436 
437 struct macp_func_cfg {
438 
439         u32 func_cfg;
440         #define MACP_FUNC_CFG_FLAGS_MASK                              0x0000007F
441         #define MACP_FUNC_CFG_FLAGS_SHIFT                             0
442         #define MACP_FUNC_CFG_FLAGS_ENABLED                           0x00000001
443         #define MACP_FUNC_CFG_FLAGS_ETHERNET                          0x00000002
444         #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD                     0x00000004
445         #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD                      0x00000008
446         /*  pause on host ring */
447         #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING_MASK                 0x00000080
448         #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING_SHIFT                7
449         #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING_DISABLED             0x00000000
450         #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING_ENABLED              0x00000080
451 
452         #define MACP_FUNC_CFG_BW_WEIGHT_MASK                          0x0000FF00
453         #define MACP_FUNC_CFG_BW_WEIGHT_SHIFT                         8
454 
455         #define MACP_FUNC_CFG_BW_MAX_MASK                             0xFFFF0000
456         #define MACP_FUNC_CFG_BW_MAX_SHIFT                            16
457 
458 
459         u32 net_mac_addr_upper;
460 
461         u32 net_mac_addr_lower;
462 
463         u32 iscsi_mac_addr_upper;
464 
465         u32 iscsi_mac_addr_lower;
466 
467         u32 fcoe_mac_addr_upper;
468 
469         u32 fcoe_mac_addr_lower;
470 
471         u32 fcoe_node_wwn_upper;
472 
473         u32 fcoe_node_wwn_lower;
474 
475         u32 fcoe_port_wwn_upper;
476 
477         u32 fcoe_port_wwn_lower;
478 
479         u32 pf_allocation;
480         /* number of vfs in function, if 0 - sriov disabled */
481         #define MACP_FUNC_CFG_NUMBER_OF_VFS_MASK                      0x000000FF
482         #define MACP_FUNC_CFG_NUMBER_OF_VFS_SHIFT                     0
483 };
484 
485 
486 typedef struct _nvm_nic_part_cfg_t
487 {
488   struct macp_gbl_cfg global_cfg;
489   struct macp_port_cfg port_cfg[NVM_PATH_MAX][PORT_MAX];
490   struct macp_func_cfg func_cfg[E1H_FUNC_MAX];
491   u8_t reserved2[72];
492   /* NOTE: CRC will be appended by nvm_program procedure */
493 }nvm_nic_part_cfg_t;
494 
495 #define NIV_FORMAT_VERSION_ONE 1
496 #define NIV_MAX_PROFILE_LEN 80
497 #define NIV_NUM_PROFILES_SUPPORTED 64
498 
499 struct niv_gbl_cfg {                              /* NVRAM OFFSET */
500 
501 	u32 gbl_cfg;                                        /* 0x1000 */
502 	#define NIV_GBL_CFG_IMAGE_VER_MASK                            0x000000FF
503 	#define NIV_GBL_CFG_IMAGE_VER_SHIFT                           0
504 
505 
506 	u32 Reserved0[2];                                   /* 0x1004 */
507 };
508 
509 struct niv_port_cfg {                             /* port 0: 0x100C port 1: 0x1018 */
510 
511 	u32 port_cfg;                                       /* 0x100C */
512 	#define NIV_PORT_CFG_FLOW_CTRL_MASK                           0x000000FF
513 	#define NIV_PORT_CFG_FLOW_CTRL_SHIFT                          0
514 	#define NIV_PORT_CFG_FLOW_CTRL_AUTO                           0x00000000
515 	#define NIV_PORT_CFG_FLOW_CTRL_TX_ONLY                        0x00000001
516 	#define NIV_PORT_CFG_FLOW_CTRL_RX_ONLY                        0x00000002
517 	#define NIV_PORT_CFG_FLOW_CTRL_BOTH                           0x00000003
518 	#define NIV_PORT_CFG_FLOW_CTRL_NONE                           0x00000004
519 
520 	#define NIV_PORT_CFG_PHY_LINK_SPD_MASK                        0x0000FF00
521 	#define NIV_PORT_CFG_PHY_LINK_SPD_SHIFT                       8
522 	#define NIV_PORT_CFG_PHY_LINK_SPD_1G                          0x00000000
523 	#define NIV_PORT_CFG_PHY_LINK_SPD_2_DOT_5G                    0x00000100
524 	#define NIV_PORT_CFG_PHY_LINK_SPD_10G                         0x00000200
525 	#define NIV_PORT_CFG_PHY_LINK_SPD_20G                         0x00000400
526 };
527 
528 struct niv_func_cfg {                             /* port 0: 0x1024 port 1: 0x10AC */
529 
530 	u32 bw_params;                                      /* 0x1024 */
531 	#define NIV_FUNC_CFG_bw_weight_MASK                           0x0000FFFF
532 	#define NIV_FUNC_CFG_bw_weight_SHIFT                          0
533 
534 	#define NIV_FUNC_CFG_bw_max_MASK                              0xFFFF0000
535 	#define NIV_FUNC_CFG_bw_max_SHIFT                             16
536 
537 
538 	u32 func_cfg_1;                                     /* 0x1028 */
539 	#define NIV_FUNC_CFG_vif_type_MASK                            0x0000007F
540 	#define NIV_FUNC_CFG_vif_type_SHIFT                           0
541 	#define NIV_FUNC_CFG_vif_type_ENABLED                         0x00000001
542 	#define NIV_FUNC_CFG_vif_type_ETHERNET                        0x00000002
543 	#define NIV_FUNC_CFG_vif_type_ISCSI_OFFLOAD                   0x00000004
544 	#define NIV_FUNC_CFG_vif_type_FCOE_OFFLOAD                    0x00000008
545 
546 	/*  pause on host ring */
547 	#define NIV_FUNC_CFG_PAUSE_ON_HOST_RING_MASK                  0x00000080
548 	#define NIV_FUNC_CFG_PAUSE_ON_HOST_RING_SHIFT                 7
549 	#define NIV_FUNC_CFG_PAUSE_ON_HOST_RING_DISABLED              0x00000000
550 	#define NIV_FUNC_CFG_PAUSE_ON_HOST_RING_ENABLED               0x00000080
551 	#define NIV_FUNC_CFG_remote_boot_enabled_MASK                 0x0000FF00
552 	#define NIV_FUNC_CFG_remote_boot_enabled_SHIFT                8
553 	#define NIV_FUNC_CFG_remote_boot_enabled_DISABLED             0x00000000
554 	#define NIV_FUNC_CFG_remote_boot_enabled_ENABLED              0x00000100
555 
556 	#define NIV_FUNC_CFG_profile_enabled_MASK                     0x00FF0000
557 	#define NIV_FUNC_CFG_profile_enabled_SHIFT                    16
558 	#define NIV_FUNC_CFG_profile_enabled_DISABLED                 0x00000000
559 	#define NIV_FUNC_CFG_profile_enabled_ENABLED                  0x00010000
560 
561 
562 	u32 net_mac_addr_upper;                             /* 0x102B */
563 
564 	u32 net_mac_addr_lower;                             /* 0x102F */
565 
566 	u32 iscsi_mac_addr_upper;                           /* 0x1034 */
567 
568 	u32 iscsi_mac_addr_lower;                           /* 0x1038 */
569 
570 	u32 fcoe_mac_addr_upper;                            /* 0x103C */
571 
572 	u32 fcoe_mac_addr_lower;                            /* 0x1040 */
573 
574 	u32 fcoe_node_wwn_upper;                            /* 0x1044 */
575 
576 	u32 fcoe_node_wwn_lower;                            /* 0x1048 */
577 
578 	u32 fcoe_port_wwn_upper;                            /* 0x104C */
579 
580 	u32 fcoe_port_wwn_lower;                            /* 0x1050 */
581 
582 	u8 profile_name[80];                                /* 0x1054 */
583 
584 	u32 Reserved0[2];                                   /* 0x10A4 */
585 };
586 
587 typedef struct _nvm_niv_cfg_t
588 {
589         struct niv_gbl_cfg      global_cfg;                // global config
590         struct niv_port_cfg    port_cfg[NVM_PATH_MAX][PORT_MAX];       // per port config
591         u32 reserved[2];
592         struct niv_func_cfg     func_cfg[E1H_FUNC_MAX];   // per func config
593 } nvm_niv_cfg_t;
594 
595 struct niv_port_profiles_cfg {                    /* port 0: 0x1600 port 1: 0x2A00 */
596 
597 	u8 profiles_list[64][80];                           /* 0x1600 */
598 };
599 
600 typedef struct _nvm_niv_port_profile_t
601 {
602         struct niv_port_profiles_cfg    port_cfg[PORT_MAX];       // per port config
603 } nvm_niv_port_profile_t;
604 
605 
606 typedef struct _hw_set_info_t
607 {
608     u32_t reg_type;
609     #define GRC_REG_TYPE 1
610     #define PHY_REG_TYPE 2
611     #define PCI_REG_TYPE 4
612 
613     u32_t bank_num;
614     u32_t pf_num;
615     u32_t operation;
616     #define READ_OP     1
617     #define WRITE_OP    2
618     #define RMW_SET_OP  3
619     #define RMW_CLR_OP  4
620 
621     u32_t reg_addr;
622     u32_t reg_data;
623 
624     u32_t reset_type;
625     #define POR_RESET_TYPE  (1 << 0)
626     #define HARD_RESET_TYPE (1 << 1)
627     #define CORE_RESET_TYPE (1 << 2)
628     #define MCP_RESET_TYPE  (1 << 3)
629     #define PERSET_ASSERT   (1 << 4)
630     #define PERSET_DEASSERT (1 << 5)
631 
632 } hw_set_info_t;
633 
634 typedef struct _hw_set_image_t
635 {
636     u32_t format_version;
637         #define HW_SET_IMAGE_VERSION        1
638     u32_t no_hw_sets;
639     /* This array length depends on the no_hw_sets */
640     hw_set_info_t hw_sets[1];
641 } hw_set_image_t;
642 
643 
644 struct iscsi_flash_meta_data {
645 	u16_t signature;
646 	u8_t reserved_a;
647 	u8_t version;
648 	u32_t block_size;
649 	u16_t target_size;
650 	u8_t target_max;
651 	u8_t reserved[5];
652 };
653 
654 #define ISID_SIZE 6
655 
656 struct iscsi_flash_session {
657 	u32_t version;
658 	u32_t ctrl_flags;
659 	#define FLASH_SESS_CTRL_ENTRY_ENABLE		(0)
660 	#define FLASH_SESS_CTRL_AUTO_CONNECT		(1)
661 	#define FLASH_SESS_CTRL_AUTO_SEND_TGT_DISABLE	(2)
662 	#define FLASH_SESS_CTRL_DISCOVERY_SESS		(3)
663 	#define FLASH_SESS_CTRL_ENABLE_IMM_DATA		(4)
664 	#define FLASH_SESS_CTRL_ENABLE_INIT_R2T		(5)
665 	#define FLASH_SESS_CTRL_DATA_SEQ_IN_ORDER	(6)
666 	#define FLASH_SESS_CTRL_DATA_PDU_IN_ORDER	(7)
667 	#define FLASH_SESS_CTRL_CHAP_AUTH		(8)
668 	#define FLASH_SESS_CTRL_BIDI_CHAP		(9)
669 	#define FLASH_SESS_CTRL_DISCOVERY_LOGOUT	(10)
670 	#define FLASH_SESS_CTRL_DISCOVERY_AUTH_OPT	(11)
671 	u32_t stat_flags;
672 	#define FLASH_SESS_STAT_IS_BOOT_TARGET		(0)
673 	char portal_type[4];
674 	u32_t first_burst_len;
675 	u16_t def_time2wait;
676 	u16_t def_time2retain;
677 	u16_t max_outstanding_r2t;
678 	u16_t tsid;
679 	u8_t isid[ISID_SIZE];  /* ISID_SIZE = 6 */
680 	u8_t erl;
681 	u8_t def_taskmgmt_tmo;
682 	u32_t max_burst_len;
683 	char targetalias[32];
684 	u16_t tpgt;
685 	u16_t discovery_parent_idx;
686 	u16_t discovery_parent_type;
687 	u16_t chap_in_idx;
688 	u16_t chap_out_idx;
689     u16_t reserved_a;
690 	char username[64];
691 	char username_in[64];
692 	char password[64];
693 	char password_in[64];
694 	char targetname[256];
695 	u8_t reserved[4];
696 };
697 
698 struct iscsi_flash_connection {
699 	u32_t ctrl_flags;
700 	#define FLASH_CONN_CTRL_HEADER_DIGEST		(0)
701 	#define FLASH_CONN_CTRL_DATA_DIGEST		(1)
702 	#define FLASH_CONN_CTRL_SNACK_REQ		(2)
703 	#define FLASH_CONN_CTRL_TCP_TIMESTAMP_STAT	(3)
704 	#define FLASH_CONN_CTRL_TCP_NAGLE_DISABLE	(4)
705 	#define FLASH_CONN_CTRL_TCP_WSF_DISABLE		(5)
706 	#define FLASH_CONN_CTRL_TCP_TIMER_SCALE		(6)
707 	#define FLASH_CONN_CTRL_TCP_TIMESTAMP_ENABLE	(7)
708 	#define FLASH_CONN_CTRL_IP_FRAG_DISABLE		(8)
709 	u32_t stat_flags;
710 	#define FLASH_CONN_STAT_IS_FW_ASSIGNED_IPV6	(0)
711 	u32_t max_recv_dlength;
712 	u32_t max_xmit_dlength;
713 	u16_t keepalive_tmo;
714 	u16_t port;
715 	u32_t ipaddress[4];
716 	u32_t link_local_ipv6[4];
717 	u32_t redirect_ipaddr[4];
718 	u16_t max_segment_size;
719 	u16_t local_port;
720 	u8_t ipv4_tos;
721 	u8_t ipv6_traffic_class;
722 	u8_t ipv6_flow_label;
723 	u8_t reserved_a;
724 	u8_t tcp_xmit_wsf;
725 	u8_t tcp_recv_wsf;
726 	u8_t reserved_b[2];
727 	u32_t statsn;
728 	u32_t exp_statsn;
729 	u8_t reserved[12];
730 };
731 
732 struct iscsi_flash_initiator {
733 	u32_t ctrl_flags;
734 	u32_t stat_flags;
735 	u8_t hwaddress[6];
736 	u8_t reserved_a[2];
737 	u32_t initiator_ip[4];
738 	u32_t subnet_mask[4];
739 	u32_t gateway[4];
740 	u16_t vlan_id;
741 	u8_t reserved_b[2];
742 	char initiatorname[256];
743 };
744 
745 struct iscsi_flashnode {
746 	struct iscsi_flash_session session;
747 	struct iscsi_flash_connection connection;
748 	struct iscsi_flash_initiator initiator;
749 };
750 
751 struct iscsi_persistent_image {
752 	struct iscsi_flash_meta_data meta_data;
753 	struct iscsi_flashnode flahsnode[16];
754 };
755 
756 
757 #define NVM_CFG_EXTENDED_SHARED_IMAGE_MAX_SIZE 256
758 
759 #endif //NVM_MAP_H
760