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Searched refs:BSM_BASE (Results 1 – 3 of 3) sorted by relevance

/illumos-gate/usr/src/uts/common/io/iwk/
H A Diwk_hw.h1038 #define BSM_BASE (CSR_BASE + 0x3400) macro
1040 #define BSM_WR_CTRL_REG (BSM_BASE + 0x000) /* ctl and status */
1041 #define BSM_WR_MEM_SRC_REG (BSM_BASE + 0x004) /* source in BSM mem */
1042 #define BSM_WR_MEM_DST_REG (BSM_BASE + 0x008) /* dest in SRAM mem */
1043 #define BSM_WR_DWCOUNT_REG (BSM_BASE + 0x00C) /* bytes */
1044 #define BSM_WR_STATUS_REG (BSM_BASE + 0x010) /* bit 0: 1 == done */
1049 #define BSM_DRAM_INST_PTR_REG (BSM_BASE + 0x090)
1050 #define BSM_DRAM_INST_BYTECOUNT_REG (BSM_BASE + 0x094)
1051 #define BSM_DRAM_DATA_PTR_REG (BSM_BASE + 0x098)
1052 #define BSM_DRAM_DATA_BYTECOUNT_REG (BSM_BASE + 0x09C)
/illumos-gate/usr/src/uts/common/io/iwh/
H A Diwh_hw.h997 #define BSM_BASE (CSR_BASE + 0x3400) macro
999 #define BSM_WR_CTRL_REG (BSM_BASE + 0x000) /* ctl and status */
1000 #define BSM_WR_MEM_SRC_REG (BSM_BASE + 0x004) /* source in BSM mem */
1001 #define BSM_WR_MEM_DST_REG (BSM_BASE + 0x008) /* dest in SRAM mem */
1002 #define BSM_WR_DWCOUNT_REG (BSM_BASE + 0x00C) /* bytes */
1003 #define BSM_WR_STATUS_REG (BSM_BASE + 0x010) /* bit 0: 1 == done */
/illumos-gate/usr/src/uts/common/io/iwp/
H A Diwp_hw.h993 #define BSM_BASE (CSR_BASE + 0x3400) macro
995 #define BSM_WR_CTRL_REG (BSM_BASE + 0x000) /* ctl and status */
996 #define BSM_WR_MEM_SRC_REG (BSM_BASE + 0x004) /* source in BSM mem */
997 #define BSM_WR_MEM_DST_REG (BSM_BASE + 0x008) /* dest in SRAM mem */
998 #define BSM_WR_DWCOUNT_REG (BSM_BASE + 0x00C) /* bytes */
999 #define BSM_WR_STATUS_REG (BSM_BASE + 0x010) /* bit 0: 1 == done */