Searched refs:BIT_6 (Results 1 – 20 of 20) sorted by relevance
24 #define PHY_CTRL_SPEED_MASK (BIT_6 | BIT_13)27 #define PHY_CTRL_SPEED_SELECT_1000MBPS BIT_666 #define PHY_AN_AD_10BASET_FULL BIT_676 #define PHY_AN_AD_1000X_HALF_DUPLEX BIT_686 #define PHY_LINK_PARTNER_10BASET_FULL BIT_6180 #define BCM5401_SHDW_NORMAL_DISABLE_INV_PRF BIT_6
403 #define IDC_RIT_MASK (BIT_6 | BIT_5 | BIT_4)429 #define IDC_MS_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4)464 #define MBC_LOOPBACK_64BIT BIT_6 /* 2200 0r 2300 */470 #define MBC_ECHO_64BIT BIT_6 /* 64bit DMA address used */543 #define MBX_6 BIT_6597 #define FO1_DISABLE_GPIO BIT_6598 #define FO1_DISABLE_LEDS BIT_6655 #define FWATTRIB2_MQUE BIT_6669 #define IMO_INTERRUPT_HANDSHAKE BIT_6826 #define LINK_CONFIG_PAUSE_MASK (BIT_6 | BIT_5)
185 #define BIT_6 0x40 macro487 #define QL_DMA_ALIGN_64_BYTE_BOUNDARY (uint64_t)BIT_6820 #define HC24_HOST_INT BIT_6 /* Host to RISC intrpt bit */937 #define VPO_ENABLE_SNS_LOGIN_SCR BIT_61339 #define SRB_UB_IN_FCA BIT_6 /* FCA holds unsolicited buffer */1485 #define TQF_PLOGI_PROGRS BIT_61598 #define QL_TASK_DAEMON_STARTED BIT_61944 #define IP_ENABLED (uint64_t)BIT_61982 #define NEED_UNSOLICITED_BUFFERS (uint64_t)BIT_62034 #define CFG_LR_SUPPORT (uint64_t)BIT_6[all …]
219 #define FLASH8192 BIT_6239 #define LED_GREEN BIT_6
94 #define CF_DATA_OUT BIT_6331 #define SF_DATA_OUT BIT_6676 #define CFO_EXPLICIT_LOGO BIT_6
33 #define BIT_6 0x40 macro
72 #define BIT_6 0x00040 macro93 #define SKD_REGS_MAPPED BIT_6
77 #define H2RISC_INTR BIT_6103 BIT_7 | BIT_6 | BIT_5 | BIT_4 | \112 #define FW_INTR_STATUS_MASK (BIT_7 | BIT_6 | BIT_5 | BIT_4 | \
2370 BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | in qlt_port_online()2389 mcp->to_fw[1] = BIT_6 | BIT_1; in qlt_port_online()2405 BIT_10 | BIT_9 | BIT_8 | BIT_7 | BIT_6 | BIT_5 | in qlt_port_online()2425 mcp->to_fw[1] = BIT_6; in qlt_port_online()3693 mcp->to_fw_mask |= BIT_2 | BIT_3 | BIT_7 | BIT_6; in qlt_alloc_mailbox_command()5605 flags = (uint16_t)(BIT_6 | BIT_15 | in qlt_send_status()5737 flags = (uint16_t)(flags | BIT_6); in qlt_send_status()5853 req1f = BIT_6; in qlt_send_els_response()6214 flags = (uint16_t)(flags | BIT_6); in qlt_handle_atio()6305 else if (tm & BIT_6) in qlt_handle_atio()[all …]
37 #define BIT_6 0x40 macro
169 #define QL_DMA_ALIGN_64_BYTE_BOUNDARY (uint64_t)BIT_6240 #define INIT_MEMORY_ALLOC BIT_6634 #define CFG_CKSUM_PARTIAL BIT_6
50 #define BIT_6 0x40 macro413 #define RT_IDX_ETH_FCOE BIT_6526 #define CQ_6_NOT_EMPTY BIT_62321 #define FLASH8192 BIT_6
665 (icb->firmware_options[0] | BIT_6 | BIT_1); in ql_nvram_config()689 BIT_7 | BIT_6 | BIT_5 | BIT_2 | BIT_0); in ql_nvram_config()696 (icb->firmware_options[1] | BIT_7 | BIT_6); in ql_nvram_config()1046 nv->firmware_options_3[1] = BIT_6; in ql_nvram_24xx_config()1177 BIT_6); in ql_nvram_24xx_config()1206 (icb->firmware_options_2[3] | BIT_6 | BIT_5); in ql_nvram_24xx_config()1209 (icb->firmware_options_2[3] | ~(BIT_6 | BIT_5)); in ql_nvram_24xx_config()1584 ~(BIT_6 | BIT_5 | BIT_4)); in ql_23_properties()2019 ~(BIT_6 | BIT_5 | BIT_4)); in ql_24xx_properties()2620 (icb->firmware_options_2[2] | BIT_7 | BIT_6); in ql_start_firmware()[all …]
735 if (echo_pt->options & BIT_6) { in ql_echo()2459 port_no = (uint8_t)(port_no | BIT_6); in ql_get_status_counts()2703 mcp->mb[1] = BIT_6; in ql_lip_reset()
1263 pkt->control_flags_l = BIT_6; in ql_ip_iocb()
636 nv->firmware_options_3[1] = BIT_6; in ql_set_nvram_adapter_defaults()
1824 if (pkt->entry_status & BIT_6) { in ql_error_entry()
4592 *bptr & (BIT_6 | BIT_5 | BIT_4))) { in ql_port_manage()4595 (*bptr & ~(BIT_6|BIT_5|BIT_4)); in ql_port_manage()4710 (echo.options | BIT_6); in ql_port_manage()
592 } else if (tm & BIT_6) { in fcoet_process_unsol_fcp_cmd()
2486 } else if (tm & BIT_6) { in emlxs_fct_handle_unsol_req()