Home
last modified time | relevance | path

Searched refs:ASI_MMU_CTX (Results 1 – 9 of 9) sorted by relevance

/illumos-gate/usr/src/uts/sun4v/vm/
H A Dmach_sfmmu_asm.S93 ldxa [%g3]ASI_MMU_CTX, %g5 /* %g5 = sec-ctx */
98 stxa %g2, [%g3]ASI_MMU_CTX /* set invalid ctx */
102 ldxa [%g7]ASI_MMU_CTX, %g5 /* %g5 = pri-ctx */
107 stxa %g2, [%g7]ASI_MMU_CTX /* set pri-ctx to invalid */
151 stxa %g2, [%g3]ASI_MMU_CTX /* set sec-ctx to invalid */
155 ldxa [%g7]ASI_MMU_CTX, %g4 /* %g4 = pri-ctx */
159 stxa %g2, [%g7]ASI_MMU_CTX /* set pri-ctx to invalid */
183 ldxa [%o0]ASI_MMU_CTX, %o0
189 ldxa [%o0]ASI_MMU_CTX, %o0
210 stxa %o0, [%o1]ASI_MMU_CTX /* set 2nd context reg. */
[all …]
H A Dmach_sfmmu.h78 stxa cnum, [tmp1]ASI_MMU_CTX; /* set 2nd ctx reg. */ \
525 ldxa [tmp]ASI_MMU_CTX, ctx1 ;\
/illumos-gate/usr/src/uts/sun4u/vm/
H A Dmach_sfmmu_asm.S99 stxa %g0, [%g5]ASI_MMU_CTX
103 ldxa [%g3]ASI_MMU_CTX, %g5 /* %g5 = pgsz | sec-ctx */
110 stxa %g2, [%g3]ASI_MMU_CTX /* set invalid ctx */
114 ldxa [%g7]ASI_MMU_CTX, %g3 /* get pgz | pri-ctx */
122 stxa %g2, [%g7]ASI_MMU_CTX /* set pri-ctx to invalid */
H A Dmach_sfmmu.h92 stxa cnum, [tmp1]ASI_MMU_CTX ;\
109 stxa cnum, [tmp1]ASI_MMU_CTX ;\
724 ldxa [tmp1]ASI_MMU_CTX, tmp1 /* tmp2 = shctx reg */ ;\
/illumos-gate/usr/src/uts/sun4u/sys/
H A Dmachthread.h250 ldxa [scr1]ASI_MMU_CTX, scr1; \
263 stxa scr2, [scr1]ASI_MMU_CTX; \
H A Dmachasi.h100 #define ASI_MMU_CTX ASI_DMMU macro
/illumos-gate/usr/src/uts/sun4v/sys/
H A Dmachasi.h57 #define ASI_MMU_CTX ASI_MMU macro
/illumos-gate/usr/src/uts/sun4u/ml/
H A Dwbuf.S415 ldxa [%g6]ASI_MMU_CTX, %g7
424 stxa %g5, [%g6]ASI_MMU_CTX
/illumos-gate/usr/src/uts/sfmmu/vm/
H A Dhat_sfmmu.h2071 ldxa [reg1]ASI_MMU_CTX, reg2; \
2089 stxa reg0, [reg1]ASI_MMU_CTX; \