xref: /illumos-gate/usr/src/uts/intel/io/amr/amrreg.h (revision 2d6eb4a5)
1 /*
2  * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
3  * Use is subject to license terms.
4  */
5 /*
6  * Copyright (c) 1999,2000 Michael Smith
7  * Copyright (c) 2000 BSDi
8  * All rights reserved.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29  * SUCH DAMAGE.
30  *
31  * Copyright (c) 2002 Eric Moore
32  * Copyright (c) 2002 LSI Logic Corporation
33  * All rights reserved.
34  *
35  * Redistribution and use in source and binary forms, with or without
36  * modification, are permitted provided that the following conditions
37  * are met:
38  * 1. Redistributions of source code must retain the above copyright
39  *    notice, this list of conditions and the following disclaimer.
40  * 2. Redistributions in binary form must reproduce the above copyright
41  *    notice, this list of conditions and the following disclaimer in the
42  *    documentation and/or other materials provided with the distribution.
43  * 3. The party using or redistributing the source code and binary forms
44  *    agrees to the disclaimer below and the terms and conditions set forth
45  *    herein.
46  *
47  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
48  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
49  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
50  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
51  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
52  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
53  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
54  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
55  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
56  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
57  * SUCH DAMAGE.
58  */
59 
60 /*
61  * Note: If the structures and variables definitions can be found from the
62  *	 "MegaRAID PCI SCSI Disk Array Controller F/W Technical Reference
63  *	 Manual", the names defined in this documents will also be provided
64  *	 by " ", and the descriptions for each variables and constants are
65  *	 given as well.
66  */
67 
68 #ifndef _AMRREG_H
69 #define	_AMRREG_H
70 
71 #ifdef	__cplusplus
72 extern "C" {
73 #endif
74 
75 #define	AMR_NSEG		26
76 #define	AMR_MAX_STATUS_ACK	46
77 
78 #define	AMR_MAXCMD		255	/* The last CMD is used for Poll only */
79 
80 #define	AMR_LIMITCMD		120	/* max count of outstanding commands */
81 #define	AMR_MAXLD		40
82 
83 #define	AMR_MAX_CHANNELS	4
84 #define	AMR_MAX_TARGETS		15
85 #define	AMR_MAX_LUNS		7
86 #define	AMR_MAX_SCSI_CMDS	(AMR_MAX_CHANNELS * AMR_MAX_TARGETS)
87 
88 #define	AMR_MAX_CDB_LEN		0x0a
89 #define	AMR_MAX_EXTCDB_LEN	0x10
90 #define	AMR_MAX_REQ_SENSE_LEN	0x20
91 
92 #define	AMR_BLKSIZE		512	/* constant for all controllers */
93 
94 /*
95  * Array constraints for controllers that support 8 logic drivers
96  */
97 #define	AMR_8LD_MAXDRIVES	8
98 #define	AMR_8LD_MAXCHAN		5
99 #define	AMR_8LD_MAXTARG		15
100 #define	AMR_8LD_MAXPHYSDRIVES	(AMR_8LD_MAXCHAN * AMR_8LD_MAXTARG)
101 
102 /*
103  * Array constraints for controllers that support 40 logic drivers
104  */
105 #define	AMR_40LD_MAXDRIVES	40
106 #define	AMR_40LD_MAXCHAN	16
107 #define	AMR_40LD_MAXTARG	16
108 #define	AMR_40LD_MAXPHYSDRIVES	(AMR_40LD_MAXCHAN * AMR_40LD_MAXTARG)
109 
110 /*
111  * The buffer size for enquiry command
112  */
113 #define	AMR_ENQ_BUFFER_SIZE	sizeof (union amr_enq_buffer)
114 
115 /*
116  * Constants used for poll command
117  */
118 #define	AMR_POLL_COMMAND_ID		0xfe
119 #define	AMR_POLL_DEFAULT_NSTATUS	0xff
120 #define	AMR_POLL_DEFAULT_STATUS		0xff
121 #define	AMR_POLL_ACK			0x77
122 
123 #pragma pack(1)
124 
125 /*
126  * The AMR mailbox. This is the main interface for
127  * programming the controller. Must be aligned at
128  * a 16-Byte physical address boundary.
129  *
130  * The first sixteen bytes are commands to the controller.
131  *
132  * There are two formats:
133  *	1. Commands for I/O: mb_blkcount/mb_lba are used.
134  *	2. Commands for I/O control: mb_channel/mb_param are used.
135  *
136  */
137 
138 struct amr_mailbox
139 {
140 	uint8_t			mb_command;	/* "Command", OUT, the op */
141 						/* code of the command */
142 	uint8_t			mb_ident;	/* "CommandID", OUT, the */
143 						/* id for this command */
144 	union {
145 		uint16_t	mbu_blkcount;	/* "NoOfSectors", OUT, the */
146 						/* number of sectors for */
147 						/* this request */
148 		uint8_t		mbu_chparam[2];	/* "Channel" and "Param", */
149 						/* OUT, Channel No. and */
150 						/* parameters */
151 	} mb_un1;
152 	union {
153 		uint32_t	mbu_lba;	/* "Lba", OUT, the starting */
154 						/* LBA for this request */
155 		uint8_t		mbu_pad[4];
156 	} mb_un2;
157 	uint32_t		mb_physaddr;	/* "DataTransferAddress", OUT */
158 						/* physical address for a */
159 						/* non-s/g command or the */
160 						/* physical address of a s/g */
161 						/* list for a s/g command */
162 	uint8_t			mb_drive;	/* "LogicalDriveNumber", OUT, */
163 						/* the log-drive for which */
164 						/* this request is intended */
165 	uint8_t			mb_nsgelem;	/* "NoSGElements", OUT, */
166 						/* number of s/g elements */
167 	uint8_t			res1;
168 	uint8_t			mb_busy;	/* "mailboxBusy", INOUT, set */
169 						/* to 1 before submit the */
170 						/* command, firmware picks */
171 						/* it and makes this byte 0 */
172 	uint8_t			mb_nstatus;	/* "NoOfStatus", IN, the */
173 						/* number of status returned */
174 						/* by firmware */
175 	uint8_t			mb_status;	/* "Status", IN, status for */
176 						/* the IDs in mb_completed[] */
177 	uint8_t			mb_completed[AMR_MAX_STATUS_ACK];
178 						/* "CompletedIdList", IN, */
179 						/* finished ID list */
180 	uint8_t			mb_poll;	/* "Mraid_poll", IN, used for */
181 						/* polling/interrupt-driven */
182 	uint8_t			mb_ack;		/* "Mraid_ack", IN, used for */
183 						/* polling/interrupt-driver */
184 	uint8_t			res2[16];
185 };
186 
187 /* Fields before mb_nstatus are the portions worth copying for controller */
188 #define	AMR_MBOX_CMDSIZE (size_t)(&((struct amr_mailbox *)(NULL))->mb_nstatus)
189 
190 #define	mb_blkcount	mb_un1.mbu_blkcount
191 #define	mb_channel	mb_un1.mbu_chparam[0]
192 #define	mb_param	mb_un1.mbu_chparam[1]
193 #define	mb_cmdsub	mb_un1.mbu_chparam[0]
194 #define	mb_cmdqual	mb_un1.mbu_chparam[1]
195 #define	mb_lba		mb_un2.mbu_lba
196 
197 /*
198  * I/O commands expect the physical address of an array
199  * of no more than AMR_NSEGS of scatter/gather table entries
200  * in mb_physaddr.
201  *
202  * sg_addr is a physical address.
203  */
204 struct amr_sgentry
205 {
206 	uint32_t	sg_addr;
207 	uint32_t	sg_count;
208 };
209 
210 /*
211  * Mailbox commands
212  * Note: This is a subset for the command set
213  */
214 #define	AMR_CMD_LREAD				0x01
215 #define	AMR_CMD_LWRITE				0x02
216 #define	AMR_CMD_PASS				0x03
217 #define	AMR_CMD_EXT_ENQUIRY			0x04
218 #define	AMR_CMD_ENQUIRY				0x05
219 #define	AMR_CMD_FLUSH				0x0a
220 #define	AMR_CMD_EXT_ENQUIRY2			0x0c
221 #define	AMR_CMD_GET_MACHINEID			0x36
222 #define	AMR_CMD_GET_INITIATOR			0x7d
223 #define	AMR_CMD_RESET_ADAPTER			0x96
224 #define	AMR_CMD_CONFIG				0xa1
225 #define	AMR_CMD_MISC_OPCODE			0xa4
226 #define	AMR_CMD_EXTPASS				0xe3
227 
228 /*
229  * Subcodes for AMR_CMD_CONFIG
230  */
231 #define	AMR_CONFIG_PRODUCT_INFO			0x0e
232 #define	AMR_CONFIG_ENQ3				0x0f
233 #define	AMR_CONFIG_ENQ3_SOLICITED_NOTIFY	0x01
234 #define	AMR_CONFIG_ENQ3_SOLICITED_FULL		0x02
235 #define	AMR_CONFIG_ENQ3_UNSOLICITED		0x03
236 
237 /*
238  * Subcodes for AMR_CMD_MISC_OPCODE
239  */
240 #define	AMR_MISC_CDB_QUERY			0x16
241 
242 /*
243  * Mailbox command results
244  */
245 #define	AMR_STATUS_SUCCESS			0x00
246 #define	AMR_STATUS_ABORTED			0x02
247 #define	AMR_STATUS_FAILED			0x80
248 
249 /*
250  * Adapter Info structure
251  */
252 struct amr_adapter_info
253 {
254 	uint8_t		aa_maxio;		/* "MaxConcCmds", concurrent */
255 						/* commands supported */
256 	uint8_t		aa_rebuild_rate;	/* "RbldRate", rebuild rate, */
257 						/* varies from 0%-100% */
258 	uint8_t		aa_maxtargchan;		/* "MaxTargPerChan", targets */
259 						/* supported per chan */
260 	uint8_t		aa_channels;		/* "ChanPresent", No. of */
261 						/* Chans present on this */
262 						/* adapter */
263 	uint8_t		aa_firmware[4];		/* "FwVer", firmware version */
264 	uint16_t	aa_flashage;		/* "AgeOfFlash", No. of times */
265 						/* FW has been downloaded */
266 	uint8_t		aa_chipsetvalue;	/* "ChipSetValue", contents */
267 						/* of 0xC0000832 */
268 	uint8_t		aa_memorysize;		/* "DramSize", in terms of MB */
269 	uint8_t		aa_cacheflush;		/* "CacheFlushInterval", in */
270 						/* terms of Seconds */
271 	uint8_t		aa_bios[4];		/* "BiosVersion", Bios ver */
272 	uint8_t		aa_boardtype;		/* "BoardType", board type */
273 	uint8_t		aa_scsisensealert;	/* "sense_alert" */
274 	uint8_t		aa_writeconfigcount;	/* "write_config_count", */
275 						/* increase with evry */
276 						/* configuration change */
277 	uint8_t		aa_driveinsertioncount;	/* "drive_inserted_count", */
278 						/* increase with every drive */
279 						/* inserted */
280 	uint8_t		aa_inserteddrive;	/* "inserted_drive", Chan:Id */
281 						/* of inserted drive */
282 	uint8_t		aa_batterystatus;	/* "battery_status", battery */
283 						/* status */
284 	uint8_t   	res1;			/* "dec_fault_bus_info", was */
285 						/* reserved */
286 };
287 
288 /*
289  * aa_batterystatus values
290  */
291 #define	AMR_BATT_MODULE_MISSING		0x01
292 #define	AMR_BATT_LOW_VOLTAGE		0x02
293 #define	AMR_BATT_TEMP_HIGH		0x04
294 #define	AMR_BATT_PACK_MISSING		0x08
295 #define	AMR_BATT_CHARGE_MASK		0x30
296 #define	AMR_BATT_CHARGE_DONE		0x00
297 #define	AMR_BATT_CHARGE_INPROG		0x10
298 #define	AMR_BATT_CHARGE_FAIL		0x20
299 #define	AMR_BATT_CYCLES_EXCEEDED	0x40
300 
301 /*
302  * Logical Drive info structure
303  */
304 struct amr_logdrive_info
305 {
306 	uint8_t		al_numdrives;		/* "NumLogDrv", No. of */
307 						/* configured logic drivers */
308 	uint8_t		res1[3];
309 	uint32_t	al_size[AMR_8LD_MAXDRIVES];
310 						/* "LDrvSize", size of each */
311 						/* logic driver */
312 	uint8_t		al_properties[AMR_8LD_MAXDRIVES];
313 						/* "LDrvProp", properties of */
314 						/* each logic driver */
315 	uint8_t		al_state[AMR_8LD_MAXDRIVES];
316 						/* "LDrvState", state of */
317 						/* each logic driver */
318 };
319 
320 /*
321  * Logical drive only: al_properties
322  */
323 #define	AMR_DRV_RAID_MASK	0x0f		/* RAID level 0, 1, 3, 5, etc */
324 #define	AMR_DRV_WRITEBACK	0x10		/* write-back enabled */
325 #define	AMR_DRV_READHEAD	0x20		/* readhead policy enabled */
326 #define	AMR_DRV_ADAPTIVE	0x40		/* adaptive I/O enabled */
327 
328 /*
329  * Physical Drive info structure
330  */
331 struct amr_physdrive_info
332 {
333 	uint8_t	ap_state[AMR_8LD_MAXPHYSDRIVES];
334 						/* "PDrvState", state of each */
335 						/* phy-driver. Low nibble is */
336 						/* current state, high nibble */
337 						/* is previous state */
338 	uint8_t	ap_predictivefailure;		/* "PredictiveFailure" */
339 };
340 
341 /*
342  * Physical/logical drive states
343  *
344  * Both logical and physical drives maintain
345  * 'current' and 'previous' states in the low/high
346  * nibble of the _state field.
347  */
348 #define	AMR_DRV_CURSTATE(x)	((x) & 0x0f)
349 #define	AMR_DRV_PREVSTATE(x)	(((x) >> 4) & 0x0f)
350 
351 /*
352  * Logical drives: al_state.
353  */
354 #define	AMR_LDRV_OFFLINE	0x00
355 #define	AMR_LDRV_DEGRADED	0x01
356 #define	AMR_LDRV_OPTIMAL	0x02
357 
358 /*
359  * Physical drives: ap_state.
360  */
361 #define	AMR_PDRV_UNCNF		0x00
362 #define	AMR_PDRV_ONLINE		0x03
363 #define	AMR_PDRV_FAILED		0x04
364 #define	AMR_PDRV_REBUILD	0x05
365 #define	AMR_PDRV_HOTSPARE	0x06
366 
367 /*
368  * Notify structure
369  */
370 struct amr_notify
371 {
372 	uint32_t	an_globalcounter;	/* "globalCounter", change */
373 						/* counter */
374 	uint8_t		an_paramcounter;	/* "paramCounter", parameter */
375 						/* change counter */
376 	uint8_t		an_paramid;		/* "paramId", param modified */
377 	uint16_t	an_paramval;		/* "paramVal", new var of */
378 						/* last param modified */
379 
380 	uint8_t	an_writeconfigcounter;		/* "writeConfigCounter", */
381 						/* write config occurred */
382 	uint8_t	res1[3];			/* "writeConfigRsvd" */
383 
384 	uint8_t	an_ldrvopcounter;		/* "ldrvOpCounter", logical */
385 						/* drive operation */
386 	uint8_t	an_ldrvopid;			/* "ldrvOpId", ldrv num */
387 	uint8_t	an_ldrvopcmd;			/* "ldrvOpCmd", ldrv */
388 						/* operations */
389 	uint8_t	an_ldrvopstatus;		/* "ldrvOpStatus", status of */
390 						/* the operation */
391 
392 	uint8_t	an_ldrvstatecounter;		/* "ldrvStateCounter", change */
393 						/* of logical drive state */
394 	uint8_t	an_ldrvstateid;			/* "ldrvStateId", ldrv num */
395 	uint8_t	an_ldrvstatenew;		/* "ldrvStateNew", new state */
396 	uint8_t	an_ldrvstateold;		/* "ldrvStateOld", old state */
397 
398 	uint8_t	an_pdrvstatecounter;		/* "pdrvStateCounter", change */
399 						/* of physical drive state */
400 	uint8_t	an_pdrvstateid;			/* "pdrvStateId", pdrv id */
401 	uint8_t	an_pdrvstatenew;		/* "pdrvStateNew", new state */
402 	uint8_t	an_pdrvstateold;		/* "pdrvStateOld", old state */
403 
404 	uint8_t	an_pdrvfmtcounter;		/* "pdrvFmtCounter", pdrv */
405 						/* format started/over */
406 	uint8_t	an_pdrvfmtid;			/* "pdrvFmtId", pdrv id */
407 	uint8_t	an_pdrvfmtval;			/* "pdrvFmtVal", format */
408 						/* started/over */
409 	uint8_t	res2;				/* "pdrvFmtRsvd" */
410 
411 	uint8_t	an_targxfercounter;		/* "targXferCounter", scsi */
412 						/* xfer rate change */
413 	uint8_t	an_targxferid;			/* "targXferId", pdrv id */
414 	uint8_t	an_targxferval;			/* "targXferVal", new Xfer */
415 						/* params of last pdrv */
416 	uint8_t	res3;				/* "targXferRsvd" */
417 
418 	uint8_t	an_fcloopidcounter;		/* "fcLoopIdChgCounter", */
419 						/* FC/AL loop ID changed */
420 	uint8_t	an_fcloopidpdrvid;		/* "fcLoopIdPdrvId", pdrv id */
421 	uint8_t	an_fcloopid0;			/* "fcLoopId0", loopid on fc */
422 						/* loop 0 */
423 	uint8_t	an_fcloopid1;			/* "fcLoopId1", loopid on fc */
424 						/* loop 1 */
425 
426 	uint8_t	an_fcloopstatecounter;		/* "fcLoopStateCounter", */
427 						/* FC/AL loop status changed */
428 	uint8_t	an_fcloopstate0;		/* "fcLoopState0", state of */
429 						/* fc loop 0 */
430 	uint8_t	an_fcloopstate1;		/* "fcLoopState1", state of */
431 						/* fc loop 1 */
432 	uint8_t	res4;				/* "fcLoopStateRsvd" */
433 	uint8_t	pad[88];
434 };
435 
436 /*
437  * an_param values
438  */
439 #define	AMR_PARAM_REBUILD_RATE		0x01
440 #define	AMR_PARAM_FLUSH_INTERVAL	0x02
441 #define	AMR_PARAM_SENSE_ALERT		0x03
442 #define	AMR_PARAM_DRIVE_INSERTED	0x04
443 #define	AMR_PARAM_BATTERY_STATUS	0x05
444 
445 /*
446  * an_ldrvopcmd values
447  */
448 #define	AMR_LDRVOP_CHECK		0x01
449 #define	AMR_LDRVOP_INIT			0x02
450 #define	AMR_LDRVOP_REBUILD		0x03
451 
452 /*
453  * an_ldrvopstatus: return values after issuing command
454  * via an_ldrvopcmd.
455  */
456 #define	AMR_LDRVOP_SUCCESS		0x00
457 #define	AMR_LDRVOP_FAILED		0x01
458 #define	AMR_LDRVOP_ABORTED		0x02
459 #define	AMR_LDRVOP_CORRECTED		0x03
460 #define	AMR_LDRVOP_STARTED		0x04
461 
462 /*
463  * an_pdrvfmtval: Formatting commands/return values
464  */
465 #define	AMR_FORMAT_START		0x01
466 #define	AMR_FORMAT_COMPLETE		0x02
467 
468 /*
469  * Enquiry response structure for AMR_CMD_ENQUIRY, AMR_CMD_EXT_ENQUIRY and
470  * AMR_CMD_EXT_ENQUIRY2.
471  */
472 struct amr_enquiry
473 {
474 	struct amr_adapter_info		ae_adapter;
475 	struct amr_logdrive_info	ae_ldrv;
476 	struct amr_physdrive_info	ae_pdrv;
477 	uint8_t				ae_formatting[AMR_8LD_MAXDRIVES];
478 	uint8_t				res1[AMR_8LD_MAXDRIVES];
479 	uint32_t			ae_extlen;
480 	uint16_t			ae_subsystem;
481 	uint16_t			ae_subvendor;
482 	uint32_t			ae_signature;
483 	uint8_t				res2[844];
484 };
485 
486 /*
487  * ae_signature values
488  */
489 #define	AMR_SIG_431			0xfffe0001
490 #define	AMR_SIG_438			0xfffd0002
491 #define	AMR_SIG_762			0xfffc0003
492 #define	AMR_SIG_T5			0xfffb0004
493 #define	AMR_SIG_466			0xfffa0005
494 #define	AMR_SIG_467			0xfff90006
495 #define	AMR_SIG_T7			0xfff80007
496 #define	AMR_SIG_490			0xfff70008
497 
498 /*
499  * Enquiry3 structure
500  */
501 struct amr_enquiry3
502 {
503 	uint32_t	ae_datasize;		/* "dataSize", current size */
504 						/* in bytes(resvd excluded) */
505 	struct amr_notify	ae_notify;	/* "notify", event notify */
506 						/* structure */
507 	uint8_t		ae_rebuildrate;		/* "rbldRate", current */
508 						/* rebuild rate in % */
509 	uint8_t		ae_cacheflush;		/* "cacheFlushInterval", */
510 						/* flush interval in seconds */
511 	uint8_t		ae_sensealert;		/* "senseAlert" */
512 	uint8_t		ae_driveinsertcount;	/* "driveInsertedCount", */
513 						/* count of inserted drives */
514 	uint8_t		ae_batterystatus;	/* "batteryStatus" */
515 	uint8_t		ae_numldrives;		/* "numLDrv", number of logic */
516 						/* drivers configured */
517 	uint8_t		ae_reconstate[AMR_40LD_MAXDRIVES/8];
518 						/* "reconState", */
519 						/* reconstruction state */
520 	uint16_t	ae_opstatus[AMR_40LD_MAXDRIVES/8];
521 						/* "lDrvOpStatus", operation */
522 						/* state per logic driver */
523 	uint32_t	ae_drivesize[AMR_40LD_MAXDRIVES];
524 						/* "lDrvSize", size of each */
525 						/* logic driver */
526 	uint8_t		ae_driveprop[AMR_40LD_MAXDRIVES];
527 						/* "lDrvProp", properties of */
528 						/* each logic driver */
529 	uint8_t		ae_drivestate[AMR_40LD_MAXDRIVES];
530 						/* "lDrvState", state of */
531 						/* each logic driver */
532 	uint8_t		ae_pdrivestate[AMR_40LD_MAXPHYSDRIVES];
533 						/* "pDrvState", state of each */
534 						/* physical driver */
535 	uint16_t	ae_pdriveformat[AMR_40LD_MAXPHYSDRIVES/16];
536 						/* "physDrvFormat" */
537 	uint8_t		ae_targxfer[80];	/* "targXfer", physical drive */
538 						/* transfer rates */
539 	uint8_t		res1[263];		/* pad to 1024 bytes */
540 };
541 
542 /*
543  * Product Info structure. Query for this via AMR_CONFIG_PRODUCT_INFO.
544  */
545 struct amr_prodinfo
546 {
547 	uint32_t	ap_size;		/* "DataSize", current size */
548 						/* in bytes */
549 	uint32_t	ap_configsig;		/* "ConfigSignature", default */
550 						/* is 0x00282008, indicating */
551 						/* 0x28 max logical drives, */
552 						/* 0x20 maximum stripes and */
553 						/* 0x08 maximum spans */
554 	uint8_t		ap_firmware[16];	/* "FwVer", firmware version */
555 	uint8_t		ap_bios[16];		/* "BiosVer", Bios version */
556 	uint8_t		ap_product[80];		/* "ProductName", prod name */
557 	uint8_t		ap_maxio;		/* "MaxConcCmds", max number */
558 						/* of concurrent commands */
559 	uint8_t		ap_nschan;		/* "SCSIChanPresent", number */
560 						/* of SCSI channels present */
561 	uint8_t		ap_fcloops;		/* "FCLoopPresent", number of */
562 						/* fibre loops present */
563 	uint8_t		ap_memtype;		/* "memType", memory type */
564 	uint32_t	ap_signature;		/* "signature" */
565 	uint16_t	ap_memsize;		/* "DramSize", onboard memory */
566 						/* in MB */
567 	uint16_t	ap_subsystem;		/* "subSystemID", subsystem */
568 						/* identifier */
569 	uint16_t	ap_subvendor;		/* "subSystemVendorID" */
570 	uint8_t		ap_numnotifyctr;	/* "numNotifyCounters", num */
571 						/* of notify counters */
572 };
573 
574 /*
575  * The union for used enquiry commands
576  */
577 union amr_enq_buffer
578 {
579 	struct amr_enquiry3	aeb_enquiry3;
580 	struct amr_enquiry	aeb_enquiry;
581 	struct amr_prodinfo	aeb_prodinfo;
582 };
583 
584 #pragma pack()
585 
586 #ifdef _KERNEL
587 
588 /*
589  * I/O Port offsets
590  */
591 #define	ACK_BYTE		0x08
592 #define	I_CMD_PORT		0x00
593 #define	I_ACK_PORT		0x00
594 #define	I_TOGGLE_PORT		0x01
595 #define	INTR_PORT		0x0a
596 #define	ENABLE_INTR_BYTE	0xc0
597 #define	DISABLE_INTR_BYTE  	0x00
598 #define	AMR_QINTR		0x0a
599 #define	AMR_QINTR_VALID		0x40
600 
601 #define	AMR_QGET_ISTAT(sc)	pci_config_get8(sc->regsmap_handle, AMR_QINTR)
602 #define	AMR_QCLEAR_INTR(sc)	pci_config_put8(sc->regsmap_handle, \
603 				I_ACK_PORT,  ACK_BYTE)
604 #define	AMR_QENABLE_INTR(sc)	pci_config_put8(sc->regsmap_handle, \
605 				I_TOGGLE_PORT,  ENABLE_INTR_BYTE)
606 #define	AMR_QDISABLE_INTR(sc)	pci_config_put8(sc->regsmap_handle, \
607 				I_TOGGLE_PORT,  DISABLE_INTR_BYTE)
608 #define	AMR_CFG_SIG		0xa0	/* PCI config register for signature */
609 #define	AMR_SIGNATURE_1		0xCCCC	/* i960 signature (older adapters) */
610 #define	AMR_SIGNATURE_2		0x3344	/* i960 signature (newer adapters) */
611 
612 /*
613  * Doorbell registers
614  */
615 #define	AMR_QIDB		0x20
616 #define	AMR_QODB		0x2c
617 #define	AMR_QIDB_SUBMIT		0x00000001 /* mailbox ready for work */
618 #define	AMR_QIDB_ACK		0x00000002 /* mailbox done */
619 #define	AMR_QODB_READY		0x10001234 /* work ready to be processed */
620 
621 /*
622  * Initialisation status
623  */
624 #define	AMR_QINIT_SCAN		0x01	/* init scanning drives */
625 #define	AMR_QINIT_SCANINIT	0x02	/* init scanning initialising */
626 #define	AMR_QINIT_FIRMWARE	0x03	/* init firmware initing */
627 #define	AMR_QINIT_INPROG	0xdc	/* init in progress */
628 #define	AMR_QINIT_SPINUP	0x2c	/* init spinning drives */
629 #define	AMR_QINIT_NOMEM		0xac	/* insufficient memory */
630 #define	AMR_QINIT_CACHEFLUSH	0xbc	/* init flushing cache */
631 #define	AMR_QINIT_DONE		0x9c	/* init successfully done */
632 
633 /*
634  * I/O primitives
635  */
636 #define	AMR_QPUT_IDB(sc, val)	pci_config_put32(sc->regsmap_handle, \
637 							AMR_QIDB, val)
638 #define	AMR_QGET_IDB(sc)	pci_config_get32(sc->regsmap_handle, \
639 							AMR_QIDB)
640 #define	AMR_QPUT_ODB(sc, val)	pci_config_put32(sc->regsmap_handle, \
641 							AMR_QODB, val)
642 #define	AMR_QGET_ODB(sc)	pci_config_get32(sc->regsmap_handle, \
643 							AMR_QODB)
644 
645 /*
646  * I/O registers
647  */
648 #define	AMR_SCMD		0x10	/* command/ack register (write) */
649 #define	AMR_SMBOX_BUSY		0x10	/* mailbox status (read) */
650 #define	AMR_STOGGLE		0x11	/* interrupt enable bit here */
651 #define	AMR_SMBOX_0		0x14	/* mailbox physical address low byte */
652 #define	AMR_SMBOX_1		0x15
653 #define	AMR_SMBOX_2		0x16
654 #define	AMR_SMBOX_3		0x17	/* high byte */
655 #define	AMR_SMBOX_ENABLE	0x18	/* atomic mailbox address enable */
656 #define	AMR_SINTR		0x1a	/* interrupt status */
657 
658 /*
659  * I/O magic numbers
660  */
661 #define	AMR_SCMD_POST		0x10	/* SCMD to initiate action on mailbox */
662 #define	AMR_SCMD_ACKINTR	0x08	/* SCMD to ack mailbox retrieved */
663 #define	AMR_STOGL_IENABLE	0xc0	/* in STOGGLE */
664 #define	AMR_SINTR_VALID		0x40	/* in SINTR */
665 #define	AMR_SMBOX_BUSYFLAG	0x10	/* in SMBOX_BUSY */
666 #define	AMR_SMBOX_ADDR		0x00	/* SMBOX_ENABLE */
667 
668 /*
669  * Initialisation status
670  */
671 #define	AMR_SINIT_ABEND		0xee	/* init abnormal terminated */
672 #define	AMR_SINIT_NOMEM		0xca	/* insufficient memory */
673 #define	AMR_SINIT_CACHEFLUSH	0xbb	/* firmware flushing cache */
674 #define	AMR_SINIT_INPROG	0x11	/* init in progress */
675 #define	AMR_SINIT_SPINUP	0x22	/* firmware spinning drives */
676 #define	AMR_SINIT_DONE		0x99	/* init successfully done */
677 
678 /*
679  * I/O primitives
680  */
681 #define	AMR_SPUT_ISTAT(sc, val)	pci_config_put8(sc->regsmap_handle, \
682 					AMR_SINTR, val)
683 #define	AMR_SGET_ISTAT(sc)	pci_config_get8(sc->regsmap_handle, AMR_SINTR)
684 #define	AMR_SACK_INTERRUPT(sc)	pci_config_put8(sc->regsmap_handle, \
685 					AMR_SCMD, AMR_SCMD_ACKINTR)
686 #define	AMR_SPOST_COMMAND(sc)	pci_config_put8(sc->regsmap_handle, AMR_SCMD, \
687 					AMR_SCMD_POST)
688 #define	AMR_SGET_MBSTAT(sc)	pci_config_get8(sc->regsmap_handle, \
689 					AMR_SMBOX_BUSY)
690 
691 #define	AMR_SENABLE_INTR(sc)	\
692 	pci_config_put8(sc->regsmap_handle, AMR_STOGGLE, \
693 		pci_config_get8(sc->regsmap_handle, AMR_STOGGLE) \
694 		| AMR_STOGL_IENABLE)
695 
696 #define	AMR_SDISABLE_INTR(sc)	\
697 	pci_config_put8(sc->regsmap_handle, AMR_STOGGLE, \
698 		pci_config_get8(sc->regsmap_handle, AMR_STOGGLE) \
699 		& ~AMR_STOGL_IENABLE)
700 
701 #define	AMR_SBYTE_SET(sc, reg, val) pci_config_put8(sc->regsmap_handle, \
702 					reg, val)
703 
704 #endif /* _KERNEL */
705 
706 #ifdef	__cplusplus
707 }
708 #endif
709 
710 #endif /* _AMRREG_H */
711