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33 ******************************************************************************/
34 /*$FreeBSD$*/
35 
36 #ifndef _IXGBE_DCB_82598_H_
37 #define _IXGBE_DCB_82598_H_
38 
39 /* DCB register definitions */
40 
41 #define IXGBE_DPMCS_MTSOS_SHIFT	16
42 #define IXGBE_DPMCS_TDPAC	0x00000001 /* 0 Round Robin,
43 					    * 1 DFP - Deficit Fixed Priority */
44 #define IXGBE_DPMCS_TRM		0x00000010 /* Transmit Recycle Mode */
45 #define IXGBE_DPMCS_ARBDIS	0x00000040 /* DCB arbiter disable */
46 #define IXGBE_DPMCS_TSOEF	0x00080000 /* TSO Expand Factor: 0=x4, 1=x2 */
47 
48 #define IXGBE_RUPPBMR_MQA	0x80000000 /* Enable UP to queue mapping */
49 
50 #define IXGBE_RT2CR_MCL_SHIFT	12 /* Offset to Max Credit Limit setting */
51 #define IXGBE_RT2CR_LSP		0x80000000 /* LSP enable bit */
52 
53 #define IXGBE_RDRXCTL_MPBEN	0x00000010 /* DMA config for multiple packet
54 					    * buffers enable */
55 #define IXGBE_RDRXCTL_MCEN	0x00000040 /* DMA config for multiple cores
56 					    * (RSS) enable */
57 
58 #define IXGBE_TDTQ2TCCR_MCL_SHIFT	12
59 #define IXGBE_TDTQ2TCCR_BWG_SHIFT	9
60 #define IXGBE_TDTQ2TCCR_GSP	0x40000000
61 #define IXGBE_TDTQ2TCCR_LSP	0x80000000
62 
63 #define IXGBE_TDPT2TCCR_MCL_SHIFT	12
64 #define IXGBE_TDPT2TCCR_BWG_SHIFT	9
65 #define IXGBE_TDPT2TCCR_GSP	0x40000000
66 #define IXGBE_TDPT2TCCR_LSP	0x80000000
67 
68 #define IXGBE_PDPMCS_TPPAC	0x00000020 /* 0 Round Robin,
69 					    * 1 DFP - Deficit Fixed Priority */
70 #define IXGBE_PDPMCS_ARBDIS	0x00000040 /* Arbiter disable */
71 #define IXGBE_PDPMCS_TRM	0x00000100 /* Transmit Recycle Mode enable */
72 
73 #define IXGBE_DTXCTL_ENDBUBD	0x00000004 /* Enable DBU buffer division */
74 
75 #define IXGBE_TXPBSIZE_40KB	0x0000A000 /* 40KB Packet Buffer */
76 #define IXGBE_RXPBSIZE_48KB	0x0000C000 /* 48KB Packet Buffer */
77 #define IXGBE_RXPBSIZE_64KB	0x00010000 /* 64KB Packet Buffer */
78 #define IXGBE_RXPBSIZE_80KB	0x00014000 /* 80KB Packet Buffer */
79 
80 /* DCB driver APIs */
81 
82 /* DCB PFC */
83 s32 ixgbe_dcb_config_pfc_82598(struct ixgbe_hw *, u8);
84 
85 /* DCB stats */
86 s32 ixgbe_dcb_config_tc_stats_82598(struct ixgbe_hw *);
87 s32 ixgbe_dcb_get_tc_stats_82598(struct ixgbe_hw *,
88 				 struct ixgbe_hw_stats *, u8);
89 s32 ixgbe_dcb_get_pfc_stats_82598(struct ixgbe_hw *,
90 				  struct ixgbe_hw_stats *, u8);
91 
92 /* DCB config arbiters */
93 s32 ixgbe_dcb_config_tx_desc_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *,
94 					   u8 *, u8 *);
95 s32 ixgbe_dcb_config_tx_data_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *,
96 					   u8 *, u8 *);
97 s32 ixgbe_dcb_config_rx_arbiter_82598(struct ixgbe_hw *, u16 *, u16 *, u8 *);
98 
99 /* DCB initialization */
100 s32 ixgbe_dcb_hw_config_82598(struct ixgbe_hw *, int, u16 *, u16 *, u8 *, u8 *);
101 #endif /* _IXGBE_DCB_82958_H_ */
102