1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright (c) 2005, 2010, Oracle and/or its affiliates. All rights reserved. 24 */ 25 26 #ifndef _PCIEX_PCI_NVIDIA_H 27 #define _PCIEX_PCI_NVIDIA_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * PCI Configuration (Nvidia, PCIe) related library functions 35 */ 36 boolean_t look_for_any_pciex_device(uchar_t); 37 boolean_t check_if_device_is_pciex(dev_info_t *, uchar_t, uchar_t, 38 uchar_t, boolean_t *, ushort_t *, ushort_t *); 39 boolean_t create_pcie_root_bus(uchar_t, dev_info_t *); 40 void add_nvidia_isa_bridge_props(dev_info_t *, uchar_t, uchar_t, 41 uchar_t); 42 43 /* Generic Nvidia chipset IDs and defines */ 44 #define NVIDIA_VENDOR_ID 0x10de /* Nvidia Vendor Id */ 45 #define NVIDIA_INTR_BCR_OFF 0x3C /* NV_XVR_INTR_BCR */ 46 #define NVIDIA_INTR_BCR_SERR_FORWARD_BIT 0x02 /* SERR_FORWARD bit */ 47 48 /* CK8-04 PCIe RC and LPC-PCI Bridge device IDs */ 49 #define NVIDIA_CK804_DEVICE_ID 0x5d /* ck8-04 dev id */ 50 #define NVIDIA_CK804_DEFAULT_ISA_BRIDGE_DEVID 0x50 /* LPC Default Bridge */ 51 #define NVIDIA_CK804_PRO_ISA_BRIDGE_DEVID 0x51 /* LPC Bridge */ 52 #define NVIDIA_CK804_SLAVE_ISA_BRIDGE_DEVID 0xd3 /* Slave LPC Bridge */ 53 #define NVIDIA_CK804_AER_VALID_REVID 0xa3 /* RID w/ AER enabled */ 54 55 #define NVIDIA_CK804_LPC2PCI_DEVICE_ID(did) \ 56 (((did) == NVIDIA_CK804_DEFAULT_ISA_BRIDGE_DEVID) || \ 57 ((did) == NVIDIA_CK804_PRO_ISA_BRIDGE_DEVID) || \ 58 ((did) == NVIDIA_CK804_SLAVE_ISA_BRIDGE_DEVID)) 59 60 /* 61 * Only for Nvidia's CrushK 8-04 chipsets: 62 * To enable hotplug; we need to map in two I/O BARs 63 * from ISA bridge's config space 64 */ 65 #define NVIDIA_CK804_ISA_SYSCTRL_BAR_OFF 0x64 /* System Control BAR */ 66 #define NVIDIA_CK804_ISA_ANALOG_BAR_OFF 0x68 /* Analog BAR */ 67 68 /* NV_XVR_VEND_CYA1 related defines */ 69 #define NVIDIA_CK804_VEND_CYA1_OFF 0xf40 /* NV_XVR_VEND_CYA1 */ 70 #define NVIDIA_CK804_VEND_CYA1_ERPT_VAL 0x2000 /* enable CYA1 ERPT */ 71 #define NVIDIA_CK804_VEND_CYA1_ERPT_MASK 0xdfff /* CYA1 ERPT mask */ 72 73 /* 74 * C51 related defines 75 */ 76 77 /* C51 PCIe Root Complex Device ID defines */ 78 #define NVIDIA_C51_DEVICE_ID_XVR16 0x2fb 79 #define NVIDIA_C51_DEVICE_ID_XVR1_0 0x2fc 80 #define NVIDIA_C51_DEVICE_ID_XVR1_1 0x2fd 81 82 #define NVIDIA_C51_DEVICE_ID(did) \ 83 (((did) == NVIDIA_C51_DEVICE_ID_XVR16) || \ 84 ((did) == NVIDIA_C51_DEVICE_ID_XVR1_0) || \ 85 ((did) == NVIDIA_C51_DEVICE_ID_XVR1_1)) 86 87 /* 88 * MCP55 related defines 89 */ 90 91 /* MCP55 PCIe Root Complex Device ID defines */ 92 #define NVIDIA_MCP55_DEVICE_ID_XVR4 0x374 93 #define NVIDIA_MCP55_DEVICE_ID_XVR8 0x375 94 #define NVIDIA_MCP55_DEVICE_ID_XVR8_VC1 0x376 95 #define NVIDIA_MCP55_DEVICE_ID_XVR16 0x377 96 #define NVIDIA_MCP55_DEVICE_ID_XVR4_VC1 0x378 97 98 #define NVIDIA_MCP55_DEVICE_ID(did) \ 99 (((did) == NVIDIA_MCP55_DEVICE_ID_XVR4) || \ 100 ((did) == NVIDIA_MCP55_DEVICE_ID_XVR8) || \ 101 ((did) == NVIDIA_MCP55_DEVICE_ID_XVR16) || \ 102 ((did) == NVIDIA_MCP55_DEVICE_ID_XVR4_VC1) || \ 103 ((did) == NVIDIA_MCP55_DEVICE_ID_XVR8_VC1)) 104 105 /* MCP55 LPC-PCI Bridge Device ID defines */ 106 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP0 0x360 107 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP1 0x361 108 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP2 0x362 109 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP3 0x363 110 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP4 0x364 111 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP5 0x365 112 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP6 0x366 113 #define NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP7 0x367 114 115 #define NVIDIA_MCP55_LPC2PCI_DEVICE_ID(did) \ 116 (((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP0) || \ 117 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP1) || \ 118 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP2) || \ 119 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP3) || \ 120 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP4) || \ 121 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP5) || \ 122 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP6) || \ 123 ((did) == NVIDIA_MCP55_PCI2LPC_DEVICE_ID_OP7)) 124 125 /* 126 * MCP61 related defines 127 */ 128 129 /* MCP61 PCIe Root Complex Device ID defines */ 130 #define NVIDIA_MCP61_DEVICE_ID_XVR4 0x3e8 131 #define NVIDIA_MCP61_DEVICE_ID_XVR8 0x3e9 132 133 #define NVIDIA_MCP61_DEVICE_ID(did) \ 134 (((did) == NVIDIA_MCP61_DEVICE_ID_XVR4) || \ 135 ((did) == NVIDIA_MCP61_DEVICE_ID_XVR8)) 136 137 /* 138 * MCP65 related defines 139 */ 140 141 /* MCP65 PCIe Root Complex Device ID defines */ 142 #define NVIDIA_MCP65_DEVICE_ID_XVR4 0x458 143 #define NVIDIA_MCP65_DEVICE_ID_XVR8 0x459 144 #define NVIDIA_MCP65_DEVICE_ID_XVR16 0x45a 145 146 #define NVIDIA_MCP65_DEVICE_ID(did) \ 147 (((did) == NVIDIA_MCP65_DEVICE_ID_XVR4) || \ 148 ((did) == NVIDIA_MCP65_DEVICE_ID_XVR8) || \ 149 ((did) == NVIDIA_MCP65_DEVICE_ID_XVR16)) 150 151 /* 152 * Check if the given device is a Nvidia's LPC bridge 153 */ 154 #define NVIDIA_IS_LPC_BRIDGE(vid, did) \ 155 (((vid) == NVIDIA_VENDOR_ID) && \ 156 (NVIDIA_CK804_LPC2PCI_DEVICE_ID(did) || \ 157 NVIDIA_MCP55_LPC2PCI_DEVICE_ID(did))) 158 159 /* Check for PCIe RC Device ID */ 160 #define NVIDIA_PCIE_RC_DEV_ID(did) \ 161 (((did) == NVIDIA_CK804_DEVICE_ID) || \ 162 NVIDIA_C51_DEVICE_ID(did) || \ 163 NVIDIA_MCP55_DEVICE_ID(did) || \ 164 NVIDIA_MCP61_DEVICE_ID(did) || \ 165 NVIDIA_MCP65_DEVICE_ID(did)) 166 167 #ifdef __cplusplus 168 } 169 #endif 170 171 #endif /* _PCIEX_PCI_NVIDIA_H */ 172