1#
2# CDDL HEADER START
3#
4# The contents of this file are subject to the terms of the
5# Common Development and Distribution License, Version 1.0 only
6# (the "License").  You may not use this file except in compliance
7# with the License.
8#
9# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10# or http://www.opensolaris.org/os/licensing.
11# See the License for the specific language governing permissions
12# and limitations under the License.
13#
14# When distributing Covered Code, include this CDDL HEADER in each
15# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16# If applicable, add the following below this CDDL HEADER, with the
17# fields enclosed by brackets "[]" replaced with your own identifying
18# information: Portions Copyright [yyyy] [name of copyright owner]
19#
20# CDDL HEADER END
21#
22#
23# Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24# Use is subject to license terms.
25#
26#pragma ident	"%Z%%M%	%I%	%E% SMI"
27#
28
29name="ppm" parent="pseudo" instance=0;
30
31#
32# ppm configuration format
33#
34# "ppm-domains" - in form of "domain_xxx" where "xxx" string highlights
35# the nature of the domain;
36#
37# "domain_xxx-model" - PM model: CPU, PCI, PCI_PROP, FET or LED.
38#
39# "domain_xxx-propname" - a property name that is exported by device in
40# a domain.  Currently, it is used by PCI_PROP model to identify devices
41# that are to have their clocks stopped when all power-manageable devices
42# in the domain are at D3 power level.
43#
44# "domain-xxx-devices" - a list of prom path match patterns to match devices
45# that fall into "domain_xxx", where wildcard '*' is allowed by observing
46# the following expectations:
47#	. a single wildcard with exact match up to (but exclude) the wildcard
48#	  which then terminates the match pattern;
49#	. a single wildcard that does not terminate a match pattern must
50#	  match driver name (followed by '@');
51#	. with two wildcard occurences, the first is to match driver name,
52#	  the second function id, as well as the last character of the match
53#	  pattern.
54#
55# "domain-xxx-ctrl" - blank space separated definitions in the form of
56# keyword=definition [keyword=definition...]
57#    The keywords are as follows, where 'method' must come before mask as it
58#       tells how to store 'mask' and 'val'.  Missing 'val' defaults to 0.
59#
60#    which keywords apply depends on cmd.  There are two sets as shown below.
61#    Here is the first:
62#	cmd=[CPU_GO | LED_ON | LED_OFF | FET_ON | FET_OFF | CLK_ON | CLK_OFF]
63# 	path=<prompath>	- control device's prom pathname (includes minor)
64# 	method=[KIO|I2CKIO]	This selects a method which may be
65#		an ioctl that sets a single value or an i2c ioctl that
66#		takes a value and a mask to access gpio register
67#	iord=<integer> - value of ioctl command for reading
68#	iowr=<integer> - value of ioctl command for writing
69# 	val=<integer>	- a single integer value, generally the value to which
70#			  the relevant bits of a register will be set
71#	mask=<integer>	- which bits of val are relevant (if method is I2CKIO)
72#
73#    Here is the second:
74#	cmd=[CPU_NEXT | PRE_CHNG | POST_CHNG]
75# 	path=<prompath>	   - control device's prom pathname, including minor
76# 	method=[CPUSPEEDKIO | VCORE]  This selects a method that uses
77#			     information like cpu speed index, value for
78#			     adjust cpu core voltage, delays, etc.
79#	iowr=<integer>     - value of ioctl write command
80#	speeds=<integer>   - indicates the number of cpu speeds that are
81#			     supported
82
83ppm-domains="domain_cpu", "domain_scsifet1", "domain_scsifet2",
84    "domain_idefet", "domain_led", "domain_pcislot_0", "domain_pcislot_1",
85    "domain_pcislot_2", "domain_pcislot_3", "domain_pcislot_4",
86    "domain_pcislot_5";
87
88
89#
90# 0x6a02 is JBPPMIOC_NEXT	(('j' << 8) | 2)
91# 0x6a03 is JBPPMIOC_GO		(('j' << 8) | 3)
92# 0x6c02 is M1535PPMIOC_SET     (('l' << 8) | 2)
93#  'delay' unit is us(microsecond)
94#
95domain_cpu-devices="/SUNW,UltraSPARC-IIIi@*";
96domain_cpu-model="CPU";
97domain_cpu-control=
98    "cmd=CPU_NEXT path=/ppm@1e,0:jbus-ppm method=CPUSPEEDKIO iowr=0x6a02 speeds=3",
99    "cmd=CPU_NEXT path=/ppm@1c,0:jbus-ppm method=CPUSPEEDKIO iowr=0x6a02 speeds=3",
100    "cmd=PRE_CHNG path=/pci@1e,600000/pmu@6/ppm@0,b3:gpo32 method=VCORE iowr=0x6c02 iord=0x6c01 val=4 delay=150000",
101    "cmd=CPU_GO path=/ppm@1e,0:jbus-ppm method=KIO iowr=0x6a03 val=0",
102    "cmd=POST_CHNG path=/pci@1e,600000/pmu@6/ppm@0,b3:gpo32 method=VCORE iowr=0x6c02 iord=0x6c01 val=5";
103
104#
105# iowr -- 0x4D82 is GPIO_SET_OUTPUT per sys/i2c/clients/i2c_gpio.h file
106# iord -- 0x4D80 is GPIO_GET_INPUT per sys/i2c/clients/i2c_gpio.h file
107# mask -- bit mask for control pin
108# val  -- pin value to set on/off
109# delay -- minimum delay between FET off and FET on
110# post_delay -- delay after turning on/off the FET
111#
112domain_scsifet1-devices = "/pci@1d,700000/scsi@3/sd@0,0", "/pci@1d,700000/scsi@4/sd@0,0";
113domain_scsifet1-model = "FET";
114domain_scsifet1-control =
115    "cmd=FET_ON path=/pci@1e,600000/isa@7/i2c@0,320/gpio@0,30:pca9556_0 method=I2CKIO iowr=0x4D82 iord=0x4D80 mask=0x80 val=0x80 post_delay=1500000",
116    "cmd=FET_OFF path=/pci@1e,600000/isa@7/i2c@0,320/gpio@0,30:pca9556_0 method=I2CKIO iowr=0x4D82 iord=0x4D80 mask=0x80 val=0";
117
118domain_scsifet2-devices = "/pci@1d,700000/scsi@3/sd@1,0", "/pci@1d,700000/scsi@4/sd@1,0";
119domain_scsifet2-model = "FET";
120domain_scsifet2-control =
121    "cmd=FET_ON path=/pci@1e,600000/isa@7/i2c@0,320/gpio@0,30:pca9556_0 method=I2CKIO iowr=0x4D82 iord=0x4D80 mask=0x02 val=0x02 post_delay=1500000",
122    "cmd=FET_OFF path=/pci@1e,600000/isa@7/i2c@0,320/gpio@0,30:pca9556_0 method=I2CKIO iowr=0x4D82 iord=0x4D80 mask=0x02 val=0";
123
124
125#
126# If we power up ide fet after powering up uata controller, atapi ide dvd
127# stuck at low power - a problem under investigation. Until the problem is
128# solved, we work around it by applying the fet to ide controller.
129#
130domain_idefet-devices = "/pci@1e,600000/ide@d";
131domain_idefet-model = "FET";
132domain_idefet-control =
133    "cmd=FET_ON path=/pci@1e,600000/isa@7/i2c@0,320/gpio@0,30:pca9556_0 method=I2CKIO iowr=0x4D82 iord=0x4D80 mask=0x10 val=0x10 delay=1000000 post_delay=1000000",
134    "cmd=FET_OFF path=/pci@1e,600000/isa@7/i2c@0,320/gpio@0,30:pca9556_0 method=I2CKIO iowr=0x4D82 iord=0x4D80 mask=0x10 val=0";
135
136#
137# iord -- 0x6c01 is M1535PPMIOC_GET	(('l' << 8) | 1)
138# iowr -- 0x6c02 is M1535PPMIOC_SET	(('l' << 8) | 2)
139#
140# Enchilada: SPLED drive low
141# Grover:    SPLED driver high
142# note: no device to claim in this domain
143#
144domain_led-devices = "";
145domain_led-model = "LED";
146domain_led-control =
147    "cmd=LED_ON path=/pci@1e,600000/pmu@6/ppm@0,b3:spled method=KIO iowr=0x6c02 iord=0x6c01 val=0",
148    "cmd=LED_OFF path=/pci@1e,600000/pmu@6/ppm@0,b3:spled method=KIO iowr=0x6c02 iord=0x6c01 val=1";
149
150
151#
152# Note, in ppm.conf file, the pci slot is counted from the inner most
153# slot toward outer most in increasing order, according to Enchilada
154# motherboard schematic. The onboard physical slots however, may have
155# been labled  differently - it's been said that prior to rev G, the
156# slots are labeled/counted from inside to outside, but starting from
157# rev G slots will be labeled/counted from outside to inside.
158#
159
160# slot 0, PCI2B segment, 66mhz
161#     iowr = (ICS951601_MODIFY_CLOCK | ICS951601_PCI2B_1) = 0x2540
162#     iord = (ICS951601_READ_CLOCK   | ICS951601_PCI2B_1) = 0x1540
163#
164domain_pcislot_0-devices = "/pci@1f,700000/*@2,*", "/pci@1f,700000/*@2";
165domain_pcislot_0-model = "PCI";
166domain_pcislot_0-control =
167    "cmd=CLK_ON path=/pci@1e,600000/isa@7/i2c@0,320/clock-generator@0,d2:ics951601_0 method=KIO iowr=0x2540 iord=0x1540 val=1",
168    "cmd=CLK_OFF path=/pci@1e,600000/isa@7/i2c@0,320/clock-generator@0,d2:ics951601_0 method=KIO iowr=0x2540 iord=0x1540 val=0";
169
170#
171# slot 1, PCI2A segment, 33mhz
172#     iowr = (ICS951601_MODIFY_CLOCK | ICS951601_PCI1A_5) = 0x2320
173#
174domain_pcislot_1-devices = "/pci@1e,600000/*@2,*", "/pci@1e,600000/*@2";
175domain_pcislot_1-model = "PCI_PROP";
176domain_pcislot_1-propname = "nonidle-bus-clock-pm";
177domain_pcislot_1-control =
178    "cmd=CLK_ON path=/pci@1e,600000/isa@7/i2c@0,320/clock-generator@0,d2:ics951601_0 method=KIO iowr=0x2320 iord=0x1320 val=1",
179    "cmd=CLK_OFF path=/pci@1e,600000/isa@7/i2c@0,320/clock-generator@0,d2:ics951601_0 method=KIO iowr=0x2320 iord=0x1320 val=0";
180
181#
182# slot 2, PCI1A segment, 66mhz
183#     iowr = (ICS951601_MODIFY_CLOCK | ICS951601_PCI2A_0) = 0x2420
184#
185domain_pcislot_2-devices = "/pci@1c,600000/*@2,*", "/pci@1c,600000/*@2";
186domain_pcislot_2-model = "PCI_PROP";
187domain_pcislot_2-propname = "nonidle-bus-clock-pm";
188domain_pcislot_2-control =
189    "cmd=CLK_ON path=/pci@1e,600000/isa@7/i2c@0,320/clock-generator@0,d2:ics951601_0 method=KIO iowr=0x2420 iord=0x1420 val=1",
190    "cmd=CLK_OFF path=/pci@1e,600000/isa@7/i2c@0,320/clock-generator@0,d2:ics951601_0 method=KIO iowr=0x2420 iord=0x1420 val=0";
191
192#
193# slot 3, PCI1B segment, 66mhz
194#     iowr = (ICS951601_MODIFY_CLOCK | ICS951601_PCI1B_0) = 0x2404
195#
196domain_pcislot_3-devices = "/pci@1d,700000/*@2,*", "/pci@1d,700000/*@2";
197domain_pcislot_3-model = "PCI_PROP";
198domain_pcislot_3-propname = "nonidle-bus-clock-pm";
199domain_pcislot_3-control =
200    "cmd=CLK_ON path=/pci@1e,600000/isa@7/i2c@0,320/clock-generator@0,d2:ics951601_0 method=KIO iowr=0x2404 iord=0x1404 val=1",
201    "cmd=CLK_OFF path=/pci@1e,600000/isa@7/i2c@0,320/clock-generator@0,d2:ics951601_0 method=KIO iowr=0x2404 iord=0x1404 val=0";
202
203#
204# slot 4, PCI2A segment, 33mhz
205#     iowr = (ICS951601_MODIFY_CLOCK | ICS951601_PCI1A_1) = 0x2302
206#
207domain_pcislot_4-devices = "/pci@1e,600000/*@3,*", "/pci@1e,600000/*@3";
208domain_pcislot_4-model = "PCI_PROP";
209domain_pcislot_4-propname = "nonidle-bus-clock-pm";
210domain_pcislot_4-control =
211    "cmd=CLK_ON path=/pci@1e,600000/isa@7/i2c@0,320/clock-generator@0,d2:ics951601_0 method=KIO iowr=0x2302 iord=0x1302 val=1",
212    "cmd=CLK_OFF path=/pci@1e,600000/isa@7/i2c@0,320/clock-generator@0,d2:ics951601_0 method=KIO iowr=0x2302 iord=0x1302 val=0";
213
214#
215# slot 5, PCI2A segment, 33mhz
216#     iowr = (ICS951601_MODIFY_CLOCK | ICS951601_PCI1A_2) = 0x2304
217#
218domain_pcislot_5-devices = "/pci@1e,600000/*@4,*", "/pci@1e,600000/*@4";
219domain_pcislot_5-model = "PCI_PROP";
220domain_pcislot_5-propname = "nonidle-bus-clock-pm";
221domain_pcislot_5-control =
222    "cmd=CLK_ON path=/pci@1e,600000/isa@7/i2c@0,320/clock-generator@0,d2:ics951601_0 method=KIO iowr=0x2304 iord=0x1304 val=1",
223    "cmd=CLK_OFF path=/pci@1e,600000/isa@7/i2c@0,320/clock-generator@0,d2:ics951601_0 method=KIO iowr=0x2304 iord=0x1304 val=0";
224