xref: /illumos-gate/usr/src/uts/sun4u/sys/upa64s.h (revision f47a9c50)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _SYS_UPA64S_VAR_H
28 #define	_SYS_UPA64S_VAR_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #ifdef	__cplusplus
33 extern "C" {
34 #endif
35 
36 #define	HI32(x) ((uint32_t)(((uint64_t)(x)) >> 32))
37 #define	LO32(x) ((uint32_t)(uintptr_t)(x))
38 #define	UPA64S_PORTS	2	/* number of UPA ports per device */
39 
40 /*
41  * the following typedef is used to describe the state
42  * of a UPA port interrupt.
43  */
44 typedef enum { INO_FREE = 0, INO_INUSE } ino_state_t;
45 
46 /*
47  * INO related macros:
48  */
49 #define	UPA64S_MAKE_MONDO(id, ino)	((id) << 6 | (ino))
50 #define	UPA64S_MONDO_TO_INO(mondo) 	((mondo) & 0x3f)
51 
52 /*
53  * Interrupt Mapping Registers
54  */
55 #define	IMR_MONDO			0x7ff
56 #define	IMR_TID_BIT			26
57 #define	IMR_TID				(0x1f << IMR_TID_BIT)
58 #define	IMR_VALID			(1u << 31)
59 #define	UPA64S_IMR_TO_CPUID(imr)	(((imr) & IMR_TID) >> IMR_TID_BIT)
60 #define	UPA64S_IMR_TO_MONDO(imr)	((imr) & IMR_MONDO)
61 #define	UPA64S_CPUID_TO_IMR(cpuid)	((cpuid) << IMR_TID_BIT)
62 #define	UPA64S_GET_MAP_REG(mondo, imr)	((mondo) | (imr) | IMR_VALID)
63 
64 /*
65  * The following structure defines the format of UPA64S addresses.
66  * This structure is used to hold UPA64S "reg" property entries.
67  */
68 typedef struct upa64s_regspec {
69 	uint64_t upa64s_phys;
70 	uint64_t upa64s_size;
71 } upa64s_regspec_t;
72 
73 /*
74  * The following structure defines the format of a "ranges"
75  * property entry for UPA64S bus node.
76  */
77 typedef struct upa64s_ranges {
78 	uint64_t upa64s_child;
79 	uint64_t upa64s_parent;
80 	uint64_t upa64s_size;
81 } upa64s_ranges_t;
82 
83 /*
84  * per-upa64s soft state structure:
85  */
86 typedef struct upa64s_devstate {
87 	dev_info_t *dip;			/* devinfo structure */
88 	uint_t safari_id;			/* safari device id */
89 
90 	ino_state_t ino_state[UPA64S_PORTS];	/* INO state */
91 	uint64_t *imr[UPA64S_PORTS];		/* Intr mapping reg; treat */
92 						/* as two element array */
93 	ddi_acc_handle_t imr_ah[UPA64S_PORTS];	/* Mapping handle */
94 	uint64_t imr_data[UPA64S_PORTS];	/* imr save/restore area */
95 
96 	caddr_t config_base;			/* conf base address */
97 	uint64_t *upa0_config;			/* UPA 0 config */
98 	uint64_t *upa1_config;			/* UPA 1 config */
99 	uint64_t *if_config;			/* UPA inteface config */
100 	uint64_t *estar;			/* UPA estar control */
101 	ddi_acc_handle_t config_base_ah;	/* config acc handle */
102 
103 	int power_level;			/* upa64s' power level */
104 	int saved_power_level;			/* power level during suspend */
105 } upa64s_devstate_t;
106 
107 /*
108  * UPA64S Register Offsets
109  */
110 #define	UPA64S_UPA0_CONFIG_OFFSET	0x00
111 #define	UPA64S_UPA1_CONFIG_OFFSET	0x08
112 #define	UPA64S_IF_CONFIG_OFFSET		0x10
113 #define	UPA64S_ESTAR_OFFSET		0x18
114 
115 /*
116  * UPA64S Interface Configurations
117  */
118 #define	UPA64S_NOT_POK_RST_L	0x0
119 #define	UPA64S_POK_RST_L	0x2
120 #define	UPA64S_POK_NOT_RST_L	0x3
121 
122 /*
123  * UPA64S Energy Star Control Register
124  */
125 #define	UPA64S_FULL_SPEED	0x01
126 #define	UPA64S_1_2_SPEED	0x02
127 #define	UPA64S_1_64_SPEED	0x40
128 
129 /*
130  * Power Management definitions
131  */
132 #define	UPA64S_PM_COMP		0		/* power management component */
133 #define	UPA64S_PM_UNKNOWN	-1		/* power unknown */
134 #define	UPA64S_PM_RESET		0		/* power off */
135 #define	UPA64S_PM_NORMOP	1		/* power on */
136 
137 /*
138  * upa64s soft state macros:
139  */
140 #define	get_upa64s_soft_state(i)	\
141 	((upa64s_devstate_t *)ddi_get_soft_state(per_upa64s_state, (i)))
142 #define	alloc_upa64s_soft_state(i)	\
143 	ddi_soft_state_zalloc(per_upa64s_state, (i))
144 #define	free_upa64s_soft_state(i)	\
145 	ddi_soft_state_free(per_upa64s_state, (i))
146 
147 /*
148  * debugging definitions:
149  */
150 #if defined(DEBUG)
151 #define	D_ATTACH	0x00000001
152 #define	D_DETACH	0x00000002
153 #define	D_POWER		0x00000004
154 #define	D_MAP		0x00000008
155 #define	D_CTLOPS	0x00000010
156 #define	D_G_ISPEC	0x00000020
157 #define	D_A_ISPEC	0x00000040
158 #define	D_R_ISPEC	0x00000080
159 #define	D_INIT_CLD	0x00400000
160 #define	D_RM_CLD	0x00800000
161 #define	D_GET_REG	0x01000000
162 #define	D_XLATE_REG	0x02000000
163 #define	D_INTRDIST	0x04000000
164 
165 #define	D_CONT		0x80000000
166 
167 #define	DBG(flag, psp, fmt) \
168 	upa64s_debug(flag, psp, fmt, 0, 0, 0, 0, 0);
169 #define	DBG1(flag, psp, fmt, a1) \
170 	upa64s_debug(flag, psp, fmt, (uintptr_t)(a1), 0, 0, 0, 0);
171 #define	DBG2(flag, psp, fmt, a1, a2) \
172 	upa64s_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), 0, 0, 0);
173 #define	DBG3(flag, psp, fmt, a1, a2, a3) \
174 	upa64s_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \
175 		(uintptr_t)(a3), 0, 0);
176 #define	DBG4(flag, psp, fmt, a1, a2, a3, a4) \
177 	upa64s_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \
178 		(uintptr_t)(a3), (uintptr_t)(a4), 0);
179 #define	DBG5(flag, psp, fmt, a1, a2, a3, a4, a5) \
180 	upa64s_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \
181 		(uintptr_t)(a3), (uintptr_t)(a4), (uintptr_t)(a5));
182 
183 static void upa64s_debug(uint_t, dev_info_t *, char *, uintptr_t, uintptr_t, \
184 	uintptr_t, uintptr_t, uintptr_t);
185 #else
186 #define	DBG(flag, psp, fmt)
187 #define	DBG1(flag, psp, fmt, a1)
188 #define	DBG2(flag, psp, fmt, a1, a2)
189 #define	DBG3(flag, psp, fmt, a1, a2, a3)
190 #define	DBG4(flag, psp, fmt, a1, a2, a3, a4)
191 #define	DBG5(flag, psp, fmt, a1, a2, a3, a4, a5)
192 #define	dump_dma_handle(flag, psp, h)
193 #endif
194 
195 #ifdef	__cplusplus
196 }
197 #endif
198 
199 #endif	/* _SYS_UPA64S_VAR_H */
200