1 /*
2 * Copyright 2014-2017 Cavium, Inc.
3 * The contents of this file are subject to the terms of the Common Development
4 * and Distribution License, v.1, (the "License").
5 *
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the License at available
9 * at http://opensource.org/licenses/CDDL-1.0
10 *
11 * See the License for the specific language governing permissions and
12 * limitations under the License.
13 */
14
15 #include "lm5706.h"
16 #include "rxpfw.h"
17 #include "txpfw.h"
18 #include "tpatfw.h"
19 #include "comfw.h"
20 #include "cpfw.h"
21 #include "rv2p_p1.h"
22 #include "rv2p_p2.h"
23 #include "xi_rv2p_p1.h"
24 #include "xi_rv2p_p2.h"
25 #include "xi90_rv2p_p1.h"
26 #include "xi90_rv2p_p2.h"
27 #include "xinanfw.h"
28
29
30
31 /*******************************************************************************
32 * CPU register info.
33 ******************************************************************************/
34
35 typedef struct _cpu_reg_t
36 {
37 u32_t mode;
38 u32_t mode_value_halt;
39 u32_t mode_value_sstep;
40
41 u32_t state;
42 u32_t state_value_clear;
43
44 u32_t gpr0;
45 u32_t evmask;
46 u32_t pc;
47 u32_t inst;
48 u32_t bp;
49
50 u32_t spad_base;
51
52 u32_t mips_view_base;
53 } cpu_reg_t;
54
55
56
57 /*******************************************************************************
58 * Firmware info.
59 ******************************************************************************/
60
61 typedef struct _fw_info_t
62 {
63 u32_t ver_major;
64 u32_t ver_minor;
65 u32_t ver_fix;
66
67 u32_t start_addr;
68
69 /* Text section. */
70 u32_t text_addr;
71 u32_t text_len;
72 u32_t text_index;
73 u32_t *text;
74
75 /* Data section. */
76 u32_t data_addr;
77 u32_t data_len;
78 u32_t data_index;
79 u32_t *data;
80
81 /* SBSS section. */
82 u32_t sbss_addr;
83 u32_t sbss_len;
84 u32_t sbss_index;
85 u32_t *sbss;
86
87 /* BSS section. */
88 u32_t bss_addr;
89 u32_t bss_len;
90 u32_t bss_index;
91 u32_t *bss;
92
93 /* Read-only section. */
94 u32_t rodata_addr;
95 u32_t rodata_len;
96 u32_t rodata_index;
97 u32_t *rodata;
98 } fw_info_t;
99
100
101
102 #define RV2P_PROC1 0
103 #define RV2P_PROC2 1
104 /*******************************************************************************
105 * Description:
106 *
107 * Return:
108 ******************************************************************************/
109 STATIC void
load_rv2p_fw(lm_device_t * pdev,u32_t * rv2p_code,u32_t rv2p_code_len,u32_t rv2p_proc)110 load_rv2p_fw(
111 lm_device_t *pdev,
112 u32_t *rv2p_code,
113 u32_t rv2p_code_len,
114 u32_t rv2p_proc)
115 {
116 u32_t idx;
117 u32_t val;
118
119 DbgBreakIf(rv2p_proc != RV2P_PROC1 && rv2p_proc != RV2P_PROC2);
120
121 for(idx = 0; idx < rv2p_code_len; idx += 8)
122 {
123 REG_WR(pdev, rv2p.rv2p_instr_high, *rv2p_code);
124 rv2p_code++;
125 REG_WR(pdev, rv2p.rv2p_instr_low, *rv2p_code);
126 rv2p_code++;
127
128 if(rv2p_proc == RV2P_PROC1)
129 {
130 val = (idx/8) | RV2P_PROC1_ADDR_CMD_RDWR;
131 REG_WR(pdev, rv2p.rv2p_proc1_addr_cmd, val);
132 }
133 else
134 {
135 val = (idx/8) | RV2P_PROC2_ADDR_CMD_RDWR;
136 REG_WR(pdev, rv2p.rv2p_proc2_addr_cmd, val);
137 }
138 }
139
140 /* Reset the processor, un-stall is done later. */
141 if(rv2p_proc == RV2P_PROC1)
142 {
143 REG_WR(pdev, rv2p.rv2p_command, RV2P_COMMAND_PROC1_RESET);
144 }
145 else
146 {
147 REG_WR(pdev, rv2p.rv2p_command, RV2P_COMMAND_PROC2_RESET);
148 }
149 } /* load_rv2p_fw */
150
151
152
153 /*******************************************************************************
154 * Description:
155 *
156 * Return:
157 ******************************************************************************/
158 STATIC void
load_cpu_fw(lm_device_t * pdev,cpu_reg_t * cpu_reg,fw_info_t * fw)159 load_cpu_fw(
160 lm_device_t *pdev,
161 cpu_reg_t *cpu_reg,
162 fw_info_t *fw)
163 {
164 u32_t val;
165
166 /* Halt the CPU. */
167 REG_RD_IND(pdev, cpu_reg->mode, &val);
168 val |= cpu_reg->mode_value_halt;
169 REG_WR_IND(pdev, cpu_reg->mode, val);
170 REG_WR_IND(pdev, cpu_reg->state, cpu_reg->state_value_clear);
171
172 /* Load the Text area. */
173 if(fw->text)
174 {
175 lm_reg_wr_blk(
176 pdev,
177 cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base),
178 fw->text,
179 fw->text_len/4);
180 }
181
182 /* Load the Data area. */
183 if(fw->data)
184 {
185 lm_reg_wr_blk(
186 pdev,
187 cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base),
188 fw->data,
189 fw->data_len/4);
190 }
191
192 /* Load the SBSS area. */
193 if(fw->sbss)
194 {
195 lm_reg_wr_blk(
196 pdev,
197 cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base),
198 fw->sbss,
199 fw->sbss_len/4);
200 }
201
202 /* Load the BSS area. */
203 if(fw->bss)
204 {
205 lm_reg_wr_blk(
206 pdev,
207 cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base),
208 fw->bss,
209 fw->bss_len/4);
210 }
211
212 /* Load the Read-Only area. */
213 if(fw->rodata)
214 {
215 lm_reg_wr_blk(
216 pdev,
217 cpu_reg->spad_base + (fw->rodata_addr - cpu_reg->mips_view_base),
218 fw->rodata,
219 fw->rodata_len/4);
220 }
221
222 /* Clear the pre-fetch instruction. */
223 REG_WR_IND(pdev, cpu_reg->inst, 0);
224 REG_WR_IND(pdev, cpu_reg->pc, fw->start_addr);
225
226 /* Start the CPU. */
227 REG_RD_IND(pdev, cpu_reg->mode, &val);
228 val &= ~cpu_reg->mode_value_halt;
229 REG_WR_IND(pdev, cpu_reg->state, cpu_reg->state_value_clear);
230 REG_WR_IND(pdev, cpu_reg->mode, val);
231 } /* load_cpu_fw */
232
233
234
235 /*******************************************************************************
236 * Description:
237 *
238 * Return:
239 ******************************************************************************/
240 STATIC void
init_5706_cpus(lm_device_t * pdev,u32_t cpu_mask)241 init_5706_cpus(
242 lm_device_t *pdev,
243 u32_t cpu_mask)
244 {
245 cpu_reg_t cpu_reg;
246 fw_info_t fw;
247
248 DbgBreakIf(
249 CHIP_NUM(pdev) != CHIP_NUM_5706 &&
250 CHIP_NUM(pdev) != CHIP_NUM_5708);
251
252 if(cpu_mask & CPU_RXP)
253 {
254 cpu_reg.mode = OFFSETOF(reg_space_t, rxp.rxp_cpu_mode);
255 cpu_reg.mode_value_halt = RXP_CPU_MODE_SOFT_HALT;
256 cpu_reg.mode_value_sstep = RXP_CPU_MODE_STEP_ENA;
257 cpu_reg.state = OFFSETOF(reg_space_t, rxp.rxp_cpu_state);
258 cpu_reg.state_value_clear = 0xffffff;
259 cpu_reg.gpr0 = OFFSETOF(reg_space_t, rxp.rxp_cpu_reg_file[0]);
260 cpu_reg.evmask = OFFSETOF(reg_space_t, rxp.rxp_cpu_event_mask);
261 cpu_reg.pc = OFFSETOF(reg_space_t, rxp.rxp_cpu_program_counter);
262 cpu_reg.inst = OFFSETOF(reg_space_t, rxp.rxp_cpu_instruction);
263 cpu_reg.bp = OFFSETOF(reg_space_t, rxp.rxp_cpu_hw_breakpoint);
264 cpu_reg.spad_base = OFFSETOF(reg_space_t, rxp.rxp_scratch[0]);
265 cpu_reg.mips_view_base = 0x8000000;
266
267 fw.ver_major = RXP_b06FwReleaseMajor;
268 fw.ver_minor = RXP_b06FwReleaseMinor;
269 fw.ver_fix = RXP_b06FwReleaseFix;
270 fw.start_addr = RXP_b06FwStartAddr;
271
272 fw.text_addr = RXP_b06FwTextAddr;
273 fw.text_len = RXP_b06FwTextLen;
274 fw.text_index = 0;
275 fw.text = RXP_b06FwText;
276
277 fw.data_addr = RXP_b06FwDataAddr;
278 fw.data_len = RXP_b06FwDataLen;
279 fw.data_index = 0;
280 fw.data = RXP_b06FwData;
281
282 fw.sbss_addr = RXP_b06FwSbssAddr;
283 fw.sbss_len = RXP_b06FwSbssLen;
284 fw.sbss_index = 0;
285 fw.sbss = RXP_b06FwSbss;
286
287 fw.bss_addr = RXP_b06FwBssAddr;
288 fw.bss_len = RXP_b06FwBssLen;
289 fw.bss_index = 0;
290 fw.bss = RXP_b06FwBss;
291
292 fw.rodata_addr = RXP_b06FwRodataAddr;
293 fw.rodata_len = RXP_b06FwRodataLen;
294 fw.rodata_index = 0;
295 fw.rodata = RXP_b06FwRodata;
296
297 load_cpu_fw(pdev, &cpu_reg, &fw);
298 }
299
300 if(cpu_mask & CPU_TXP)
301 {
302 cpu_reg.mode = OFFSETOF(reg_space_t, txp.txp_cpu_mode);
303 cpu_reg.mode_value_halt = TXP_CPU_MODE_SOFT_HALT;
304 cpu_reg.mode_value_sstep = TXP_CPU_MODE_STEP_ENA;
305 cpu_reg.state = OFFSETOF(reg_space_t, txp.txp_cpu_state);
306 cpu_reg.state_value_clear = 0xffffff;
307 cpu_reg.gpr0 = OFFSETOF(reg_space_t, txp.txp_cpu_reg_file[0]);
308 cpu_reg.evmask = OFFSETOF(reg_space_t, txp.txp_cpu_event_mask);
309 cpu_reg.pc = OFFSETOF(reg_space_t, txp.txp_cpu_program_counter);
310 cpu_reg.inst = OFFSETOF(reg_space_t, txp.txp_cpu_instruction);
311 cpu_reg.bp = OFFSETOF(reg_space_t, txp.txp_cpu_hw_breakpoint);
312 cpu_reg.spad_base = OFFSETOF(reg_space_t, txp.txp_scratch[0]);
313 cpu_reg.mips_view_base = 0x8000000;
314
315 fw.ver_major = TXP_b06FwReleaseMajor;
316 fw.ver_minor = TXP_b06FwReleaseMinor;
317 fw.ver_fix = TXP_b06FwReleaseFix;
318 fw.start_addr = TXP_b06FwStartAddr;
319
320 fw.text_addr = TXP_b06FwTextAddr;
321 fw.text_len = TXP_b06FwTextLen;
322 fw.text_index = 0;
323 fw.text = TXP_b06FwText;
324
325 fw.data_addr = TXP_b06FwDataAddr;
326 fw.data_len = TXP_b06FwDataLen;
327 fw.data_index = 0;
328 fw.data = TXP_b06FwData;
329
330 fw.sbss_addr = TXP_b06FwSbssAddr;
331 fw.sbss_len = TXP_b06FwSbssLen;
332 fw.sbss_index = 0;
333 fw.sbss = TXP_b06FwSbss;
334
335 fw.bss_addr = TXP_b06FwBssAddr;
336 fw.bss_len = TXP_b06FwBssLen;
337 fw.bss_index = 0;
338 fw.bss = TXP_b06FwBss;
339
340 fw.rodata_addr = TXP_b06FwRodataAddr;
341 fw.rodata_len = TXP_b06FwRodataLen;
342 fw.rodata_index = 0;
343 fw.rodata = TXP_b06FwRodata;
344
345 load_cpu_fw(pdev, &cpu_reg, &fw);
346 }
347
348 if(cpu_mask & CPU_TPAT)
349 {
350 cpu_reg.mode = OFFSETOF(reg_space_t, tpat.tpat_cpu_mode);
351 cpu_reg.mode_value_halt = TPAT_CPU_MODE_SOFT_HALT;
352 cpu_reg.mode_value_sstep = TPAT_CPU_MODE_STEP_ENA;
353 cpu_reg.state = OFFSETOF(reg_space_t, tpat.tpat_cpu_state);
354 cpu_reg.state_value_clear = 0xffffff;
355 cpu_reg.gpr0 = OFFSETOF(reg_space_t, tpat.tpat_cpu_reg_file[0]);
356 cpu_reg.evmask = OFFSETOF(reg_space_t, tpat.tpat_cpu_event_mask);
357 cpu_reg.pc = OFFSETOF(reg_space_t, tpat.tpat_cpu_program_counter);
358 cpu_reg.inst = OFFSETOF(reg_space_t, tpat.tpat_cpu_instruction);
359 cpu_reg.bp = OFFSETOF(reg_space_t, tpat.tpat_cpu_hw_breakpoint);
360 cpu_reg.spad_base = OFFSETOF(reg_space_t, tpat.tpat_scratch[0]);
361 cpu_reg.mips_view_base = 0x8000000;
362
363 fw.ver_major = TPAT_b06FwReleaseMajor;
364 fw.ver_minor = TPAT_b06FwReleaseMinor;
365 fw.ver_fix = TPAT_b06FwReleaseFix;
366 fw.start_addr = TPAT_b06FwStartAddr;
367
368 fw.text_addr = TPAT_b06FwTextAddr;
369 fw.text_len = TPAT_b06FwTextLen;
370 fw.text_index = 0;
371 fw.text = TPAT_b06FwText;
372
373 fw.data_addr = TPAT_b06FwDataAddr;
374 fw.data_len = TPAT_b06FwDataLen;
375 fw.data_index = 0;
376 fw.data = TPAT_b06FwData;
377
378 fw.sbss_addr = TPAT_b06FwSbssAddr;
379 fw.sbss_len = TPAT_b06FwSbssLen;
380 fw.sbss_index = 0;
381 fw.sbss = TPAT_b06FwSbss;
382
383 fw.bss_addr = TPAT_b06FwBssAddr;
384 fw.bss_len = TPAT_b06FwBssLen;
385 fw.bss_index = 0;
386 fw.bss = TPAT_b06FwBss;
387
388 fw.rodata_addr = TPAT_b06FwRodataAddr;
389 fw.rodata_len = TPAT_b06FwRodataLen;
390 fw.rodata_index = 0;
391 fw.rodata = TPAT_b06FwRodata;
392
393 load_cpu_fw(pdev, &cpu_reg, &fw);
394 }
395
396 if(cpu_mask & CPU_COM)
397 {
398 cpu_reg.mode = OFFSETOF(reg_space_t, com.com_cpu_mode);
399 cpu_reg.mode_value_halt = COM_CPU_MODE_SOFT_HALT;
400 cpu_reg.mode_value_sstep = COM_CPU_MODE_STEP_ENA;
401 cpu_reg.state = OFFSETOF(reg_space_t, com.com_cpu_state);
402 cpu_reg.state_value_clear = 0xffffff;
403 cpu_reg.gpr0 = OFFSETOF(reg_space_t, com.com_cpu_reg_file[0]);
404 cpu_reg.evmask = OFFSETOF(reg_space_t, com.com_cpu_event_mask);
405 cpu_reg.pc = OFFSETOF(reg_space_t, com.com_cpu_program_counter);
406 cpu_reg.inst = OFFSETOF(reg_space_t, com.com_cpu_instruction);
407 cpu_reg.bp = OFFSETOF(reg_space_t, com.com_cpu_hw_breakpoint);
408 cpu_reg.spad_base = OFFSETOF(reg_space_t, com.com_scratch[0]);
409 cpu_reg.mips_view_base = 0x8000000;
410
411 fw.ver_major = COM_b06FwReleaseMajor;
412 fw.ver_minor = COM_b06FwReleaseMinor;
413 fw.ver_fix = COM_b06FwReleaseFix;
414 fw.start_addr = COM_b06FwStartAddr;
415
416 fw.text_addr = COM_b06FwTextAddr;
417 fw.text_len = COM_b06FwTextLen;
418 fw.text_index = 0;
419 fw.text = COM_b06FwText;
420
421 fw.data_addr = COM_b06FwDataAddr;
422 fw.data_len = COM_b06FwDataLen;
423 fw.data_index = 0;
424 fw.data = COM_b06FwData;
425
426 fw.sbss_addr = COM_b06FwSbssAddr;
427 fw.sbss_len = COM_b06FwSbssLen;
428 fw.sbss_index = 0;
429 fw.sbss = COM_b06FwSbss;
430
431 fw.bss_addr = COM_b06FwBssAddr;
432 fw.bss_len = COM_b06FwBssLen;
433 fw.bss_index = 0;
434 fw.bss = COM_b06FwBss;
435
436 fw.rodata_addr = COM_b06FwRodataAddr;
437 fw.rodata_len = COM_b06FwRodataLen;
438 fw.rodata_index = 0;
439 fw.rodata = COM_b06FwRodata;
440
441 load_cpu_fw(pdev, &cpu_reg, &fw);
442 }
443
444 if(cpu_mask & CPU_CP)
445 {
446 cpu_reg.mode = OFFSETOF(reg_space_t, cp.cp_cpu_mode);
447 cpu_reg.mode_value_halt = CP_CPU_MODE_SOFT_HALT;
448 cpu_reg.mode_value_sstep = CP_CPU_MODE_STEP_ENA;
449 cpu_reg.state = OFFSETOF(reg_space_t, cp.cp_cpu_state);
450 cpu_reg.state_value_clear = 0xffffff;
451 cpu_reg.gpr0 = OFFSETOF(reg_space_t, cp.cp_cpu_reg_file[0]);
452 cpu_reg.evmask = OFFSETOF(reg_space_t, cp.cp_cpu_event_mask);
453 cpu_reg.pc = OFFSETOF(reg_space_t, cp.cp_cpu_program_counter);
454 cpu_reg.inst = OFFSETOF(reg_space_t, cp.cp_cpu_instruction);
455 cpu_reg.bp = OFFSETOF(reg_space_t, cp.cp_cpu_hw_breakpoint);
456 cpu_reg.spad_base = OFFSETOF(reg_space_t, cp.cp_scratch[0]);
457 cpu_reg.mips_view_base = 0x8000000;
458
459 fw.ver_major = CP_b06FwReleaseMajor;
460 fw.ver_minor = CP_b06FwReleaseMinor;
461 fw.ver_fix = CP_b06FwReleaseFix;
462 fw.start_addr = CP_b06FwStartAddr;
463
464 fw.text_addr = CP_b06FwTextAddr;
465 fw.text_len = CP_b06FwTextLen;
466 fw.text_index = 0;
467 fw.text = CP_b06FwText;
468
469 fw.data_addr = CP_b06FwDataAddr;
470 fw.data_len = CP_b06FwDataLen;
471 fw.data_index = 0;
472 fw.data = CP_b06FwData;
473
474 fw.sbss_addr = CP_b06FwSbssAddr;
475 fw.sbss_len = CP_b06FwSbssLen;
476 fw.sbss_index = 0;
477 fw.sbss = CP_b06FwSbss;
478
479 fw.bss_addr = CP_b06FwBssAddr;
480 fw.bss_len = CP_b06FwBssLen;
481 fw.bss_index = 0;
482 fw.bss = CP_b06FwBss;
483
484 fw.rodata_addr = CP_b06FwRodataAddr;
485 fw.rodata_len = CP_b06FwRodataLen;
486 fw.rodata_index = 0;
487 fw.rodata = CP_b06FwRodata;
488
489 load_cpu_fw(pdev, &cpu_reg, &fw);
490 }
491 } /* init_5706_cpus */
492
493
494
495 /*******************************************************************************
496 * Description:
497 *
498 * Return:
499 ******************************************************************************/
500 STATIC void
init_5709_cpus(lm_device_t * pdev,u32_t cpu_mask)501 init_5709_cpus(
502 lm_device_t *pdev,
503 u32_t cpu_mask)
504 {
505 cpu_reg_t cpu_reg;
506 fw_info_t fw;
507
508 DbgBreakIf(CHIP_NUM(pdev) != CHIP_NUM_5709);
509
510 if(cpu_mask & CPU_RXP)
511 {
512 cpu_reg.mode = OFFSETOF(reg_space_t, rxp.rxp_cpu_mode);
513 cpu_reg.mode_value_halt = RXP_CPU_MODE_SOFT_HALT;
514 cpu_reg.mode_value_sstep = RXP_CPU_MODE_STEP_ENA;
515 cpu_reg.state = OFFSETOF(reg_space_t, rxp.rxp_cpu_state);
516 cpu_reg.state_value_clear = 0xffffff;
517 cpu_reg.gpr0 = OFFSETOF(reg_space_t, rxp.rxp_cpu_reg_file[0]);
518 cpu_reg.evmask = OFFSETOF(reg_space_t, rxp.rxp_cpu_event_mask);
519 cpu_reg.pc = OFFSETOF(reg_space_t, rxp.rxp_cpu_program_counter);
520 cpu_reg.inst = OFFSETOF(reg_space_t, rxp.rxp_cpu_instruction);
521 cpu_reg.bp = OFFSETOF(reg_space_t, rxp.rxp_cpu_hw_breakpoint);
522 cpu_reg.spad_base = OFFSETOF(reg_space_t, rxp.rxp_scratch[0]);
523 cpu_reg.mips_view_base = 0x8000000;
524
525 fw.ver_major = RXP_b09FwReleaseMajor;
526 fw.ver_minor = RXP_b09FwReleaseMinor;
527 fw.ver_fix = RXP_b09FwReleaseFix;
528 fw.start_addr = RXP_b09FwStartAddr;
529
530 fw.text_addr = RXP_b09FwTextAddr;
531 fw.text_len = RXP_b09FwTextLen;
532 fw.text_index = 0;
533 fw.text = RXP_b09FwText;
534
535 fw.data_addr = RXP_b09FwDataAddr;
536 fw.data_len = RXP_b09FwDataLen;
537 fw.data_index = 0;
538 fw.data = RXP_b09FwData;
539
540 fw.sbss_addr = RXP_b09FwSbssAddr;
541 fw.sbss_len = RXP_b09FwSbssLen;
542 fw.sbss_index = 0;
543 fw.sbss = RXP_b09FwSbss;
544
545 fw.bss_addr = RXP_b09FwBssAddr;
546 fw.bss_len = RXP_b09FwBssLen;
547 fw.bss_index = 0;
548 fw.bss = RXP_b09FwBss;
549
550 fw.rodata_addr = RXP_b09FwRodataAddr;
551 fw.rodata_len = RXP_b09FwRodataLen;
552 fw.rodata_index = 0;
553 fw.rodata = RXP_b09FwRodata;
554
555 load_cpu_fw(pdev, &cpu_reg, &fw);
556 }
557
558 if(cpu_mask & CPU_TXP)
559 {
560 cpu_reg.mode = OFFSETOF(reg_space_t, txp.txp_cpu_mode);
561 cpu_reg.mode_value_halt = TXP_CPU_MODE_SOFT_HALT;
562 cpu_reg.mode_value_sstep = TXP_CPU_MODE_STEP_ENA;
563 cpu_reg.state = OFFSETOF(reg_space_t, txp.txp_cpu_state);
564 cpu_reg.state_value_clear = 0xffffff;
565 cpu_reg.gpr0 = OFFSETOF(reg_space_t, txp.txp_cpu_reg_file[0]);
566 cpu_reg.evmask = OFFSETOF(reg_space_t, txp.txp_cpu_event_mask);
567 cpu_reg.pc = OFFSETOF(reg_space_t, txp.txp_cpu_program_counter);
568 cpu_reg.inst = OFFSETOF(reg_space_t, txp.txp_cpu_instruction);
569 cpu_reg.bp = OFFSETOF(reg_space_t, txp.txp_cpu_hw_breakpoint);
570 cpu_reg.spad_base = OFFSETOF(reg_space_t, txp.txp_scratch[0]);
571 cpu_reg.mips_view_base = 0x8000000;
572
573 fw.ver_major = TXP_b09FwReleaseMajor;
574 fw.ver_minor = TXP_b09FwReleaseMinor;
575 fw.ver_fix = TXP_b09FwReleaseFix;
576 fw.start_addr = TXP_b09FwStartAddr;
577
578 fw.text_addr = TXP_b09FwTextAddr;
579 fw.text_len = TXP_b09FwTextLen;
580 fw.text_index = 0;
581 fw.text = TXP_b09FwText;
582
583 fw.data_addr = TXP_b09FwDataAddr;
584 fw.data_len = TXP_b09FwDataLen;
585 fw.data_index = 0;
586 fw.data = TXP_b09FwData;
587
588 fw.sbss_addr = TXP_b09FwSbssAddr;
589 fw.sbss_len = TXP_b09FwSbssLen;
590 fw.sbss_index = 0;
591 fw.sbss = TXP_b09FwSbss;
592
593 fw.bss_addr = TXP_b09FwBssAddr;
594 fw.bss_len = TXP_b09FwBssLen;
595 fw.bss_index = 0;
596 fw.bss = TXP_b09FwBss;
597
598 fw.rodata_addr = TXP_b09FwRodataAddr;
599 fw.rodata_len = TXP_b09FwRodataLen;
600 fw.rodata_index = 0;
601 fw.rodata = TXP_b09FwRodata;
602
603 load_cpu_fw(pdev, &cpu_reg, &fw);
604 }
605
606 if(cpu_mask & CPU_TPAT)
607 {
608 cpu_reg.mode = OFFSETOF(reg_space_t, tpat.tpat_cpu_mode);
609 cpu_reg.mode_value_halt = TPAT_CPU_MODE_SOFT_HALT;
610 cpu_reg.mode_value_sstep = TPAT_CPU_MODE_STEP_ENA;
611 cpu_reg.state = OFFSETOF(reg_space_t, tpat.tpat_cpu_state);
612 cpu_reg.state_value_clear = 0xffffff;
613 cpu_reg.gpr0 = OFFSETOF(reg_space_t, tpat.tpat_cpu_reg_file[0]);
614 cpu_reg.evmask = OFFSETOF(reg_space_t, tpat.tpat_cpu_event_mask);
615 cpu_reg.pc = OFFSETOF(reg_space_t, tpat.tpat_cpu_program_counter);
616 cpu_reg.inst = OFFSETOF(reg_space_t, tpat.tpat_cpu_instruction);
617 cpu_reg.bp = OFFSETOF(reg_space_t, tpat.tpat_cpu_hw_breakpoint);
618 cpu_reg.spad_base = OFFSETOF(reg_space_t, tpat.tpat_scratch[0]);
619 cpu_reg.mips_view_base = 0x8000000;
620
621 fw.ver_major = TPAT_b09FwReleaseMajor;
622 fw.ver_minor = TPAT_b09FwReleaseMinor;
623 fw.ver_fix = TPAT_b09FwReleaseFix;
624 fw.start_addr = TPAT_b09FwStartAddr;
625
626 fw.text_addr = TPAT_b09FwTextAddr;
627 fw.text_len = TPAT_b09FwTextLen;
628 fw.text_index = 0;
629 fw.text = TPAT_b09FwText;
630
631 fw.data_addr = TPAT_b09FwDataAddr;
632 fw.data_len = TPAT_b09FwDataLen;
633 fw.data_index = 0;
634 fw.data = TPAT_b09FwData;
635
636 fw.sbss_addr = TPAT_b09FwSbssAddr;
637 fw.sbss_len = TPAT_b09FwSbssLen;
638 fw.sbss_index = 0;
639 fw.sbss = TPAT_b09FwSbss;
640
641 fw.bss_addr = TPAT_b09FwBssAddr;
642 fw.bss_len = TPAT_b09FwBssLen;
643 fw.bss_index = 0;
644 fw.bss = TPAT_b09FwBss;
645
646 fw.rodata_addr = TPAT_b09FwRodataAddr;
647 fw.rodata_len = TPAT_b09FwRodataLen;
648 fw.rodata_index = 0;
649 fw.rodata = TPAT_b09FwRodata;
650
651 load_cpu_fw(pdev, &cpu_reg, &fw);
652 }
653
654 if(cpu_mask & CPU_COM)
655 {
656 cpu_reg.mode = OFFSETOF(reg_space_t, com.com_cpu_mode);
657 cpu_reg.mode_value_halt = COM_CPU_MODE_SOFT_HALT;
658 cpu_reg.mode_value_sstep = COM_CPU_MODE_STEP_ENA;
659 cpu_reg.state = OFFSETOF(reg_space_t, com.com_cpu_state);
660 cpu_reg.state_value_clear = 0xffffff;
661 cpu_reg.gpr0 = OFFSETOF(reg_space_t, com.com_cpu_reg_file[0]);
662 cpu_reg.evmask = OFFSETOF(reg_space_t, com.com_cpu_event_mask);
663 cpu_reg.pc = OFFSETOF(reg_space_t, com.com_cpu_program_counter);
664 cpu_reg.inst = OFFSETOF(reg_space_t, com.com_cpu_instruction);
665 cpu_reg.bp = OFFSETOF(reg_space_t, com.com_cpu_hw_breakpoint);
666 cpu_reg.spad_base = OFFSETOF(reg_space_t, com.com_scratch[0]);
667 cpu_reg.mips_view_base = 0x8000000;
668
669 fw.ver_major = COM_b09FwReleaseMajor;
670 fw.ver_minor = COM_b09FwReleaseMinor;
671 fw.ver_fix = COM_b09FwReleaseFix;
672 fw.start_addr = COM_b09FwStartAddr;
673
674 fw.text_addr = COM_b09FwTextAddr;
675 fw.text_len = COM_b09FwTextLen;
676 fw.text_index = 0;
677 fw.text = COM_b09FwText;
678
679 fw.data_addr = COM_b09FwDataAddr;
680 fw.data_len = COM_b09FwDataLen;
681 fw.data_index = 0;
682 fw.data = COM_b09FwData;
683
684 fw.sbss_addr = COM_b09FwSbssAddr;
685 fw.sbss_len = COM_b09FwSbssLen;
686 fw.sbss_index = 0;
687 fw.sbss = COM_b09FwSbss;
688
689 fw.bss_addr = COM_b09FwBssAddr;
690 fw.bss_len = COM_b09FwBssLen;
691 fw.bss_index = 0;
692 fw.bss = COM_b09FwBss;
693
694 fw.rodata_addr = COM_b09FwRodataAddr;
695 fw.rodata_len = COM_b09FwRodataLen;
696 fw.rodata_index = 0;
697 fw.rodata = COM_b09FwRodata;
698
699 load_cpu_fw(pdev, &cpu_reg, &fw);
700 }
701
702 if(cpu_mask & CPU_CP)
703 {
704 cpu_reg.mode = OFFSETOF(reg_space_t, cp.cp_cpu_mode);
705 cpu_reg.mode_value_halt = CP_CPU_MODE_SOFT_HALT;
706 cpu_reg.mode_value_sstep = CP_CPU_MODE_STEP_ENA;
707 cpu_reg.state = OFFSETOF(reg_space_t, cp.cp_cpu_state);
708 cpu_reg.state_value_clear = 0xffffff;
709 cpu_reg.gpr0 = OFFSETOF(reg_space_t, cp.cp_cpu_reg_file[0]);
710 cpu_reg.evmask = OFFSETOF(reg_space_t, cp.cp_cpu_event_mask);
711 cpu_reg.pc = OFFSETOF(reg_space_t, cp.cp_cpu_program_counter);
712 cpu_reg.inst = OFFSETOF(reg_space_t, cp.cp_cpu_instruction);
713 cpu_reg.bp = OFFSETOF(reg_space_t, cp.cp_cpu_hw_breakpoint);
714 cpu_reg.spad_base = OFFSETOF(reg_space_t, cp.cp_scratch[0]);
715 cpu_reg.mips_view_base = 0x8000000;
716
717 fw.ver_major = CP_b09FwReleaseMajor;
718 fw.ver_minor = CP_b09FwReleaseMinor;
719 fw.ver_fix = CP_b09FwReleaseFix;
720 fw.start_addr = CP_b09FwStartAddr;
721
722 fw.text_addr = CP_b09FwTextAddr;
723 fw.text_len = CP_b09FwTextLen;
724 fw.text_index = 0;
725 fw.text = CP_b09FwText;
726
727 fw.data_addr = CP_b09FwDataAddr;
728 fw.data_len = CP_b09FwDataLen;
729 fw.data_index = 0;
730 fw.data = CP_b09FwData;
731
732 fw.sbss_addr = CP_b09FwSbssAddr;
733 fw.sbss_len = CP_b09FwSbssLen;
734 fw.sbss_index = 0;
735 fw.sbss = CP_b09FwSbss;
736
737 fw.bss_addr = CP_b09FwBssAddr;
738 fw.bss_len = CP_b09FwBssLen;
739 fw.bss_index = 0;
740 fw.bss = CP_b09FwBss;
741
742 fw.rodata_addr = CP_b09FwRodataAddr;
743 fw.rodata_len = CP_b09FwRodataLen;
744 fw.rodata_index = 0;
745 fw.rodata = CP_b09FwRodata;
746
747 load_cpu_fw(pdev, &cpu_reg, &fw);
748 }
749 } /* init_5709_cpus */
750
751
752
753 /*******************************************************************************
754 * Description:
755 *
756 * Return:
757 ******************************************************************************/
758 void
lm_init_cpus(lm_device_t * pdev,u32_t cpu_mask)759 lm_init_cpus(
760 lm_device_t *pdev,
761 u32_t cpu_mask)
762 {
763 DbgBreakIf(
764 CHIP_NUM(pdev) != CHIP_NUM_5706 &&
765 CHIP_NUM(pdev) != CHIP_NUM_5708 &&
766 CHIP_NUM(pdev) != CHIP_NUM_5709);
767
768 if(CHIP_NUM(pdev) == CHIP_NUM_5706 || CHIP_NUM(pdev) == CHIP_NUM_5708)
769 {
770 if(cpu_mask & CPU_RV2P_1)
771 {
772 // Calling this macro prior to loading will change value of POST_WAIT_TIMEOUT
773 // This parameter dictates how long to wait before dropping L2 packet
774 // due to insufficient posted buffers
775 // 0 mean no waiting before dropping, 0xFFFF means maximum wait
776 if (pdev->params.fw_flow_control)
777 {
778 RV2P_PROC1_CHG_POST_WAIT_TIMEOUT(pdev->params.fw_flow_control_wait);
779 }
780 else
781 {
782 // No waiting if fw_flow_control is not enabled
783 RV2P_PROC1_CHG_POST_WAIT_TIMEOUT(0);
784 }
785 load_rv2p_fw(pdev, rv2p_proc1, sizeof(rv2p_proc1), RV2P_PROC1);
786 }
787
788 if(cpu_mask & CPU_RV2P_2)
789 {
790 load_rv2p_fw(pdev, rv2p_proc2, sizeof(rv2p_proc2), RV2P_PROC2);
791 }
792
793 init_5706_cpus(pdev, cpu_mask);
794 }
795 else if(CHIP_ID(pdev) == CHIP_ID_5709_A0 || CHIP_ID(pdev) == CHIP_ID_5709_A1)
796 {
797 if(cpu_mask & CPU_RV2P_1)
798 {
799 // Calling this macro prior to loading will change value of POST_WAIT_TIMEOUT
800 // This parameter dictates how long to wait before dropping L2 packet
801 // due to insufficient posted buffers
802 // 0 mean no waiting before dropping, 0xFFFF means maximum wait
803 if (pdev->params.fw_flow_control)
804 {
805 XI90_RV2P_PROC1_CHG_POST_WAIT_TIMEOUT(pdev->params.fw_flow_control_wait);
806 }
807 else
808 {
809 // No waiting if fw_flow_control is not enabled
810 XI90_RV2P_PROC1_CHG_POST_WAIT_TIMEOUT(0);
811 }
812 load_rv2p_fw(
813 pdev,
814 xi90_rv2p_proc1,
815 sizeof(xi90_rv2p_proc1),
816 RV2P_PROC1);
817 }
818
819 if(cpu_mask & CPU_RV2P_2)
820 {
821 load_rv2p_fw(
822 pdev,
823 xi90_rv2p_proc2,
824 sizeof(xi90_rv2p_proc2),
825 RV2P_PROC2);
826 }
827
828 init_5709_cpus(pdev, cpu_mask);
829 }
830 else
831 {
832 if(cpu_mask & CPU_RV2P_1)
833 {
834 // Calling this macro prior to loading will change value of POST_WAIT_TIMEOUT
835 // This parameter dictates how long to wait before dropping L2 packet
836 // due to insufficient posted buffers
837 // 0 mean no waiting before dropping, 0xFFFF means maximum wait
838 if (pdev->params.fw_flow_control)
839 {
840 XI_RV2P_PROC1_CHG_POST_WAIT_TIMEOUT(pdev->params.fw_flow_control_wait);
841 }
842 else
843 {
844 // No waiting if fw_flow_control is not enabled
845 XI_RV2P_PROC1_CHG_POST_WAIT_TIMEOUT(0);
846 }
847 load_rv2p_fw(pdev,xi_rv2p_proc1,sizeof(xi_rv2p_proc1),RV2P_PROC1);
848 }
849
850 if(cpu_mask & CPU_RV2P_2)
851 {
852 load_rv2p_fw(pdev,xi_rv2p_proc2,sizeof(xi_rv2p_proc2),RV2P_PROC2);
853 }
854
855 init_5709_cpus(pdev, cpu_mask);
856 }
857 } /* lm_init_cpus */
858
859