| /gfx-drm/usr/src/uts/intel/io/i915/ |
| H A D | i915_drv.c | 1186 #define NEEDS_FORCE_WAKE(dev_priv, reg) \ argument
1201 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg) in hsw_unclaimed_reg_clear()
1221 u8 i915_read8(struct drm_i915_private *dev_priv, u32 reg) in i915_read8()
1242 u16 i915_read16(struct drm_i915_private *dev_priv, u32 reg) in i915_read16()
1263 u32 i915_read32(struct drm_i915_private *dev_priv, u32 reg) in i915_read32()
1284 u64 i915_read64(struct drm_i915_private *dev_priv, u32 reg) in i915_read64()
1305 void i915_write8(struct drm_i915_private *dev_priv, u32 reg, in i915_write8()
1327 void i915_write16(struct drm_i915_private *dev_priv, u32 reg, in i915_write16()
1349 void i915_write32(struct drm_i915_private *dev_priv, u32 reg, in i915_write32()
1371 void i915_write64(struct drm_i915_private *dev_priv, u32 reg, in i915_write64()
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| H A D | intel_sideband.c | 104 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg) in vlv_dpio_read()
114 void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val) in vlv_dpio_write()
121 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, in intel_sbi_read()
150 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, in intel_sbi_write()
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| H A D | i915_suspend.c | 37 static u8 i915_read_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg) in i915_read_indexed()
45 static u8 i915_read_ar(struct drm_device *dev, u16 st01, u8 reg, u16 palette_enable) in i915_read_ar()
54 static void i915_write_ar(struct drm_device *dev, u16 st01, u8 reg, u8 val, u16 palette_enable) in i915_write_ar()
63 static void i915_write_indexed(struct drm_device *dev, u16 index_port, u16 data_port, u8 reg, u8 va… in i915_write_indexed()
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| H A D | intel_hdmi.c | 186 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); in ibx_write_infoframe() local
226 int reg = TVIDEO_DIP_CTL(intel_crtc->pipe); in cpt_write_infoframe() local
269 int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); in vlv_write_infoframe() local
391 u32 reg = VIDEO_DIP_CTL; in g4x_set_infoframes() local
456 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); in ibx_set_infoframes() local
516 u32 reg = TVIDEO_DIP_CTL(intel_crtc->pipe); in cpt_set_infoframes() local
551 u32 reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe); in vlv_set_infoframes() local
585 u32 reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder); in hsw_set_infoframes() local
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| H A D | i915_ums.c | 54 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B); in i915_save_palette() local
76 unsigned long reg = (pipe == PIPE_A ? _PALETTE_A : _PALETTE_B); in i915_restore_palette() local
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| H A D | intel_display.c | 894 int reg; in assert_pll() local
948 int reg; in assert_fdi_tx() local
974 int reg; in assert_fdi_rx() local
991 int reg; in assert_fdi_tx_pll_enabled() local
1011 int reg; in assert_fdi_rx_pll_enabled() local
1052 int reg; in assert_pipe() local
1079 int reg; in assert_plane() local
1174 int reg; in assert_pch_transcoder_disabled() local
1280 int reg; in assert_pch_ports_disabled() local
1319 int reg; in intel_enable_pll() local
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| H A D | i915_gem.c | 1407 struct drm_i915_fence_reg *reg; in i915_gem_object_move_to_active() local
1763 struct drm_i915_fence_reg *reg = &dev_priv->fence_regs[i]; in i915_gem_restore_fences() local
2160 static void i965_write_fence_reg(struct drm_device *dev, int reg, in i965_write_fence_reg()
2212 static void i915_write_fence_reg(struct drm_device *dev, int reg, in i915_write_fence_reg()
2256 static void i830_write_fence_reg(struct drm_device *dev, int reg, in i830_write_fence_reg()
2293 static void i915_gem_write_fence(struct drm_device *dev, int reg, in i915_gem_write_fence()
2336 int reg = fence_number(dev_priv, fence); in i915_gem_object_update_fence() local
2393 struct drm_i915_fence_reg *reg, *avail; in i915_find_fence_reg() local
2441 struct drm_i915_fence_reg *reg; in i915_gem_object_get_fence() local
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| H A D | i915_gem_debug.c | 56 uint32_t reg; member
65 add_instdone_bit(uint32_t reg, uint32_t bit, const char *name) in add_instdone_bit()
361 #define ring_read(ring, reg) I915_READ(ring->mmio + reg) argument
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| H A D | intel_ddi.c | 94 u32 reg; in intel_prepare_ddi_buffers() local
149 uint32_t reg = DDI_BUF_CTL(port); in intel_wait_ddi_buf_idle() local
643 uint32_t reg, val; in intel_ddi_pll_mode_set() local
853 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); in intel_ddi_disable_transcoder_func() local
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| H A D | intel_panel.c | 529 uint32_t reg, tmp; in intel_panel_disable_backlight() local
563 uint32_t reg, tmp; in intel_panel_enable_backlight() local
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| H A D | i915_irq.c | 320 u32 reg = PIPESTAT(pipe); in i915_enable_pipestat() local
335 u32 reg = PIPESTAT(pipe); in i915_disable_pipestat() local
409 int reg = PIPE_FRMCOUNT_GM45(pipe); in gm45_get_vblank_counter() local
942 int reg = PIPESTAT(pipe); in valleyview_irq_handler() local
3011 int reg = PIPESTAT(pipe); in i8xx_irq_handler() local
3184 int reg = PIPESTAT(pipe); in i915_irq_handler() local
3417 int reg = PIPESTAT(pipe); in i965_irq_handler() local
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| H A D | i915_drv.h | 2008 #define I915_READ(reg) i915_read32(dev_priv, (reg)) argument
2010 #define I915_READ_NOTRACE(reg) DRM_READ32(dev_priv->regs, (reg)) argument
2012 #define I915_READ16(reg) i915_read16(dev_priv, (reg)) argument
2013 #define I915_WRITE16(reg,val) i915_write16(dev_priv, (reg), (u16)(val)) argument
2014 #define I915_READ16_NOTRACE(reg) DRM_READ16(dev_priv->regs, (reg)) argument
2016 #define I915_READ8(reg) i915_read8(dev_priv, (reg)) argument
2017 #define I915_WRITE8(reg,val) i915_write8(dev_priv, (reg), (u8)(val)) argument
2019 #define I915_READ64(reg) i915_read64(dev_priv, (reg)) argument
2020 #define POSTING_READ(reg) (void)DRM_READ32(dev_priv->regs, (reg)) argument
2021 #define POSTING_READ16(reg) (void)DRM_READ16(dev_priv->regs, (reg)) argument
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| H A D | intel_ringbuffer.h | 230 int reg) in intel_read_status_page()
238 int reg, u32 value) in intel_write_status_page()
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| H A D | i915_gem_context.c | 114 u32 reg; in get_context_size() local
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| H A D | intel_sprite.c | 506 int reg = DSPCNTR(intel_crtc->plane); in intel_enable_primary() local
523 int reg = DSPCNTR(intel_crtc->plane); in intel_disable_primary() local
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| H A D | i915_dma.c | 71 intel_read_legacy_status_page(struct drm_i915_private *dev_priv, int reg) in intel_read_legacy_status_page()
80 #define READ_HWSP(dev_priv, reg) intel_read_legacy_status_page(dev_priv, reg) argument
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| H A D | intel_i2c.c | 43 int reg; member
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| H A D | intel_lvds.c | 53 u32 reg; member
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| H A D | dvo_ch7017.c | 386 #define DUMP(reg) \ in ch7017_dump_regs() argument
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| H A D | intel_pm.c | 1098 u32 reg; in pineview_update_wm() local
2738 int sprite_wm, reg; in sandybridge_update_sprite_wm() local
4144 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); in gen7_setup_fixed_func_scheduler() local
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| H A D | intel_sdvo.c | 2251 struct intel_sdvo *sdvo, u32 reg) in intel_sdvo_select_ddc_bus()
2268 struct intel_sdvo *sdvo, u32 reg) in intel_sdvo_select_i2c_bus()
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| H A D | intel_ringbuffer.c | 975 u32 reg = RING_INSTPM(ring->mmio_base); in intel_ring_setup_status_page() local
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| /gfx-drm/usr/src/uts/intel/io/radeon/ |
| H A D | r300_cmdbuf.c | 152 #define ADD_RANGE_MARK(reg, count, mark) \ in r300_init_reg_flags() argument
159 #define ADD_RANGE(reg, count) ADD_RANGE_MARK(reg, count, MARK_SAFE) in r300_init_reg_flags() argument
248 static __inline__ int r300_check_range(unsigned reg, int count) in r300_check_range()
263 int reg; in r300_emit_carefully_checked_packet0() local
317 int reg; in r300_emit_packet0() local
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| H A D | radeon_drv.h | 1006 #define RADEON_READ(reg) \ argument
1008 #define RADEON_WRITE(reg, val) \ argument
1010 #define RADEON_READ8(reg) \ argument
1012 #define RADEON_WRITE8(reg, val) \ argument
1029 #define CP_PACKET0(reg, n) \ argument
1031 #define CP_PACKET0_TABLE(reg, n) \ argument
1175 #define OUT_RING_REG(reg, val) do { \ argument
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| H A D | radeon_state.c | 2824 int sz, reg; in radeon_emit_packets() local
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