xref: /illumos-gate/usr/src/uts/common/io/qede/qede_fp.h (revision 14b24e2b)
1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, v.1,  (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://opensource.org/licenses/CDDL-1.0.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 
22 /*
23 * Copyright 2014-2017 Cavium, Inc.
24 * The contents of this file are subject to the terms of the Common Development
25 * and Distribution License, v.1,  (the "License").
26 
27 * You may not use this file except in compliance with the License.
28 
29 * You can obtain a copy of the License at available
30 * at http://opensource.org/licenses/CDDL-1.0
31 
32 * See the License for the specific language governing permissions and
33 * limitations under the License.
34 */
35 
36 #ifndef _QEDE_FP_H
37 #define _QEDE_FP_H
38 
39 #define	RX_INDICATE_UPSTREAM(rx_ring, mp) \
40 	mac_rx_ring(rx_ring->qede->mac_handle, \
41 	    rx_ring->mac_ring_handle, mp, \
42 	    rx_ring->mr_gen_num)
43 
44 #define	MAX_TX_RING_SIZE		8192
45 
46 #define	RESUME_TX(tx_ring)  mac_tx_ring_update(tx_ring->qede->mac_handle, \
47 			    tx_ring->mac_ring_handle)
48 
49 #define CQE_FLAGS_ERR   (PARSING_AND_ERR_FLAGS_IPHDRERROR_MASK <<   \
50 			PARSING_AND_ERR_FLAGS_IPHDRERROR_SHIFT |   \
51 			PARSING_AND_ERR_FLAGS_L4CHKSMERROR_MASK << \
52 			PARSING_AND_ERR_FLAGS_L4CHKSMERROR_SHIFT | \
53 			PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_MASK << \
54 			PARSING_AND_ERR_FLAGS_TUNNELIPHDRERROR_SHIFT | \
55 			PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_MASK << \
56 			PARSING_AND_ERR_FLAGS_TUNNELL4CHKSMERROR_SHIFT)
57 
58 /*
59  * VB: Keeping such perf. tuning macros as ifndefs so that
60  * they can be collectively tuned from Makefile when exp.
61  * are to be done
62  */
63 #ifndef	QEDE_POLL_ALL
64 #define	QEDE_POLL_ALL			INT_MAX
65 #endif
66 #ifndef	QEDE_MAX_RX_PKTS_PER_INTR
67 #define	QEDE_MAX_RX_PKTS_PER_INTR	128
68 #endif
69 
70 #ifndef	QEDE_TX_MAP_PATH_PAUSE_THRESHOLD
71 #define	QEDE_TX_MAP_PATH_PAUSE_THRESHOLD	128
72 #endif
73 
74 #ifndef	QEDE_TX_COPY_PATH_PAUSE_THRESHOLD
75 #define	QEDE_TX_COPY_PATH_PAUSE_THRESHOLD	8
76 #endif
77 
78 #define ETHER_VLAN_HEADER_LEN		sizeof (struct ether_vlan_header)
79 #define ETHER_HEADER_LEN                sizeof (struct ether_header)
80 #define IP_HEADER_LEN                   sizeof (ipha_t)
81 
82 #ifndef	MBLKL
83 #define	MBLKL(_mp_)	((uintptr_t)(_mp_)->b_wptr - (uintptr_t)(_mp_)->b_rptr)
84 #endif
85 
86 #define	UPDATE_RX_PROD(_ptr, data) \
87 	internal_ram_wr(&(_ptr)->qede->edev.hwfns[0], \
88 	    (_ptr)->hw_rxq_prod_addr, sizeof (data), \
89 	    (u32 *)&data);
90 
91 #define	BD_SET_ADDR_LEN(_bd, _addr, _len) \
92        do { \
93        	(_bd)->addr.hi = HOST_TO_LE_32(U64_HI(_addr)); \
94 	(_bd)->addr.lo = HOST_TO_LE_32(U64_LO(_addr)); \
95 	(_bd)->nbytes = HOST_TO_LE_32(_len); \
96        } while (0)
97 
98 enum qede_xmit_mode {
99 	XMIT_MODE_UNUSED,
100 	USE_DMA_BIND,
101 	USE_BCOPY,
102 	USE_PULLUP
103 };
104 
105 enum qede_xmit_status {
106 	XMIT_FAILED,
107 	XMIT_DONE,
108 	XMIT_FALLBACK_BCOPY,
109 	XMIT_FALLBACK_PULLUP,
110 	XMIT_PAUSE_QUEUE,
111 	XMIT_TOO_MANY_COOKIES
112 };
113 
114 /*
115  * Maintain the metadata of the
116  * tx packet in one place
117  */
118 typedef struct qede_tx_pktinfo_s {
119 	u32		total_len;
120 	u32		mblk_no;
121 	u32		cksum_flags;
122 
123 	/* tso releated */
124 	bool		use_lso;
125 	u16		mss;
126 
127 	bool 	pulled_up;
128 
129 	/* hdr parse data */
130 	u16		ether_type;
131 	u16		mac_hlen;
132 	u16		ip_hlen;
133 	u16		l4_hlen;
134 	u16		total_hlen;
135 	u16		l4_proto;
136 	u16		vlan_tag;
137 } qede_tx_pktinfo_t;
138 
139 typedef struct qede_tx_bcopy_pkt_s {
140 	mblk_t *mp;
141 	ddi_acc_handle_t	acc_handle;
142 	ddi_dma_handle_t	dma_handle;
143 	u32			ncookies;
144 	u32			offset;
145 	u64			phys_addr;
146 	void *virt_addr;
147 	u32			padding;
148 } qede_tx_bcopy_pkt_t;
149 
150 typedef	struct qede_tx_bcopy_list_s {
151 	qede_tx_bcopy_pkt_t *bcopy_pool;
152 	qede_tx_bcopy_pkt_t *free_list[MAX_TX_RING_SIZE];
153 	u16		head;
154 	u16		tail;
155 	kmutex_t	lock;
156 	size_t		size;
157 } qede_tx_bcopy_list_t;
158 
159 typedef	struct qede_dma_handle_entry_s {
160 	mblk_t *mp;
161 	ddi_dma_handle_t	dma_handle;
162 	struct qede_dma_handle_entry_s *next;
163 } qede_dma_handle_entry_t;
164 
165 typedef	struct qede_dma_handles_list_s {
166 	qede_dma_handle_entry_t	*dmah_pool;
167 	qede_dma_handle_entry_t *free_list[MAX_TX_RING_SIZE];
168 	u16		head;
169 	u16		tail;
170 	kmutex_t	lock;
171 	size_t		size;
172 } qede_dma_handles_list_t;
173 
174 typedef struct qede_tx_recycle_list_s {
175 	qede_tx_bcopy_pkt_t *bcopy_pkt;
176 	qede_dma_handle_entry_t	*dmah_entry;
177 } qede_tx_recycle_list_t;
178 
179 mblk_t *qede_ring_tx(void *arg, mblk_t *mp);
180 
181 #endif  /* !_QEDE_FP_H */
182