xref: /illumos-gate/usr/src/uts/sun4/io/px/px_space.c (revision 26947304)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 /*
27  * PCI Express nexus driver tunables
28  */
29 
30 #include <sys/types.h>
31 #include <sys/ddi.h>
32 #include <sys/sunddi.h>
33 #include <sys/cmn_err.h>
34 #include <sys/time.h>
35 #include "px_obj.h"
36 
37 /*LINTLIBRARY*/
38 
39 uint32_t px_spurintr_duration = 60000000; /* One minute */
40 uint64_t px_spurintr_msgs = PX_SPURINTR_MSG_DEFAULT;
41 
42 /*
43  * The following variable enables a workaround for the following obp bug:
44  *
45  *	1234181 - obp should set latency timer registers in pci
46  *		configuration header
47  *
48  * Until this bug gets fixed in the obp, the following workaround should
49  * be enabled.
50  */
51 uint_t px_set_latency_timer_register = 1;
52 
53 /*
54  * The following driver parameters are defined as variables to allow
55  * patching for debugging and tuning.  Flags that can be set on a per
56  * PBM basis are bit fields where the PBM device instance number maps
57  * to the bit position.
58  */
59 uint_t px_mmu_error_intr_enable = (uint_t)-1;
60 uint_t px_rerun_disable = 0;
61 
62 uint_t px_error_intr_enable = (uint_t)-1;
63 uint_t px_dwsync_disable = 0;
64 uint_t px_intsync_disable = 0;
65 
66 uint_t px_intr_retry_intv = 5;		/* for interrupt retry reg */
67 uint8_t px_latency_timer = 0x40;	/* for pci latency timer reg */
68 uint_t px_panic_on_fatal_errors = 1;	/* should be 1 at beta */
69 uint_t px_thermal_intr_fatal = 1;	/* thermal interrupts fatal */
70 uint_t px_buserr_interrupt = 1;	/* safari buserr interrupt */
71 uint_t px_ctx_no_active_flush = 0;	/* cannot handle active ctx flush */
72 uint_t px_use_contexts = 1;
73 
74 hrtime_t px_intrpend_timeout = 5ull * NANOSEC;	/* 5 seconds in nanoseconds */
75 
76 uint64_t px_perr_fatal = -1ull;
77 uint64_t px_serr_fatal = -1ull;
78 uint64_t px_errtrig_pa = 0x0;
79 
80 char px_panic_hb_msg[] = " System bus";
81 char px_panic_rc_msg[] = " PCIe root complex";
82 char px_panic_rp_msg[] = " PCIe root port";
83 char px_panic_fab_msg[] = " PCIe fabric";
84 
85 /*
86  * The following flag controls behavior of the ino handler routine
87  * when multiple interrupts are attached to a single ino.  Typically
88  * this case would occur for the ino's assigned to the PCI bus slots
89  * with multi-function devices or bus bridges.
90  *
91  * Setting the flag to zero causes the ino handler routine to return
92  * after finding the first interrupt handler to claim the interrupt.
93  *
94  * Setting the flag to non-zero causes the ino handler routine to
95  * return after making one complete pass through the interrupt
96  * handlers.
97  */
98 uint_t px_check_all_handlers = 1;
99 
100 /*
101  * The following value is the number of consecutive unclaimed interrupts that
102  * will be tolerated for a particular ino_p before the interrupt is deemed to
103  * be jabbering and is blocked.
104  */
105 uint_t px_unclaimed_intr_max = 20;
106 
107 /*
108  * The following value will cause the nexus driver to block an ino after
109  * px_unclaimed_intr_max unclaimed interrupts have been seen.  Setting this
110  * value to 0 will cause interrupts to never be blocked, no matter how many
111  * unclaimed interrupts are seen on a particular ino.
112  */
113 uint_t px_unclaimed_intr_block = 1;
114 
115 uint_t px_lock_tlb = 0;
116 
117 uint64_t px_dvma_debug_on = 0;
118 uint64_t px_dvma_debug_off = 0;
119 uint32_t px_dvma_debug_rec = 512;
120 
121 /*
122  * dvma address space allocation cache variables
123  */
124 uint_t px_dvma_page_cache_entries = 0x200;	/* # of chunks (1 << bits) */
125 uint_t px_dvma_page_cache_clustsz = 0x8;	/* # of pages per chunk */
126 #ifdef PX_DMA_PROF
127 uint_t px_dvmaft_npages = 0;			/* FT fail due npages */
128 uint_t px_dvmaft_limit = 0;			/* FT fail due limits */
129 uint_t px_dvmaft_free = 0;			/* FT free */
130 uint_t px_dvmaft_success = 0;			/* FT success */
131 uint_t px_dvmaft_exhaust = 0;			/* FT vmem fallback */
132 uint_t px_dvma_vmem_alloc = 0;			/* vmem alloc */
133 uint_t px_dvma_vmem_xalloc = 0;		/* vmem xalloc */
134 uint_t px_dvma_vmem_xfree = 0;			/* vmem xfree */
135 uint_t px_dvma_vmem_free = 0;			/* vmem free */
136 #endif
137 uint_t px_disable_fdvma = 0;
138 uint_t px_mmu_ctx_lock_failure = 0;
139 
140 uint_t px_max_msiq_msgs = 4;
141 uint_t px_min_msiq_msgs = 2;
142 
143 /*
144  * memory callback list id callback list for kmem_alloc failure clients
145  */
146 uintptr_t px_kmem_clid = 0;
147 
148 /* timeout in micro seconds for receiving PME_To_ACK */
149 uint64_t px_pme_to_ack_timeout	= PX_PME_TO_ACK_TIMEOUT;
150 
151 /* timeout in micro seconds for receiving link up interrupt */
152 uint64_t px_lup_poll_to = PX_LUP_POLL_TO;
153 uint64_t px_lup_poll_interval = PX_LUP_POLL_INTERVAL;
154 
155 /* PIL at which PME_To_ACK message interrupt is handled */
156 uint32_t px_pwr_pil		= PX_PWR_PIL;
157 
158 uint32_t px_max_l1_tries	= PX_MAX_L1_TRIES;
159 
160 /* Print and Log tunables.  The following variables are booleans */
161 #ifdef DEBUG
162 uint32_t px_log = PX_PANIC | PX_NO_PANIC | PX_PROTECTED | PX_HW_RESET;
163 #else
164 uint32_t px_log = PX_PANIC;
165 #endif
166 uint32_t px_die = PX_PANIC | PX_PROTECTED | PX_HW_RESET;
167