Searched defs:pil (Results 1 - 23 of 23) sorted by relevance

/illumos-gate/usr/src/uts/sun4v/sys/
H A Dcnex.h49 uint32_t pil; /* PIL for device class */ member in struct:cnex_intr_map
/illumos-gate/usr/src/uts/sun4/io/
H A Divintr.c184 add_ivintr(uint_t inum, uint_t pil, intrfunc intr_handler, argument
189 if (inum >= MAXIVNUM || pil > PIL_MAX)
202 if (iv_p->iv_pil == pil) {
215 new_iv_p->iv_pil = (ushort_t)pil;
229 rem_ivintr(uint_t inum, uint_t pil) argument
233 if (inum >= MAXIVNUM || pil > PIL_MAX)
240 if (iv_p->iv_pil == pil)
265 add_softintr(uint_t pil, softintrfunc intr_handler, caddr_t intr_arg1, argument
270 if (pil > PIL_MAX)
277 iv_p->iv_pil = (ushort_t)pil;
346 update_softint_pri(uint64_t softint_id, uint_t pil) argument
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H A Debus.c746 uint32_t pil; member in struct:ebus_string_to_pil
813 ebus_name_to_pil[i].pil);
815 hdlp->ih_pri = ebus_name_to_pil[i].pil;
831 string, ebus_device_type_to_pil[i].pil);
833 hdlp->ih_pri = ebus_device_type_to_pil[i].pil;
/illumos-gate/usr/src/cmd/mdb/sparc/mdb/
H A Dkvm_v9dep.c249 uint32_t pil; local
359 * which on sparcv9 is the %pil register's value.
361 if (mdb_tgt_readsym(t, MDB_TGT_AS_VIRT, &pil, sizeof (pil),
362 MDB_TGT_OBJ_EXEC, "panic_ipl") == sizeof (pil))
363 kregs[KREG_PIL] = pil;
/illumos-gate/usr/src/cmd/mdb/sparc/modules/intr/
H A Dintr.c46 uint32_t pil; member in struct:intr_info
250 info.pil = niumx_state.niumx_ihtable[i].ih_pri;
337 info.pil = ipil.ipil_pil;
439 info.pil = ipil.ipil_pil;
507 mdb_printf(" %4d\t", info.pil);
531 mdb_printf("Pil:\t\t%d\n", info.pil);
/illumos-gate/usr/src/uts/i86pc/io/apix/
H A Dapix_intr.c230 apix_do_softint_prolog(struct cpu *cpu, uint_t pil, uint_t oldpil, argument
238 ASSERT(pil > mcpu->mcpu_pri && pil > cpu->cpu_base_spl);
240 atomic_and_32((uint32_t *)&mcpu->mcpu_softinfo.st_pending, ~(1 << pil));
242 mcpu->mcpu_pri = pil;
259 mcpu->intrstat[pil][0] += intrtime;
285 smt_begin_intr(pil);
288 * Set bit for this pil in CPU's interrupt active bitmask.
290 ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0);
291 cpu->cpu_intr_actv |= (1 << pil);
308 uint_t pil, basespl; local
416 apix_hilevel_intr_prolog(struct cpu *cpu, uint_t pil, uint_t oldpil, struct regs *rp) argument
501 uint_t mask, pil; local
622 apix_intr_thread_prolog(struct cpu *cpu, uint_t pil, caddr_t stackptr) argument
697 uint_t pil, basespl; local
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/illumos-gate/usr/src/uts/i86pc/os/
H A Dsmt.c187 smt_intr_alloc_pil(uint_t pil) argument
189 ASSERT(pil <= PIL_MAX);
191 if (empty_pil == pil)
382 pil_needs_kick(uint_t pil) argument
384 return (pil != empty_pil);
388 smt_begin_intr(uint_t pil) argument
393 ASSERT(pil <= PIL_MAX);
403 if (atomic_inc_64_nv(&smt->cs_intr_depth) == 1 && pil_needs_kick(pil)) {
H A Dintr.c284 * | | | softint pil too low | |
536 * The 'pil' is already set to the appropriate level for rp->r_trapno.
539 hilevel_intr_prolog(struct cpu *cpu, uint_t pil, uint_t oldpil, struct regs *rp) argument
546 ASSERT(pil > LOCK_LEVEL);
548 if (pil == CBE_HIGH_PIL) {
573 ASSERT(nestpil < pil);
600 smt_begin_intr(pil);
605 mcpu->pil_high_start[pil - (LOCK_LEVEL + 1)] = now;
607 ASSERT((cpu->cpu_intr_actv & (1 << pil)) == 0);
609 if (pil
637 hilevel_intr_epilog(struct cpu *cpu, uint_t pil, uint_t oldpil, uint_t vecnum) argument
720 intr_thread_prolog(struct cpu *cpu, caddr_t stackptr, uint_t pil) argument
793 uint_t pil, basespl; local
930 uint_t pil; local
965 uint_t pil; local
1073 uint_t pil, basespl; local
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/illumos-gate/usr/src/uts/sun4v/io/
H A Dvnex.c48 * Vnex name to pil map
57 uint32_t pil; member in struct:vnex_pil_map
394 return (vnex_name_to_pil[i].pil);
398 * if not found pil is 0
H A Dcnex.c611 int rv, idx, pil; local
684 for (idx = 0, pil = PIL_3; idx < CNEX_MAX_DEVS; idx++) {
686 pil = cnex_class_to_intr[idx].pil;
692 if (add_ivintr(iinfo->icookie, pil, (intrfunc)cnex_intr_wrapper,
734 (void) rem_ivintr(iinfo->icookie, pil);
800 int rv, idx, pil; local
878 for (idx = 0, pil = PIL_3; idx < CNEX_MAX_DEVS; idx++) {
880 pil = cnex_class_to_intr[idx].pil;
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/illumos-gate/usr/src/uts/sun4/io/px/
H A Dpx_intr.c150 ushort_t pil = ipil_p->ipil_pil; local
155 "ino=%x sysino=%llx pil=%x ih_size=%x ih_lst=%x\n",
189 if (pil <= LOCK_LEVEL)
204 ino_p->ino_claimed |= (1 << pil);
206 /* Interrupt can only be cleared after all pil levels are handled */
207 if (pil != ino_p->ino_lopil)
254 ushort_t pil = ipil_p->ipil_pil; local
263 DBG(DBG_MSIQ_INTR, dip, "px_msiq_intr: msiq_id =%x ino=%x pil=%x "
398 if (pil <= LOCK_LEVEL)
433 ino_p->ino_claimed |= (1 << pil);
[all...]
H A Dpx_ib.c485 px_ib_new_ino_pil(px_ib_t *ib_p, devino_t ino_num, uint_t pil, px_ih_t *ih_p) argument
496 ipil_p->ipil_pil = pil;
507 if ((ino_p->ino_lopil == 0) || (ino_p->ino_lopil > pil))
508 ino_p->ino_lopil = pil;
517 ushort_t pil = ipil_p->ipil_pil; local
535 if ((--ino_p->ino_ipil_size) && (ino_p->ino_lopil == pil)) {
536 for (next = ino_p->ino_ipil_p, pil = next->ipil_pil;
539 if (pil > next->ipil_pil)
540 pil = next->ipil_pil;
544 * Value stored in pil shoul
589 px_ib_ino_locate_ipil(px_ino_t *ino_p, uint_t pil) argument
807 px_ib_update_intr_state(px_t *px_p, dev_info_t *rdip, uint_t inum, devino_t ino, uint_t pil, uint_t new_intr_state, msiq_rec_type_t rec_type, msgcode_t msg_code) argument
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/illumos-gate/usr/src/uts/sun4u/io/pci/
H A Dpci_ib.c511 ib_new_ino_pil(ib_t *ib_p, ib_ino_t ino_num, uint_t pil, ih_t *ih_p) argument
528 ino_p->ino_lopil = pil;
532 ipil_p->ipil_pil = pil;
543 if (ino_p->ino_lopil > pil)
544 ino_p->ino_lopil = pil;
554 ushort_t pil = ipil_p->ipil_pil; local
571 if ((--ino_p->ino_ipil_size) && (ino_p->ino_lopil == pil)) {
572 for (next = ino_p->ino_ipil_p, pil = next->ipil_pil;
575 if (pil > next->ipil_pil)
576 pil
617 ib_ino_locate_ipil(ib_ino_info_t *ino_p, uint_t pil) argument
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/illumos-gate/usr/src/uts/common/io/
H A Dpci_intr_lib.c47 /* default class to pil value mapping */
1268 * Return the pil for a given PCI device.
1273 uint32_t pil; local
1275 /* Default pil is 1 */
1276 pil = pci_class_to_val(rdip,
1281 if (pil >= 0xf)
1282 pil = 1;
1284 return (pil);
H A Davintr.c735 av_dispatch_softvect(uint_t pil) argument
744 ASSERT(pil >= 0 && pil <= PIL_MAX);
746 for (av = softvect[pil].avh_link; av; av = av->av_link) {
/illumos-gate/usr/src/uts/sun4/os/
H A Dintr.c336 no_ivintr(struct regs *rp, int inum, int pil) argument
339 cmn_err(CE_WARN, "invalid vector intr: number 0x%x, pil 0x%x",
340 inum, pil);
348 intr_dequeue_req(uint_t pil, uint64_t inum) argument
363 next = mcpu->intr_head[pil];
380 mcpu->intr_head[pil] = next_iv; /* head */
383 mcpu->intr_tail[pil] = prev; /* tail */
387 if (mcpu->intr_head[pil] == NULL) {
388 clr = 1 << pil;
389 if (pil
846 create_softint(uint_t pil, uint_t (*func)(caddr_t, caddr_t), caddr_t arg1) argument
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/illumos-gate/usr/src/uts/common/io/cardbus/
H A Dcardbus_cfg.c113 int pil; member in struct:cardbus_name_entry
/illumos-gate/usr/src/uts/sun4u/os/
H A Dcpr_impl.c473 uint_t pil, reset_pil; local
475 pil = getpil();
476 if (pil < XCALL_PIL)
484 setpil(pil);
/illumos-gate/usr/src/uts/sun4u/io/
H A Dsysiosbus.c224 uint32_t *pil, int32_t ign);
1573 spurious_cntr = &intr_info->softsp->spurious_cntrs[intr_info->pil];
1614 else if (intr_info->pil >= LOCK_LEVEL) {
1617 intr_info->pil);
1797 sbus_arg->pil = hdlp->ih_pri;
1980 uint32_t *pil, int32_t ign)
2028 if (*pil == 0) {
2034 *pil = SOC_PRIORITY;
2036 /* Figure out the pil associated with this interrupt */
2037 *pil
1979 sbus_xlate_intrs(dev_info_t *dip, dev_info_t *rdip, uint32_t *intr, uint32_t *pil, int32_t ign) argument
[all...]
/illumos-gate/usr/src/uts/sun4u/sys/
H A Dsysiosbus.h360 uint32_t pil; member in struct:sbus_wrapper_arg
/illumos-gate/usr/src/uts/common/io/nvme/
H A Dnvme.c1887 boolean_t ms, uint8_t pi, boolean_t pil, uint8_t ses)
1896 format_nvm.b.fm_pil = pil ? 1 : 0;
1886 nvme_format_nvm(nvme_t *nvme, boolean_t user, uint32_t nsid, uint8_t lbaf, boolean_t ms, uint8_t pi, boolean_t pil, uint8_t ses) argument
/illumos-gate/usr/src/uts/sun4u/sunfire/sys/
H A Dfhc.h958 uint_t pil; member in struct:fhcintrspec
/illumos-gate/usr/src/cmd/mdb/common/modules/genunix/
H A Dgenunix.c3122 uint8_t pil; local
3140 if ((pil = thr->t_pil) >= NINTR) {
3141 mdb_warn("thread %p has pil (%d) greater than %d\n",
3142 addr, pil, NINTR);
3146 if (cid->cid_ithr[id][pil] != 0) {
3147 mdb_warn("CPU %d has multiple threads at pil %d (at least "
3148 "%p and %p)\n", id, pil, addr, cid->cid_ithr[id][pil]);
3152 cid->cid_ithr[id][pil] = addr;

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