1 /*
2 * Copyright (c) 2006, 2016, Oracle and/or its affiliates. All rights reserved.
3 */
4
5 /*
6 * Copyright (c) 2006-2007, 2013, Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
26 *
27 * Authors:
28 * Eric Anholt <eric@anholt.net>
29 */
30
31 #include "drm_edid.h"
32 #include "drmP.h"
33 #include "intel_drv.h"
34 #include "i915_drm.h"
35 #include "i915_drv.h"
36 #include "drm_dp_helper.h"
37
38 #include "drm_crtc_helper.h"
39
40 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
41 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
42
43 typedef struct {
44 int min, max;
45 } intel_range_t;
46
47 typedef struct {
48 int dot_limit;
49 int p2_slow, p2_fast;
50 } intel_p2_t;
51
52 #define INTEL_P2_NUM 2
53 typedef struct intel_limit intel_limit_t;
54 struct intel_limit {
55 intel_range_t dot, vco, n, m, m1, m2, p, p1;
56 intel_p2_t p2;
57 };
58
59 /* FDI */
60 #define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
61
62 int
intel_pch_rawclk(struct drm_device * dev)63 intel_pch_rawclk(struct drm_device *dev)
64 {
65 struct drm_i915_private *dev_priv = dev->dev_private;
66
67 WARN_ON(!HAS_PCH_SPLIT(dev));
68
69 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
70 }
71
72 static inline u32 /* units of 100MHz */
intel_fdi_link_freq(struct drm_device * dev)73 intel_fdi_link_freq(struct drm_device *dev)
74 {
75 if (IS_GEN5(dev)) {
76 struct drm_i915_private *dev_priv = dev->dev_private;
77 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
78 } else
79 return 27;
80 }
81
82 static const intel_limit_t intel_limits_i8xx_dvo = {
83 .dot = { .min = 25000, .max = 350000 },
84 .vco = { .min = 930000, .max = 1400000 },
85 .n = { .min = 3, .max = 16 },
86 .m = { .min = 96, .max = 140 },
87 .m1 = { .min = 18, .max = 26 },
88 .m2 = { .min = 6, .max = 16 },
89 .p = { .min = 4, .max = 128 },
90 .p1 = { .min = 2, .max = 33 },
91 .p2 = { .dot_limit = 165000,
92 .p2_slow = 4, .p2_fast = 2 },
93 };
94
95 static const intel_limit_t intel_limits_i8xx_lvds = {
96 .dot = { .min = 25000, .max = 350000 },
97 .vco = { .min = 930000, .max = 1400000 },
98 .n = { .min = 3, .max = 16 },
99 .m = { .min = 96, .max = 140 },
100 .m1 = { .min = 18, .max = 26 },
101 .m2 = { .min = 6, .max = 16 },
102 .p = { .min = 4, .max = 128 },
103 .p1 = { .min = 1, .max = 6 },
104 .p2 = { .dot_limit = 165000,
105 .p2_slow = 14, .p2_fast = 7 },
106 };
107
108 static const intel_limit_t intel_limits_i9xx_sdvo = {
109 .dot = { .min = 20000, .max = 400000 },
110 .vco = { .min = 1400000, .max = 2800000 },
111 .n = { .min = 1, .max = 6 },
112 .m = { .min = 70, .max = 120 },
113 .m1 = { .min = 8, .max = 18 },
114 .m2 = { .min = 3, .max = 7 },
115 .p = { .min = 5, .max = 80 },
116 .p1 = { .min = 1, .max = 8 },
117 .p2 = { .dot_limit = 200000,
118 .p2_slow = 10, .p2_fast = 5 },
119 };
120
121 static const intel_limit_t intel_limits_i9xx_lvds = {
122 .dot = { .min = 20000, .max = 400000 },
123 .vco = { .min = 1400000, .max = 2800000 },
124 .n = { .min = 1, .max = 6 },
125 .m = { .min = 70, .max = 120 },
126 .m1 = { .min = 8, .max = 18 },
127 .m2 = { .min = 3, .max = 7 },
128 .p = { .min = 7, .max = 98 },
129 .p1 = { .min = 1, .max = 8 },
130 .p2 = { .dot_limit = 112000,
131 .p2_slow = 14, .p2_fast = 7 },
132 };
133
134
135 static const intel_limit_t intel_limits_g4x_sdvo = {
136 .dot = { .min = 25000, .max = 270000 },
137 .vco = { .min = 1750000, .max = 3500000},
138 .n = { .min = 1, .max = 4 },
139 .m = { .min = 104, .max = 138 },
140 .m1 = { .min = 17, .max = 23 },
141 .m2 = { .min = 5, .max = 11 },
142 .p = { .min = 10, .max = 30 },
143 .p1 = { .min = 1, .max = 3},
144 .p2 = { .dot_limit = 270000,
145 .p2_slow = 10,
146 .p2_fast = 10
147 },
148 };
149
150 static const intel_limit_t intel_limits_g4x_hdmi = {
151 .dot = { .min = 22000, .max = 400000 },
152 .vco = { .min = 1750000, .max = 3500000},
153 /* n.min 1->2 fix high resolution issue */
154 .n = { .min = 2, .max = 4 },
155 .m = { .min = 104, .max = 138 },
156 .m1 = { .min = 16, .max = 23 },
157 .m2 = { .min = 5, .max = 11 },
158 .p = { .min = 5, .max = 80 },
159 .p1 = { .min = 1, .max = 8},
160 .p2 = { .dot_limit = 165000,
161 .p2_slow = 10, .p2_fast = 5 },
162 };
163
164 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
165 .dot = { .min = 20000, .max = 115000 },
166 .vco = { .min = 1750000, .max = 3500000 },
167 .n = { .min = 1, .max = 3 },
168 .m = { .min = 104, .max = 138 },
169 .m1 = { .min = 17, .max = 23 },
170 .m2 = { .min = 5, .max = 11 },
171 .p = { .min = 28, .max = 112 },
172 .p1 = { .min = 2, .max = 8 },
173 .p2 = { .dot_limit = 0,
174 .p2_slow = 14, .p2_fast = 14
175 },
176 };
177
178 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
179 .dot = { .min = 80000, .max = 224000 },
180 .vco = { .min = 1750000, .max = 3500000 },
181 .n = { .min = 1, .max = 3 },
182 .m = { .min = 104, .max = 138 },
183 .m1 = { .min = 17, .max = 23 },
184 .m2 = { .min = 5, .max = 11 },
185 .p = { .min = 14, .max = 42 },
186 .p1 = { .min = 2, .max = 6 },
187 .p2 = { .dot_limit = 0,
188 .p2_slow = 7, .p2_fast = 7
189 },
190 };
191
192 static const intel_limit_t intel_limits_pineview_sdvo = {
193 .dot = { .min = 20000, .max = 400000},
194 .vco = { .min = 1700000, .max = 3500000 },
195 /* Pineview's Ncounter is a ring counter */
196 .n = { .min = 3, .max = 6 },
197 .m = { .min = 2, .max = 256 },
198 /* Pineview only has one combined m divider, which we treat as m2. */
199 .m1 = { .min = 0, .max = 0 },
200 .m2 = { .min = 0, .max = 254 },
201 .p = { .min = 5, .max = 80 },
202 .p1 = { .min = 1, .max = 8 },
203 .p2 = { .dot_limit = 200000,
204 .p2_slow = 10, .p2_fast = 5 },
205 };
206
207 static const intel_limit_t intel_limits_pineview_lvds = {
208 .dot = { .min = 20000, .max = 400000 },
209 .vco = { .min = 1700000, .max = 3500000 },
210 .n = { .min = 3, .max = 6 },
211 .m = { .min = 2, .max = 256 },
212 .m1 = { .min = 0, .max = 0 },
213 .m2 = { .min = 0, .max = 254 },
214 .p = { .min = 7, .max = 112 },
215 .p1 = { .min = 1, .max = 8 },
216 .p2 = { .dot_limit = 112000,
217 .p2_slow = 14, .p2_fast = 14 },
218 };
219
220 /* Ironlake / Sandybridge
221 *
222 * We calculate clock using (register_value + 2) for N/M1/M2, so here
223 * the range value for them is (actual_value - 2).
224 */
225 static const intel_limit_t intel_limits_ironlake_dac = {
226 .dot = { .min = 25000, .max = 350000 },
227 .vco = { .min = 1760000, .max = 3510000 },
228 /* n.min 1->2 fix high resolution issue */
229 .n = { .min = 2, .max = 5 },
230 .m = { .min = 79, .max = 127 },
231 .m1 = { .min = 12, .max = 22 },
232 .m2 = { .min = 5, .max = 9 },
233 .p = { .min = 5, .max = 80 },
234 .p1 = { .min = 1, .max = 8 },
235 .p2 = { .dot_limit = 225000,
236 .p2_slow = 10, .p2_fast = 5 },
237 };
238
239 static const intel_limit_t intel_limits_ironlake_single_lvds = {
240 .dot = { .min = 25000, .max = 350000 },
241 .vco = { .min = 1760000, .max = 3510000 },
242 .n = { .min = 1, .max = 3 },
243 .m = { .min = 79, .max = 118 },
244 .m1 = { .min = 12, .max = 22 },
245 .m2 = { .min = 5, .max = 9 },
246 .p = { .min = 28, .max = 112 },
247 .p1 = { .min = 2, .max = 8 },
248 .p2 = { .dot_limit = 225000,
249 .p2_slow = 14, .p2_fast = 14 },
250 };
251
252 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
253 .dot = { .min = 25000, .max = 350000 },
254 .vco = { .min = 1760000, .max = 3510000 },
255 .n = { .min = 1, .max = 3 },
256 .m = { .min = 79, .max = 127 },
257 .m1 = { .min = 12, .max = 22 },
258 .m2 = { .min = 5, .max = 9 },
259 .p = { .min = 14, .max = 56 },
260 .p1 = { .min = 2, .max = 8 },
261 .p2 = { .dot_limit = 225000,
262 .p2_slow = 7, .p2_fast = 7 },
263 };
264
265 /* LVDS 100mhz refclk limits. */
266 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
267 .dot = { .min = 25000, .max = 350000 },
268 .vco = { .min = 1760000, .max = 3510000 },
269 .n = { .min = 1, .max = 2 },
270 .m = { .min = 79, .max = 126 },
271 .m1 = { .min = 12, .max = 22 },
272 .m2 = { .min = 5, .max = 9 },
273 .p = { .min = 28, .max = 112 },
274 .p1 = { .min = 2,.max = 8 },
275 .p2 = { .dot_limit = 225000,
276 .p2_slow = 14, .p2_fast = 14 },
277 };
278
279 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
280 .dot = { .min = 25000, .max = 350000 },
281 .vco = { .min = 1760000, .max = 3510000 },
282 .n = { .min = 1, .max = 3 },
283 .m = { .min = 79, .max = 126 },
284 .m1 = { .min = 12, .max = 22 },
285 .m2 = { .min = 5, .max = 9 },
286 .p = { .min = 14, .max = 42 },
287 .p1 = { .min = 2,.max = 6 },
288 .p2 = { .dot_limit = 225000,
289 .p2_slow = 7, .p2_fast = 7 },
290 };
291
292 static const intel_limit_t intel_limits_vlv_dac = {
293 .dot = { .min = 25000, .max = 270000 },
294 .vco = { .min = 4000000, .max = 6000000 },
295 .n = { .min = 1, .max = 7 },
296 .m = { .min = 22, .max = 450 }, /* guess */
297 .m1 = { .min = 2, .max = 3 },
298 .m2 = { .min = 11, .max = 156 },
299 .p = { .min = 10, .max = 30 },
300 .p1 = { .min = 1, .max = 3 },
301 .p2 = { .dot_limit = 270000,
302 .p2_slow = 2, .p2_fast = 20 },
303 };
304
305 static const intel_limit_t intel_limits_vlv_hdmi = {
306 .dot = { .min = 25000, .max = 270000 },
307 .vco = { .min = 4000000, .max = 6000000 },
308 .n = { .min = 1, .max = 7 },
309 .m = { .min = 60, .max = 300 }, /* guess */
310 .m1 = { .min = 2, .max = 3 },
311 .m2 = { .min = 11, .max = 156 },
312 .p = { .min = 10, .max = 30 },
313 .p1 = { .min = 2, .max = 3 },
314 .p2 = { .dot_limit = 270000,
315 .p2_slow = 2, .p2_fast = 20 },
316 };
317
318 static const intel_limit_t intel_limits_vlv_dp = {
319 .dot = { .min = 25000, .max = 270000 },
320 .vco = { .min = 4000000, .max = 6000000 },
321 .n = { .min = 1, .max = 7 },
322 .m = { .min = 22, .max = 450 },
323 .m1 = { .min = 2, .max = 3 },
324 .m2 = { .min = 11, .max = 156 },
325 .p = { .min = 10, .max = 30 },
326 .p1 = { .min = 1, .max = 3 },
327 .p2 = { .dot_limit = 270000,
328 .p2_slow = 2, .p2_fast = 20 },
329 };
330
intel_ironlake_limit(struct drm_crtc * crtc,int refclk)331 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
332 int refclk)
333 {
334 struct drm_device *dev = crtc->dev;
335 const intel_limit_t *limit;
336
337 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
338 if (intel_is_dual_link_lvds(dev)) {
339 if (refclk == 100000)
340 limit = &intel_limits_ironlake_dual_lvds_100m;
341 else
342 limit = &intel_limits_ironlake_dual_lvds;
343 } else {
344 if (refclk == 100000)
345 limit = &intel_limits_ironlake_single_lvds_100m;
346 else
347 limit = &intel_limits_ironlake_single_lvds;
348 }
349 } else
350 limit = &intel_limits_ironlake_dac;
351
352 return limit;
353 }
354
intel_g4x_limit(struct drm_crtc * crtc)355 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
356 {
357 struct drm_device *dev = crtc->dev;
358 const intel_limit_t *limit;
359
360 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
361 if (intel_is_dual_link_lvds(dev))
362 limit = &intel_limits_g4x_dual_channel_lvds;
363 else
364 limit = &intel_limits_g4x_single_channel_lvds;
365 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
366 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
367 limit = &intel_limits_g4x_hdmi;
368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
369 limit = &intel_limits_g4x_sdvo;
370 } else /* The option is for other outputs */
371 limit = &intel_limits_i9xx_sdvo;
372
373 return limit;
374 }
375
intel_limit(struct drm_crtc * crtc,int refclk)376 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
377 {
378 struct drm_device *dev = crtc->dev;
379 const intel_limit_t *limit;
380
381 if (HAS_PCH_SPLIT(dev))
382 limit = intel_ironlake_limit(crtc, refclk);
383 else if (IS_G4X(dev)) {
384 limit = intel_g4x_limit(crtc);
385 } else if (IS_PINEVIEW(dev)) {
386 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
387 limit = &intel_limits_pineview_lvds;
388 else
389 limit = &intel_limits_pineview_sdvo;
390 } else if (IS_VALLEYVIEW(dev)) {
391 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
392 limit = &intel_limits_vlv_dac;
393 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
394 limit = &intel_limits_vlv_hdmi;
395 else
396 limit = &intel_limits_vlv_dp;
397 } else if (!IS_GEN2(dev)) {
398 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
399 limit = &intel_limits_i9xx_lvds;
400 else
401 limit = &intel_limits_i9xx_sdvo;
402 } else {
403 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
404 limit = &intel_limits_i8xx_lvds;
405 else
406 limit = &intel_limits_i8xx_dvo;
407 }
408 return limit;
409 }
410
411 /* m1 is reserved as 0 in Pineview, n is a ring counter */
pineview_clock(int refclk,intel_clock_t * clock)412 static void pineview_clock(int refclk, intel_clock_t *clock)
413 {
414 clock->m = clock->m2 + 2;
415 clock->p = clock->p1 * clock->p2;
416 clock->vco = refclk * clock->m / clock->n;
417 clock->dot = clock->vco / clock->p;
418 }
419
i9xx_dpll_compute_m(struct dpll * dpll)420 static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
421 {
422 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
423 }
424
i9xx_clock(int refclk,intel_clock_t * clock)425 static void i9xx_clock(int refclk, intel_clock_t *clock)
426 {
427 clock->m = i9xx_dpll_compute_m(clock);
428 clock->p = clock->p1 * clock->p2;
429 clock->vco = refclk * clock->m / (clock->n + 2);
430 clock->dot = clock->vco / clock->p;
431 }
432
433 /**
434 * Returns whether any output on the specified pipe is of the specified type
435 */
intel_pipe_has_type(struct drm_crtc * crtc,int type)436 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
437 {
438 struct drm_device *dev = crtc->dev;
439 struct intel_encoder *encoder;
440
441 for_each_encoder_on_crtc(dev, crtc, encoder)
442 if (encoder->type == type)
443 return true;
444
445 return false;
446 }
447
448 #define INTELPllInvalid(s) { DRM_DEBUG_KMS(s); return false; }
449 /**
450 * Returns whether the given set of divisors are valid for a given refclk with
451 * the given connectors.
452 */
453
intel_PLL_is_valid(struct drm_device * dev,const intel_limit_t * limit,const intel_clock_t * clock)454 static bool intel_PLL_is_valid(struct drm_device *dev,
455 const intel_limit_t *limit,
456 const intel_clock_t *clock)
457 {
458 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
459 INTELPllInvalid ("p1 out of range\n");
460 if (clock->p < limit->p.min || limit->p.max < clock->p)
461 INTELPllInvalid ("p out of range\n");
462 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
463 INTELPllInvalid ("m2 out of range\n");
464 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
465 INTELPllInvalid ("m1 out of range\n");
466 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
467 INTELPllInvalid ("m1 <= m2\n");
468 if (clock->m < limit->m.min || limit->m.max < clock->m)
469 INTELPllInvalid ("m out of range\n");
470 if (clock->n < limit->n.min || limit->n.max < clock->n)
471 INTELPllInvalid ("n out of range\n");
472 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
473 INTELPllInvalid ("vco out of range\n");
474 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
475 * connector, etc., rather than just a single range.
476 */
477 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
478 INTELPllInvalid ("dot out of range\n");
479
480 return true;
481 }
482
483 static bool
i9xx_find_best_dpll(const intel_limit_t * limit,struct drm_crtc * crtc,int target,int refclk,intel_clock_t * match_clock,intel_clock_t * best_clock)484 i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
485 int target, int refclk, intel_clock_t *match_clock,
486 intel_clock_t *best_clock)
487 {
488 struct drm_device *dev = crtc->dev;
489 intel_clock_t clock;
490 int err = target;
491
492 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
493 /*
494 * For LVDS just rely on its current settings for dual-channel.
495 * We haven't figured out how to reliably set up different
496 * single/dual channel state, if we even can.
497 */
498 if (intel_is_dual_link_lvds(dev))
499 clock.p2 = limit->p2.p2_fast;
500 else
501 clock.p2 = limit->p2.p2_slow;
502 } else {
503 if (target < limit->p2.dot_limit)
504 clock.p2 = limit->p2.p2_slow;
505 else
506 clock.p2 = limit->p2.p2_fast;
507 }
508
509 (void) memset (best_clock, 0, sizeof (*best_clock));
510
511 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
512 clock.m1++) {
513 for (clock.m2 = limit->m2.min;
514 clock.m2 <= limit->m2.max; clock.m2++) {
515 if (clock.m2 >= clock.m1)
516 break;
517 for (clock.n = limit->n.min;
518 clock.n <= limit->n.max; clock.n++) {
519 for (clock.p1 = limit->p1.min;
520 clock.p1 <= limit->p1.max; clock.p1++) {
521 int this_err;
522
523 i9xx_clock(refclk, &clock);
524 if (!intel_PLL_is_valid(dev, limit,
525 &clock))
526 continue;
527 if (match_clock &&
528 clock.p != match_clock->p)
529 continue;
530
531 this_err = abs(clock.dot - target);
532 if (this_err < err) {
533 *best_clock = clock;
534 err = this_err;
535 }
536 }
537 }
538 }
539 }
540
541 return (err != target);
542 }
543
544 static bool
pnv_find_best_dpll(const intel_limit_t * limit,struct drm_crtc * crtc,int target,int refclk,intel_clock_t * match_clock,intel_clock_t * best_clock)545 pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
546 int target, int refclk, intel_clock_t *match_clock,
547 intel_clock_t *best_clock)
548 {
549 struct drm_device *dev = crtc->dev;
550 intel_clock_t clock;
551 int err = target;
552
553 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
554 /*
555 * For LVDS just rely on its current settings for dual-channel.
556 * We haven't figured out how to reliably set up different
557 * single/dual channel state, if we even can.
558 */
559 if (intel_is_dual_link_lvds(dev))
560 clock.p2 = limit->p2.p2_fast;
561 else
562 clock.p2 = limit->p2.p2_slow;
563 } else {
564 if (target < limit->p2.dot_limit)
565 clock.p2 = limit->p2.p2_slow;
566 else
567 clock.p2 = limit->p2.p2_fast;
568 }
569
570 (void) memset(best_clock, 0, sizeof(*best_clock));
571
572 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
573 clock.m1++) {
574 for (clock.m2 = limit->m2.min;
575 clock.m2 <= limit->m2.max; clock.m2++) {
576 for (clock.n = limit->n.min;
577 clock.n <= limit->n.max; clock.n++) {
578 for (clock.p1 = limit->p1.min;
579 clock.p1 <= limit->p1.max; clock.p1++) {
580 int this_err;
581
582 pineview_clock(refclk, &clock);
583 if (!intel_PLL_is_valid(dev, limit,
584 &clock))
585 continue;
586 if (match_clock &&
587 clock.p != match_clock->p)
588 continue;
589
590 this_err = abs(clock.dot - target);
591 if (this_err < err) {
592 *best_clock = clock;
593 err = this_err;
594 }
595 }
596 }
597 }
598 }
599
600 return (err != target);
601 }
602
603 static bool
g4x_find_best_dpll(const intel_limit_t * limit,struct drm_crtc * crtc,int target,int refclk,intel_clock_t * match_clock,intel_clock_t * best_clock)604 g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
605 int target, int refclk, intel_clock_t *match_clock,
606 intel_clock_t *best_clock)
607 {
608 struct drm_device *dev = crtc->dev;
609 intel_clock_t clock;
610 int max_n;
611 bool found;
612 /* approximately equals target * 0.00585 */
613 int err_most = (target >> 8) + (target >> 9);
614 found = false;
615
616 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
617 if (intel_is_dual_link_lvds(dev))
618 clock.p2 = limit->p2.p2_fast;
619 else
620 clock.p2 = limit->p2.p2_slow;
621 } else {
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
624 else
625 clock.p2 = limit->p2.p2_fast;
626 }
627
628 (void) memset(best_clock, 0, sizeof(*best_clock));
629 max_n = limit->n.max;
630 /* based on hardware requirement prefer smaller n to precision */
631 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
632 /* based on hardware requirement prefer larger m1,m2 */
633 for (clock.m1 = limit->m1.max;
634 clock.m1 >= limit->m1.min; clock.m1--) {
635 for (clock.m2 = limit->m2.max;
636 clock.m2 >= limit->m2.min; clock.m2--) {
637 for (clock.p1 = limit->p1.max;
638 clock.p1 >= limit->p1.min; clock.p1--) {
639 int this_err;
640
641 i9xx_clock(refclk, &clock);
642 if (!intel_PLL_is_valid(dev, limit,
643 &clock))
644 continue;
645
646 this_err = abs(clock.dot - target) ;
647 if (this_err < err_most) {
648 *best_clock = clock;
649 err_most = this_err;
650 max_n = clock.n;
651 found = true;
652 }
653 }
654 }
655 }
656 }
657 return found;
658 }
659
660 static bool
vlv_find_best_dpll(const intel_limit_t * limit,struct drm_crtc * crtc,int target,int refclk,intel_clock_t * match_clock,intel_clock_t * best_clock)661 vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
662 int target, int refclk, intel_clock_t *match_clock,
663 intel_clock_t *best_clock)
664 {
665 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
666 u32 m, n, fastclk;
667 u32 updrate, minupdate, p;
668 unsigned long bestppm, ppm, absppm;
669 int dotclk, flag;
670
671 flag = 0;
672 dotclk = target * 1000;
673 bestppm = 1000000;
674 ppm = absppm = 0;
675 fastclk = dotclk / (2*100);
676 updrate = 0;
677 minupdate = 19200;
678 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
679 bestm1 = bestm2 = bestp1 = bestp2 = 0;
680
681 /* based on hardware requirement, prefer smaller n to precision */
682 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
683 updrate = refclk / n;
684 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
685 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
686 if (p2 > 10)
687 p2 = p2 - 1;
688 p = p1 * p2;
689 /* based on hardware requirement, prefer bigger m1,m2 values */
690 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
691 m2 = (((2*(fastclk * p * n / m1 )) +
692 refclk) / (2*refclk));
693 m = m1 * m2;
694 vco = updrate * m;
695 if (vco >= limit->vco.min && vco < limit->vco.max) {
696 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
697 absppm = (ppm > 0) ? ppm : (-ppm);
698 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
699 bestppm = 0;
700 flag = 1;
701 }
702 if (absppm < bestppm - 10) {
703 bestppm = absppm;
704 flag = 1;
705 }
706 if (flag) {
707 bestn = n;
708 bestm1 = m1;
709 bestm2 = m2;
710 bestp1 = p1;
711 bestp2 = p2;
712 flag = 0;
713 }
714 }
715 }
716 }
717 }
718 }
719 best_clock->n = bestn;
720 best_clock->m1 = bestm1;
721 best_clock->m2 = bestm2;
722 best_clock->p1 = bestp1;
723 best_clock->p2 = bestp2;
724
725 return true;
726 }
727
intel_pipe_to_cpu_transcoder(struct drm_i915_private * dev_priv,enum pipe pipe)728 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
729 enum pipe pipe)
730 {
731 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
732 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
733
734 return intel_crtc->config.cpu_transcoder;
735 }
736
ironlake_wait_for_vblank(struct drm_device * dev,int pipe)737 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
738 {
739 struct drm_i915_private *dev_priv = dev->dev_private;
740 u32 frame, frame_reg = PIPEFRAME(pipe);
741
742 frame = I915_READ(frame_reg);
743
744 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
745 DRM_DEBUG_KMS("vblank wait timed out\n");
746 }
747
748 /**
749 * intel_wait_for_vblank - wait for vblank on a given pipe
750 * @dev: drm device
751 * @pipe: pipe to wait for
752 *
753 * Wait for vblank to occur on a given pipe. Needed for various bits of
754 * mode setting code.
755 */
intel_wait_for_vblank(struct drm_device * dev,int pipe)756 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
757 {
758 struct drm_i915_private *dev_priv = dev->dev_private;
759 int pipestat_reg = PIPESTAT(pipe);
760
761 if (INTEL_INFO(dev)->gen >= 5) {
762 ironlake_wait_for_vblank(dev, pipe);
763 return;
764 }
765
766 /* Clear existing vblank status. Note this will clear any other
767 * sticky status fields as well.
768 *
769 * This races with i915_driver_irq_handler() with the result
770 * that either function could miss a vblank event. Here it is not
771 * fatal, as we will either wait upon the next vblank interrupt or
772 * timeout. Generally speaking intel_wait_for_vblank() is only
773 * called during modeset at which time the GPU should be idle and
774 * should *not* be performing page flips and thus not waiting on
775 * vblanks...
776 * Currently, the result of us stealing a vblank from the irq
777 * handler is that a single frame will be skipped during swapbuffers.
778 */
779 I915_WRITE(pipestat_reg,
780 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
781
782 /* Wait for vblank interrupt bit to set */
783 if (wait_for(I915_READ(pipestat_reg) &
784 PIPE_VBLANK_INTERRUPT_STATUS,
785 50))
786 DRM_DEBUG_KMS("vblank wait timed out\n");
787 }
788
789 /*
790 * intel_wait_for_pipe_off - wait for pipe to turn off
791 * @dev: drm device
792 * @pipe: pipe to wait for
793 *
794 * After disabling a pipe, we can't wait for vblank in the usual way,
795 * spinning on the vblank interrupt status bit, since we won't actually
796 * see an interrupt when the pipe is disabled.
797 *
798 * On Gen4 and above:
799 * wait for the pipe register state bit to turn off
800 *
801 * Otherwise:
802 * wait for the display line value to settle (it usually
803 * ends up stopping at the start of the next frame).
804 *
805 */
intel_wait_for_pipe_off(struct drm_device * dev,int pipe)806 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
807 {
808 struct drm_i915_private *dev_priv = dev->dev_private;
809 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
810 pipe);
811
812 if (INTEL_INFO(dev)->gen >= 4) {
813 int reg = PIPECONF(cpu_transcoder);
814
815 /* Wait for the Pipe State to go off */
816 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
817 100))
818 DRM_ERROR("pipe_off wait timed out\n");
819 } else {
820 u32 last_line, line_mask;
821 int reg = PIPEDSL(pipe);
822 unsigned long timeout = jiffies + msecs_to_jiffies(100);
823
824 if (IS_GEN2(dev))
825 line_mask = DSL_LINEMASK_GEN2;
826 else
827 line_mask = DSL_LINEMASK_GEN3;
828
829 /* Wait for the display line to settle */
830 do {
831 last_line = I915_READ(reg) & line_mask;
832 mdelay(5);
833 } while (((I915_READ(reg) & line_mask) != last_line) &&
834 time_after(timeout, jiffies));
835 if (time_after(jiffies, timeout))
836 DRM_ERROR("pipe_off wait timed out\n");
837 }
838 }
839
840 /*
841 * ibx_digital_port_connected - is the specified port connected?
842 * @dev_priv: i915 private structure
843 * @port: the port to test
844 *
845 * Returns true if @port is connected, false otherwise.
846 */
ibx_digital_port_connected(struct drm_i915_private * dev_priv,struct intel_digital_port * port)847 bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
848 struct intel_digital_port *port)
849 {
850 u32 bit;
851
852 if (HAS_PCH_IBX(dev_priv->dev)) {
853 switch(port->port) {
854 case PORT_B:
855 bit = SDE_PORTB_HOTPLUG;
856 break;
857 case PORT_C:
858 bit = SDE_PORTC_HOTPLUG;
859 break;
860 case PORT_D:
861 bit = SDE_PORTD_HOTPLUG;
862 break;
863 default:
864 return true;
865 }
866 } else {
867 switch(port->port) {
868 case PORT_B:
869 bit = SDE_PORTB_HOTPLUG_CPT;
870 break;
871 case PORT_C:
872 bit = SDE_PORTC_HOTPLUG_CPT;
873 break;
874 case PORT_D:
875 bit = SDE_PORTD_HOTPLUG_CPT;
876 break;
877 default:
878 return true;
879 }
880 }
881
882 return I915_READ(SDEISR) & bit;
883 }
884
state_string(bool enabled)885 static const char *state_string(bool enabled)
886 {
887 return enabled ? "on" : "off";
888 }
889
890 /* Only for pre-ILK configs */
assert_pll(struct drm_i915_private * dev_priv,enum pipe pipe,bool state)891 static void assert_pll(struct drm_i915_private *dev_priv,
892 enum pipe pipe, bool state)
893 {
894 int reg;
895 u32 val;
896 bool cur_state;
897
898 reg = DPLL(pipe);
899 val = I915_READ(reg);
900 cur_state = !!(val & DPLL_VCO_ENABLE);
901 if (cur_state != state)
902 DRM_ERROR("PLL state assertion failure (expected %s, current %s)",
903 state_string(state), state_string(cur_state));
904 }
905 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
906 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
907
908 static struct intel_shared_dpll *
intel_crtc_to_shared_dpll(struct intel_crtc * crtc)909 intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
910 {
911 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
912
913 if (crtc->config.shared_dpll < 0)
914 return NULL;
915
916 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
917 }
918
919 /* For ILK+ */
assert_shared_dpll(struct drm_i915_private * dev_priv,struct intel_shared_dpll * pll,bool state)920 static void assert_shared_dpll(struct drm_i915_private *dev_priv,
921 struct intel_shared_dpll *pll,
922 bool state)
923 {
924 bool cur_state;
925 struct intel_dpll_hw_state hw_state;
926
927 if (HAS_PCH_LPT(dev_priv->dev)) {
928 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
929 return;
930 }
931
932 if (!pll) {
933 DRM_ERROR("asserting PCH PLL %s with no PLL\n", state_string(state));
934 return;
935 }
936
937 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
938 if (cur_state != state)
939 DRM_DEBUG_KMS("%s assertion failure (expected %s, current %s)",
940 pll->name, state_string(state), state_string(cur_state));
941 }
942 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
943 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
944
assert_fdi_tx(struct drm_i915_private * dev_priv,enum pipe pipe,bool state)945 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
946 enum pipe pipe, bool state)
947 {
948 int reg;
949 u32 val;
950 bool cur_state;
951 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
952 pipe);
953
954 if (HAS_DDI(dev_priv->dev)) {
955 /* On Haswell, DDI is used instead of FDI_TX_CTL */
956 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
957 val = I915_READ(reg);
958 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
959 } else {
960 reg = FDI_TX_CTL(pipe);
961 val = I915_READ(reg);
962 cur_state = !!(val & FDI_TX_ENABLE);
963 }
964 if(cur_state != state)
965 DRM_ERROR("FDI TX state assertion failure (expected %s, current %s)\n",
966 state_string(state), state_string(cur_state));
967 }
968 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
969 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
970
assert_fdi_rx(struct drm_i915_private * dev_priv,enum pipe pipe,bool state)971 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
972 enum pipe pipe, bool state)
973 {
974 int reg;
975 u32 val;
976 bool cur_state;
977
978 reg = FDI_RX_CTL(pipe);
979 val = I915_READ(reg);
980 cur_state = !!(val & FDI_RX_ENABLE);
981 if(cur_state != state)
982 DRM_ERROR("FDI RX state assertion failure (expected %s, current %s)\n",
983 state_string(state), state_string(cur_state));
984 }
985 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
986 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
987
assert_fdi_tx_pll_enabled(struct drm_i915_private * dev_priv,enum pipe pipe)988 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
989 enum pipe pipe)
990 {
991 int reg;
992 u32 val;
993
994 /* ILK FDI PLL is always enabled */
995 if (dev_priv->info->gen == 5)
996 return;
997
998 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
999 if (HAS_DDI(dev_priv->dev))
1000 return;
1001
1002 reg = FDI_TX_CTL(pipe);
1003 val = I915_READ(reg);
1004 if(!(val & FDI_TX_PLL_ENABLE))
1005 DRM_ERROR("FDI TX PLL assertion failure, should be active but is disabled\n");
1006 }
1007
assert_fdi_rx_pll_enabled(struct drm_i915_private * dev_priv,enum pipe pipe)1008 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1009 enum pipe pipe)
1010 {
1011 int reg;
1012 u32 val;
1013
1014 reg = FDI_RX_CTL(pipe);
1015 val = I915_READ(reg);
1016 if(!(val & FDI_RX_PLL_ENABLE))
1017 DRM_ERROR("FDI RX PLL assertion failure, should be active but is disabled\n");
1018 }
1019
assert_panel_unlocked(struct drm_i915_private * dev_priv,enum pipe pipe)1020 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1021 enum pipe pipe)
1022 {
1023 int pp_reg, lvds_reg;
1024 u32 val;
1025 enum pipe panel_pipe = PIPE_A;
1026 bool locked = true;
1027
1028 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1029 pp_reg = PCH_PP_CONTROL;
1030 lvds_reg = PCH_LVDS;
1031 } else {
1032 pp_reg = PP_CONTROL;
1033 lvds_reg = LVDS;
1034 }
1035
1036 val = I915_READ(pp_reg);
1037 if (!(val & PANEL_POWER_ON) ||
1038 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1039 locked = false;
1040
1041 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1042 panel_pipe = PIPE_B;
1043
1044 if(panel_pipe == pipe && locked)
1045 DRM_ERROR("panel assertion failure, pipe %c regs locked\n",
1046 pipe_name(pipe));
1047 }
1048
assert_pipe(struct drm_i915_private * dev_priv,enum pipe pipe,bool state)1049 void assert_pipe(struct drm_i915_private *dev_priv,
1050 enum pipe pipe, bool state)
1051 {
1052 int reg;
1053 u32 val;
1054 bool cur_state;
1055 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1056 pipe);
1057
1058 /* if we need the pipe A quirk it must be always on */
1059 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1060 state = true;
1061
1062 if (!intel_display_power_enabled(dev_priv->dev,
1063 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
1064 cur_state = false;
1065 } else {
1066 reg = PIPECONF(cpu_transcoder);
1067 val = I915_READ(reg);
1068 cur_state = !!(val & PIPECONF_ENABLE);
1069 }
1070
1071 if(cur_state != state)
1072 DRM_ERROR("pipe %c assertion failure (expected %s, current %s)\n",
1073 pipe_name(pipe), state_string(state), state_string(cur_state));
1074 }
1075
assert_plane(struct drm_i915_private * dev_priv,enum plane plane,bool state)1076 static void assert_plane(struct drm_i915_private *dev_priv,
1077 enum plane plane, bool state)
1078 {
1079 int reg;
1080 u32 val;
1081 bool cur_state;
1082
1083 reg = DSPCNTR(plane);
1084 val = I915_READ(reg);
1085 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1086 if(cur_state != state)
1087 DRM_ERROR("plane %c assertion failure, should be active but is disabled\n",
1088 plane_name(plane));
1089 }
1090
1091 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1092 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1093
assert_planes_disabled(struct drm_i915_private * dev_priv,enum pipe pipe)1094 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1095 enum pipe pipe)
1096 {
1097 struct drm_device *dev = dev_priv->dev;
1098 int reg, i;
1099 u32 val;
1100 int cur_pipe;
1101
1102 /* Planes are fixed to pipes on ILK+ */
1103 if (INTEL_INFO(dev)->gen >= 4) {
1104 reg = DSPCNTR(pipe);
1105 val = I915_READ(reg);
1106 if(val & DISPLAY_PLANE_ENABLE)
1107 DRM_ERROR("plane %c assertion failure, should be disabled but not\n",
1108 plane_name(pipe));
1109 return;
1110 }
1111
1112 /* Need to check both planes against the pipe */
1113 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
1114 reg = DSPCNTR(i);
1115 val = I915_READ(reg);
1116 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1117 DISPPLANE_SEL_PIPE_SHIFT;
1118 if((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe)
1119 DRM_ERROR("plane %c assertion failure, should be off on pipe %c but is still active\n",
1120 plane_name(i), pipe_name(pipe));
1121 }
1122 }
1123
assert_sprites_disabled(struct drm_i915_private * dev_priv,enum pipe pipe)1124 static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1125 enum pipe pipe)
1126 {
1127 struct drm_device *dev = dev_priv->dev;
1128 int reg, i;
1129 u32 val;
1130
1131 if (IS_VALLEYVIEW(dev)) {
1132 for (i = 0; i < dev_priv->num_plane; i++) {
1133 reg = SPCNTR(pipe, i);
1134 val = I915_READ(reg);
1135 if(val & SP_ENABLE)
1136 DRM_ERROR("sprite %c assertion failure, should be off on pipe %c but is still active\n",
1137 sprite_name(pipe, i), pipe_name(pipe));
1138 }
1139 } else if (INTEL_INFO(dev)->gen >= 7) {
1140 reg = SPRCTL(pipe);
1141 val = I915_READ(reg);
1142 if(val & SPRITE_ENABLE)
1143 DRM_ERROR("sprite %c assertion failure, should be off on pipe %c but is still active\n",
1144 plane_name(pipe), pipe_name(pipe));
1145 } else if (INTEL_INFO(dev)->gen >= 5) {
1146 reg = DVSCNTR(pipe);
1147 val = I915_READ(reg);
1148 if(val & DVS_ENABLE)
1149 DRM_ERROR("sprite %c assertion failure, should be off on pipe %c but is still active\n",
1150 plane_name(pipe), pipe_name(pipe));
1151 }
1152 }
1153
assert_pch_refclk_enabled(struct drm_i915_private * dev_priv)1154 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1155 {
1156 u32 val;
1157 bool enabled;
1158
1159 if (HAS_PCH_LPT(dev_priv->dev)) {
1160 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1161 return;
1162 }
1163
1164 val = I915_READ(PCH_DREF_CONTROL);
1165 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1166 DREF_SUPERSPREAD_SOURCE_MASK));
1167 if(!enabled)
1168 DRM_ERROR("PCH refclk assertion failure, should be active but is disabled\n");
1169 }
1170
assert_pch_transcoder_disabled(struct drm_i915_private * dev_priv,enum pipe pipe)1171 static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1172 enum pipe pipe)
1173 {
1174 int reg;
1175 u32 val;
1176 bool enabled;
1177
1178 reg = PCH_TRANSCONF(pipe);
1179 val = I915_READ(reg);
1180 enabled = !!(val & TRANS_ENABLE);
1181 if(enabled)
1182 DRM_ERROR("transcoder assertion failed, should be off on pipe %c but is still active\n",
1183 pipe_name(pipe));
1184 }
1185
dp_pipe_enabled(struct drm_i915_private * dev_priv,enum pipe pipe,u32 port_sel,u32 val)1186 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1187 enum pipe pipe, u32 port_sel, u32 val)
1188 {
1189 if ((val & DP_PORT_EN) == 0)
1190 return false;
1191
1192 if (HAS_PCH_CPT(dev_priv->dev)) {
1193 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1194 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1195 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1196 return false;
1197 } else {
1198 if ((val & DP_PIPE_MASK) != (pipe << 30))
1199 return false;
1200 }
1201 return true;
1202 }
1203
hdmi_pipe_enabled(struct drm_i915_private * dev_priv,enum pipe pipe,u32 val)1204 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, u32 val)
1206 {
1207 if ((val & SDVO_ENABLE) == 0)
1208 return false;
1209
1210 if (HAS_PCH_CPT(dev_priv->dev)) {
1211 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1212 return false;
1213 } else {
1214 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1215 return false;
1216 }
1217 return true;
1218 }
1219
lvds_pipe_enabled(struct drm_i915_private * dev_priv,enum pipe pipe,u32 val)1220 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1221 enum pipe pipe, u32 val)
1222 {
1223 if ((val & LVDS_PORT_EN) == 0)
1224 return false;
1225
1226 if (HAS_PCH_CPT(dev_priv->dev)) {
1227 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1228 return false;
1229 } else {
1230 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1231 return false;
1232 }
1233 return true;
1234 }
1235
adpa_pipe_enabled(struct drm_i915_private * dev_priv,enum pipe pipe,u32 val)1236 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1237 enum pipe pipe, u32 val)
1238 {
1239 if ((val & ADPA_DAC_ENABLE) == 0)
1240 return false;
1241 if (HAS_PCH_CPT(dev_priv->dev)) {
1242 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1243 return false;
1244 } else {
1245 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1246 return false;
1247 }
1248 return true;
1249 }
1250
assert_pch_dp_disabled(struct drm_i915_private * dev_priv,enum pipe pipe,int reg,u32 port_sel)1251 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1252 enum pipe pipe, int reg, u32 port_sel)
1253 {
1254 u32 val = I915_READ(reg);
1255 if(dp_pipe_enabled(dev_priv, pipe, port_sel, val))
1256 DRM_ERROR("PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1257 reg, pipe_name(pipe));
1258
1259 if (HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1260 && (val & DP_PIPEB_SELECT))
1261 DRM_ERROR("IBX PCH dp port still using transcoder B\n");
1262 }
1263
assert_pch_hdmi_disabled(struct drm_i915_private * dev_priv,enum pipe pipe,int reg)1264 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1265 enum pipe pipe, int reg)
1266 {
1267 u32 val = I915_READ(reg);
1268 if(hdmi_pipe_enabled(dev_priv, pipe, val))
1269 DRM_ERROR("PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1270 reg, pipe_name(pipe));
1271
1272 if (HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
1273 && (val & SDVO_PIPE_B_SELECT))
1274 DRM_ERROR("IBX PCH hdmi port still using transcoder B\n");
1275 }
1276
assert_pch_ports_disabled(struct drm_i915_private * dev_priv,enum pipe pipe)1277 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1278 enum pipe pipe)
1279 {
1280 int reg;
1281 u32 val;
1282
1283 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1284 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1285 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1286
1287 reg = PCH_ADPA;
1288 val = I915_READ(reg);
1289 if(adpa_pipe_enabled(dev_priv, pipe, val))
1290 DRM_ERROR("PCH VGA enabled on transcoder %c, should be disabled\n",
1291 pipe_name(pipe));
1292
1293 reg = PCH_LVDS;
1294 val = I915_READ(reg);
1295 if(lvds_pipe_enabled(dev_priv, pipe, val))
1296 DRM_ERROR("PCH LVDS enabled on transcoder %c, should be disabled\n",
1297 pipe_name(pipe));
1298
1299 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1300 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1301 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
1302 }
1303
1304 /**
1305 * intel_enable_pll - enable a PLL
1306 * @dev_priv: i915 private structure
1307 * @pipe: pipe PLL to enable
1308 *
1309 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1310 * make sure the PLL reg is writable first though, since the panel write
1311 * protect mechanism may be enabled.
1312 *
1313 * Note! This is for pre-ILK only.
1314 *
1315 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1316 */
intel_enable_pll(struct drm_i915_private * dev_priv,enum pipe pipe)1317 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1318 {
1319 int reg;
1320 u32 val;
1321
1322 assert_pipe_disabled(dev_priv, pipe);
1323
1324 /* No really, not for ILK+ */
1325 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1326
1327 /* PLL is protected by panel, make sure we can write it */
1328 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1329 assert_panel_unlocked(dev_priv, pipe);
1330
1331 reg = DPLL(pipe);
1332 val = I915_READ(reg);
1333 val |= DPLL_VCO_ENABLE;
1334
1335 /* We do this three times for luck */
1336 I915_WRITE(reg, val);
1337 POSTING_READ(reg);
1338 udelay(150); /* wait for warmup */
1339 I915_WRITE(reg, val);
1340 POSTING_READ(reg);
1341 udelay(150); /* wait for warmup */
1342 I915_WRITE(reg, val);
1343 POSTING_READ(reg);
1344 udelay(150); /* wait for warmup */
1345 }
1346
1347 /**
1348 * intel_disable_pll - disable a PLL
1349 * @dev_priv: i915 private structure
1350 * @pipe: pipe PLL to disable
1351 *
1352 * Disable the PLL for @pipe, making sure the pipe is off first.
1353 *
1354 * Note! This is for pre-ILK only.
1355 */
intel_disable_pll(struct drm_i915_private * dev_priv,enum pipe pipe)1356 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1357 {
1358 int reg;
1359 u32 val;
1360
1361 /* Don't disable pipe A or pipe A PLLs if needed */
1362 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1363 return;
1364
1365 /* Make sure the pipe isn't still relying on us */
1366 assert_pipe_disabled(dev_priv, pipe);
1367
1368 reg = DPLL(pipe);
1369 val = I915_READ(reg);
1370 val &= ~DPLL_VCO_ENABLE;
1371 I915_WRITE(reg, val);
1372 POSTING_READ(reg);
1373 }
1374
vlv_wait_port_ready(struct drm_i915_private * dev_priv,int port)1375 void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1376 {
1377 u32 port_mask;
1378
1379 if (!port)
1380 port_mask = DPLL_PORTB_READY_MASK;
1381 else
1382 port_mask = DPLL_PORTC_READY_MASK;
1383
1384 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1385 DRM_ERROR("timed out waiting for port %c ready: 0x%08x\n",
1386 'B' + port, I915_READ(DPLL(0)));
1387 }
1388
1389 /**
1390 * ironlake_enable_pch_pll - enable PCH PLL
1391 * @dev_priv: i915 private structure
1392 * @pipe: pipe PLL to enable
1393 *
1394 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1395 * drives the transcoder clock.
1396 */
ironlake_enable_shared_dpll(struct intel_crtc * crtc)1397 static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
1398 {
1399 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1400 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1401
1402 /* PCH PLLs only available on ILK, SNB and IVB */
1403 BUG_ON(dev_priv->info->gen < 5);
1404 if (pll == NULL) {
1405 DRM_ERROR("pll is NULL");
1406 return;
1407 }
1408 if (pll->refcount == 0) {
1409 DRM_ERROR("pll refcount equal to 0");
1410 return;
1411 }
1412
1413 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1414 pll->name, pll->active, pll->on,
1415 crtc->base.base.id);
1416
1417 if (pll->active++) {
1418 WARN_ON(!pll->on);
1419 assert_shared_dpll_enabled(dev_priv, pll);
1420 return;
1421 }
1422 WARN_ON(pll->on);
1423
1424 DRM_DEBUG_KMS("enabling %s\n", pll->name);
1425 pll->enable(dev_priv, pll);
1426 pll->on = true;
1427 }
1428
intel_disable_shared_dpll(struct intel_crtc * crtc)1429 static void intel_disable_shared_dpll(struct intel_crtc *crtc)
1430 {
1431 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1432 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1433
1434 /* PCH only available on ILK+ */
1435 BUG_ON(dev_priv->info->gen < 5);
1436 if (pll == NULL) {
1437 DRM_ERROR("pll is NULL");
1438 return;
1439 }
1440
1441 if (pll->refcount == 0) {
1442 DRM_ERROR("pll refcount equal to 0");
1443 return;
1444 }
1445
1446 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1447 pll->name, pll->active, pll->on,
1448 crtc->base.base.id);
1449
1450 if ((pll->active == 0)) {
1451 assert_shared_dpll_disabled(dev_priv, pll);
1452 return;
1453 }
1454
1455 assert_shared_dpll_enabled(dev_priv, pll);
1456 WARN_ON(!pll->on);
1457 if (--pll->active)
1458 return;
1459
1460 DRM_DEBUG_KMS("disabling %s\n", pll->name);
1461 pll->disable(dev_priv, pll);
1462 pll->on = false;
1463 }
1464
ironlake_enable_pch_transcoder(struct drm_i915_private * dev_priv,enum pipe pipe)1465 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1466 enum pipe pipe)
1467 {
1468 struct drm_device *dev = dev_priv->dev;
1469 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1471 uint32_t reg, val, pipeconf_val;
1472
1473 /* PCH only available on ILK+ */
1474 BUG_ON(dev_priv->info->gen < 5);
1475
1476 /* Make sure PCH DPLL is enabled */
1477 assert_shared_dpll_enabled(dev_priv,
1478 intel_crtc_to_shared_dpll(intel_crtc));
1479
1480 /* FDI must be feeding us bits for PCH ports */
1481 assert_fdi_tx_enabled(dev_priv, pipe);
1482 assert_fdi_rx_enabled(dev_priv, pipe);
1483
1484 if (HAS_PCH_CPT(dev)) {
1485 /* Workaround: Set the timing override bit before enabling the
1486 * pch transcoder. */
1487 reg = TRANS_CHICKEN2(pipe);
1488 val = I915_READ(reg);
1489 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1490 I915_WRITE(reg, val);
1491 }
1492
1493 reg = PCH_TRANSCONF(pipe);
1494 val = I915_READ(reg);
1495 pipeconf_val = I915_READ(PIPECONF(pipe));
1496
1497 if (HAS_PCH_IBX(dev_priv->dev)) {
1498 /*
1499 * make the BPC in transcoder be consistent with
1500 * that in pipeconf reg.
1501 */
1502 val &= ~PIPECONF_BPC_MASK;
1503 val |= pipeconf_val & PIPECONF_BPC_MASK;
1504 }
1505
1506 val &= ~TRANS_INTERLACE_MASK;
1507 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1508 if (HAS_PCH_IBX(dev_priv->dev) &&
1509 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1510 val |= TRANS_LEGACY_INTERLACED_ILK;
1511 else
1512 val |= TRANS_INTERLACED;
1513 else
1514 val |= TRANS_PROGRESSIVE;
1515
1516 I915_WRITE(reg, val | TRANS_ENABLE);
1517 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1518 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
1519 }
1520
lpt_enable_pch_transcoder(struct drm_i915_private * dev_priv,enum transcoder cpu_transcoder)1521 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1522 enum transcoder cpu_transcoder)
1523 {
1524 u32 val, pipeconf_val;
1525
1526 /* PCH only available on ILK+ */
1527 BUG_ON(dev_priv->info->gen < 5);
1528
1529 /* FDI must be feeding us bits for PCH ports */
1530 assert_fdi_tx_enabled(dev_priv, (enum pipe)cpu_transcoder);
1531 assert_fdi_rx_enabled(dev_priv, (enum pipe)TRANSCODER_A);
1532
1533 /* Workaround: set timing override bit. */
1534 val = I915_READ(_TRANSA_CHICKEN2);
1535 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1536 I915_WRITE(_TRANSA_CHICKEN2, val);
1537
1538 val = TRANS_ENABLE;
1539 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1540
1541 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1542 PIPECONF_INTERLACED_ILK)
1543 val |= TRANS_INTERLACED;
1544 else
1545 val |= TRANS_PROGRESSIVE;
1546
1547 I915_WRITE(LPT_TRANSCONF, val);
1548 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
1549 DRM_ERROR("Failed to enable PCH transcoder\n");
1550 }
1551
ironlake_disable_pch_transcoder(struct drm_i915_private * dev_priv,enum pipe pipe)1552 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1553 enum pipe pipe)
1554 {
1555 struct drm_device *dev = dev_priv->dev;
1556 uint32_t reg, val;
1557
1558 /* FDI relies on the transcoder */
1559 assert_fdi_tx_disabled(dev_priv, pipe);
1560 assert_fdi_rx_disabled(dev_priv, pipe);
1561
1562 /* Ports must be off as well */
1563 assert_pch_ports_disabled(dev_priv, pipe);
1564
1565 reg = PCH_TRANSCONF(pipe);
1566 val = I915_READ(reg);
1567 val &= ~TRANS_ENABLE;
1568 I915_WRITE(reg, val);
1569 /* wait for PCH transcoder off, transcoder state */
1570 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1571 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
1572
1573 if (!HAS_PCH_IBX(dev)) {
1574 /* Workaround: Clear the timing override chicken bit again. */
1575 reg = TRANS_CHICKEN2(pipe);
1576 val = I915_READ(reg);
1577 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1578 I915_WRITE(reg, val);
1579 }
1580 }
1581
lpt_disable_pch_transcoder(struct drm_i915_private * dev_priv)1582 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1583 {
1584 u32 val;
1585
1586 val = I915_READ(LPT_TRANSCONF);
1587 val &= ~TRANS_ENABLE;
1588 I915_WRITE(LPT_TRANSCONF, val);
1589 /* wait for PCH transcoder off, transcoder state */
1590 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
1591 DRM_ERROR("Failed to disable PCH transcoder\n");
1592
1593 /* Workaround: clear timing override bit. */
1594 val = I915_READ(_TRANSA_CHICKEN2);
1595 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1596 I915_WRITE(_TRANSA_CHICKEN2, val);
1597 }
1598
1599 /**
1600 * intel_enable_pipe - enable a pipe, asserting requirements
1601 * @dev_priv: i915 private structure
1602 * @pipe: pipe to enable
1603 * @pch_port: on ILK+, is this pipe driving a PCH port or not
1604 *
1605 * Enable @pipe, making sure that various hardware specific requirements
1606 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1607 *
1608 * @pipe should be %PIPE_A or %PIPE_B.
1609 *
1610 * Will wait until the pipe is actually running (i.e. first vblank) before
1611 * returning.
1612 */
intel_enable_pipe(struct drm_i915_private * dev_priv,enum pipe pipe,bool pch_port)1613 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1614 bool pch_port)
1615 {
1616 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1617 pipe);
1618 enum pipe pch_transcoder;
1619 int reg;
1620 u32 val;
1621
1622 assert_planes_disabled(dev_priv, pipe);
1623 assert_sprites_disabled(dev_priv, pipe);
1624
1625 if (HAS_PCH_LPT(dev_priv->dev))
1626 pch_transcoder = (enum pipe)TRANSCODER_A;
1627 else
1628 pch_transcoder = pipe;
1629
1630 /*
1631 * A pipe without a PLL won't actually be able to drive bits from
1632 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1633 * need the check.
1634 */
1635 if (!HAS_PCH_SPLIT(dev_priv->dev))
1636 assert_pll_enabled(dev_priv, pipe);
1637 else {
1638 if (pch_port) {
1639 /* if driving the PCH, we need FDI enabled */
1640 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1641 assert_fdi_tx_pll_enabled(dev_priv,
1642 (enum pipe) cpu_transcoder);
1643 }
1644 /* FIXME: assert CPU port conditions for SNB+ */
1645 }
1646
1647 reg = PIPECONF(cpu_transcoder);
1648 val = I915_READ(reg);
1649 if (val & PIPECONF_ENABLE)
1650 return;
1651
1652 I915_WRITE(reg, val | PIPECONF_ENABLE);
1653 intel_wait_for_vblank(dev_priv->dev, pipe);
1654 }
1655
1656 /**
1657 * intel_disable_pipe - disable a pipe, asserting requirements
1658 * @dev_priv: i915 private structure
1659 * @pipe: pipe to disable
1660 *
1661 * Disable @pipe, making sure that various hardware specific requirements
1662 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1663 *
1664 * @pipe should be %PIPE_A or %PIPE_B.
1665 *
1666 * Will wait until the pipe has shut down before returning.
1667 */
intel_disable_pipe(struct drm_i915_private * dev_priv,enum pipe pipe)1668 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1669 enum pipe pipe)
1670 {
1671 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1672 pipe);
1673 int reg;
1674 u32 val;
1675
1676 /*
1677 * Make sure planes won't keep trying to pump pixels to us,
1678 * or we might hang the display.
1679 */
1680 assert_planes_disabled(dev_priv, pipe);
1681 assert_sprites_disabled(dev_priv, pipe);
1682
1683 /* Don't disable pipe A or pipe A PLLs if needed */
1684 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1685 return;
1686
1687 reg = PIPECONF(cpu_transcoder);
1688 val = I915_READ(reg);
1689 if ((val & PIPECONF_ENABLE) == 0)
1690 return;
1691
1692 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1693 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1694 }
1695
1696 /*
1697 * Plane regs are double buffered, going from enabled->disabled needs a
1698 * trigger in order to latch. The display address reg provides this.
1699 */
intel_flush_display_plane(struct drm_i915_private * dev_priv,enum plane plane)1700 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1701 enum plane plane)
1702 {
1703 if (dev_priv->info->gen >= 4)
1704 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1705 else
1706 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1707 }
1708
1709 /**
1710 * intel_enable_plane - enable a display plane on a given pipe
1711 * @dev_priv: i915 private structure
1712 * @plane: plane to enable
1713 * @pipe: pipe being fed
1714 *
1715 * Enable @plane on @pipe, making sure that @pipe is running first.
1716 */
intel_enable_plane(struct drm_i915_private * dev_priv,enum plane plane,enum pipe pipe)1717 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1718 enum plane plane, enum pipe pipe)
1719 {
1720 int reg;
1721 u32 val;
1722
1723 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1724 assert_pipe_enabled(dev_priv, pipe);
1725
1726 reg = DSPCNTR(plane);
1727 val = I915_READ(reg);
1728 if (val & DISPLAY_PLANE_ENABLE)
1729 return;
1730
1731 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1732 intel_flush_display_plane(dev_priv, plane);
1733 intel_wait_for_vblank(dev_priv->dev, pipe);
1734 }
1735
1736 /**
1737 * intel_disable_plane - disable a display plane
1738 * @dev_priv: i915 private structure
1739 * @plane: plane to disable
1740 * @pipe: pipe consuming the data
1741 *
1742 * Disable @plane; should be an independent operation.
1743 */
intel_disable_plane(struct drm_i915_private * dev_priv,enum plane plane,enum pipe pipe)1744 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1745 enum plane plane, enum pipe pipe)
1746 {
1747 int reg;
1748 u32 val;
1749
1750 reg = DSPCNTR(plane);
1751 val = I915_READ(reg);
1752 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1753 return;
1754
1755 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1756 intel_flush_display_plane(dev_priv, plane);
1757 intel_wait_for_vblank(dev_priv->dev, pipe);
1758 }
1759
need_vtd_wa(struct drm_device * dev)1760 static bool need_vtd_wa(struct drm_device *dev)
1761 {
1762 #ifdef CONFIG_INTEL_IOMMU
1763 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1764 return true;
1765 #endif
1766 return false;
1767 }
1768
1769 int
intel_pin_and_fence_fb_obj(struct drm_device * dev,struct drm_i915_gem_object * obj,struct intel_ring_buffer * pipelined)1770 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1771 struct drm_i915_gem_object *obj,
1772 struct intel_ring_buffer *pipelined)
1773 {
1774 struct drm_i915_private *dev_priv = dev->dev_private;
1775 u32 alignment;
1776 int ret;
1777
1778 switch (obj->tiling_mode) {
1779 case I915_TILING_NONE:
1780 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1781 alignment = 128 * 1024;
1782 else if (INTEL_INFO(dev)->gen >= 4)
1783 alignment = 4 * 1024;
1784 else
1785 alignment = 64 * 1024;
1786 break;
1787 case I915_TILING_X:
1788 /* pin() will align the object as required by fence */
1789 alignment = 0;
1790 break;
1791 case I915_TILING_Y:
1792 /* Despite that we check this in framebuffer_init userspace can
1793 * screw us over and change the tiling after the fact. Only
1794 * pinned buffers can't change their tiling. */
1795 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
1796 return -EINVAL;
1797 default:
1798 BUG();
1799 return -EINVAL;
1800 }
1801
1802 /* Note that the w/a also requires 64 PTE of padding following the
1803 * bo. We currently fill all unused PTE with the shadow page and so
1804 * we should always have valid PTE following the scanout preventing
1805 * the VT-d warning.
1806 */
1807 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1808 alignment = 256 * 1024;
1809
1810 dev_priv->mm.interruptible = false;
1811 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1812 if (ret)
1813 goto err_interruptible;
1814
1815 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1816 * fence, whereas 965+ only requires a fence if using
1817 * framebuffer compression. For simplicity, we always install
1818 * a fence as the cost is not that onerous.
1819 */
1820 ret = i915_gem_object_get_fence(obj);
1821 if (ret)
1822 goto err_unpin;
1823
1824 i915_gem_object_pin_fence(obj);
1825
1826 dev_priv->mm.interruptible = true;
1827 return 0;
1828
1829 err_unpin:
1830 i915_gem_object_unpin(obj);
1831 err_interruptible:
1832 dev_priv->mm.interruptible = true;
1833 return ret;
1834 }
1835
intel_unpin_fb_obj(struct drm_i915_gem_object * obj)1836 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1837 {
1838 i915_gem_object_unpin_fence(obj);
1839 i915_gem_object_unpin(obj);
1840 }
1841
1842 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1843 * is assumed to be a power-of-two. */
intel_gen4_compute_page_offset(int * x,int * y,unsigned int tiling_mode,unsigned int cpp,unsigned int pitch)1844 unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1845 unsigned int tiling_mode,
1846 unsigned int cpp,
1847 unsigned int pitch)
1848 {
1849 if (tiling_mode != I915_TILING_NONE) {
1850 unsigned int tile_rows, tiles;
1851
1852 tile_rows = *y / 8;
1853 *y %= 8;
1854
1855 tiles = *x / (512/cpp);
1856 *x %= 512/cpp;
1857
1858 return tile_rows * pitch * 8 + tiles * 4096;
1859 } else {
1860 unsigned int offset;
1861
1862 offset = *y * pitch + *x * cpp;
1863 *y = 0;
1864 *x = (offset & 4095) / cpp;
1865 return offset & -4096;
1866 }
1867 }
1868
i9xx_update_plane(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y)1869 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1870 int x, int y)
1871 {
1872 struct drm_device *dev = crtc->dev;
1873 struct drm_i915_private *dev_priv = dev->dev_private;
1874 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1875 struct intel_framebuffer *intel_fb;
1876 struct drm_i915_gem_object *obj;
1877 int plane = intel_crtc->plane;
1878 unsigned long linear_offset;
1879 u32 dspcntr;
1880 u32 reg;
1881
1882 switch (plane) {
1883 case 0:
1884 case 1:
1885 break;
1886 default:
1887 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1888 return -EINVAL;
1889 }
1890
1891 intel_fb = to_intel_framebuffer(fb);
1892 obj = intel_fb->obj;
1893
1894 reg = DSPCNTR(plane);
1895 dspcntr = I915_READ(reg);
1896 /* Mask out pixel format bits in case we change it */
1897 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1898 switch (fb->pixel_format) {
1899 case DRM_FORMAT_C8:
1900 dspcntr |= DISPPLANE_8BPP;
1901 break;
1902 case DRM_FORMAT_XRGB1555:
1903 case DRM_FORMAT_ARGB1555:
1904 dspcntr |= DISPPLANE_BGRX555;
1905 break;
1906 case DRM_FORMAT_RGB565:
1907 dspcntr |= DISPPLANE_BGRX565;
1908 break;
1909 case DRM_FORMAT_XRGB8888:
1910 case DRM_FORMAT_ARGB8888:
1911 dspcntr |= DISPPLANE_BGRX888;
1912 break;
1913 case DRM_FORMAT_XBGR8888:
1914 case DRM_FORMAT_ABGR8888:
1915 dspcntr |= DISPPLANE_RGBX888;
1916 break;
1917 case DRM_FORMAT_XRGB2101010:
1918 case DRM_FORMAT_ARGB2101010:
1919 dspcntr |= DISPPLANE_BGRX101010;
1920 break;
1921 case DRM_FORMAT_XBGR2101010:
1922 case DRM_FORMAT_ABGR2101010:
1923 dspcntr |= DISPPLANE_RGBX101010;
1924 break;
1925 default:
1926 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
1927 return -EINVAL;
1928 }
1929
1930 if (INTEL_INFO(dev)->gen >= 4) {
1931 if (obj->tiling_mode != I915_TILING_NONE)
1932 dspcntr |= DISPPLANE_TILED;
1933 else
1934 dspcntr &= ~DISPPLANE_TILED;
1935 }
1936
1937 if (IS_G4X(dev))
1938 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1939
1940 I915_WRITE(reg, dspcntr);
1941
1942 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
1943
1944 if (INTEL_INFO(dev)->gen >= 4) {
1945 intel_crtc->dspaddr_offset =
1946 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1947 fb->bits_per_pixel / 8,
1948 fb->pitches[0]);
1949 linear_offset -= intel_crtc->dspaddr_offset;
1950 } else {
1951 intel_crtc->dspaddr_offset = linear_offset;
1952 }
1953
1954 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1955 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
1956 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
1957 if (INTEL_INFO(dev)->gen >= 4) {
1958 I915_MODIFY_DISPBASE(DSPSURF(plane),
1959 obj->gtt_offset + intel_crtc->dspaddr_offset);
1960 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1961 I915_WRITE(DSPLINOFF(plane), linear_offset);
1962 } else
1963 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
1964 POSTING_READ(reg);
1965
1966 return 0;
1967 }
1968
ironlake_update_plane(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y)1969 static int ironlake_update_plane(struct drm_crtc *crtc,
1970 struct drm_framebuffer *fb, int x, int y)
1971 {
1972 struct drm_device *dev = crtc->dev;
1973 struct drm_i915_private *dev_priv = dev->dev_private;
1974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1975 struct intel_framebuffer *intel_fb;
1976 struct drm_i915_gem_object *obj;
1977 int plane = intel_crtc->plane;
1978 unsigned long linear_offset;
1979 u32 dspcntr;
1980 u32 reg;
1981
1982 switch (plane) {
1983 case 0:
1984 case 1:
1985 case 2:
1986 break;
1987 default:
1988 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
1989 return -EINVAL;
1990 }
1991
1992 intel_fb = to_intel_framebuffer(fb);
1993 obj = intel_fb->obj;
1994
1995 reg = DSPCNTR(plane);
1996 dspcntr = I915_READ(reg);
1997 /* Mask out pixel format bits in case we change it */
1998 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1999 switch (fb->pixel_format) {
2000 case DRM_FORMAT_C8:
2001 dspcntr |= DISPPLANE_8BPP;
2002 break;
2003 case DRM_FORMAT_RGB565:
2004 dspcntr |= DISPPLANE_BGRX565;
2005 break;
2006 case DRM_FORMAT_XRGB8888:
2007 case DRM_FORMAT_ARGB8888:
2008 dspcntr |= DISPPLANE_BGRX888;
2009 break;
2010 case DRM_FORMAT_XBGR8888:
2011 case DRM_FORMAT_ABGR8888:
2012 dspcntr |= DISPPLANE_RGBX888;
2013 break;
2014 case DRM_FORMAT_XRGB2101010:
2015 case DRM_FORMAT_ARGB2101010:
2016 dspcntr |= DISPPLANE_BGRX101010;
2017 break;
2018 case DRM_FORMAT_XBGR2101010:
2019 case DRM_FORMAT_ABGR2101010:
2020 dspcntr |= DISPPLANE_RGBX101010;
2021 break;
2022 default:
2023 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2024 return -EINVAL;
2025 }
2026
2027 if (obj->tiling_mode != I915_TILING_NONE)
2028 dspcntr |= DISPPLANE_TILED;
2029 else
2030 dspcntr &= ~DISPPLANE_TILED;
2031
2032 /* must disable */
2033 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2034
2035 I915_WRITE(reg, dspcntr);
2036
2037 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2038 intel_crtc->dspaddr_offset =
2039 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2040 fb->bits_per_pixel / 8,
2041 fb->pitches[0]);
2042 linear_offset -= intel_crtc->dspaddr_offset;
2043
2044 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2045 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2046 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2047 I915_MODIFY_DISPBASE(DSPSURF(plane),
2048 obj->gtt_offset + intel_crtc->dspaddr_offset);
2049 if (IS_HASWELL(dev)) {
2050 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2051 } else {
2052 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2053 I915_WRITE(DSPLINOFF(plane), linear_offset);
2054 }
2055 POSTING_READ(reg);
2056
2057 return 0;
2058 }
2059
2060 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2061 static int
intel_pipe_set_base_atomic(struct drm_crtc * crtc,struct drm_framebuffer * fb,int x,int y,enum mode_set_atomic state)2062 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2063 int x, int y, enum mode_set_atomic state)
2064 {
2065 struct drm_device *dev = crtc->dev;
2066 struct drm_i915_private *dev_priv = dev->dev_private;
2067
2068 if (dev_priv->display.disable_fbc)
2069 dev_priv->display.disable_fbc(dev);
2070 intel_increase_pllclock(crtc);
2071
2072 return dev_priv->display.update_plane(crtc, fb, x, y);
2073 }
2074
intel_display_handle_reset(struct drm_device * dev)2075 void intel_display_handle_reset(struct drm_device *dev)
2076 {
2077 struct drm_i915_private *dev_priv = dev->dev_private;
2078 struct drm_crtc *crtc;
2079
2080 /*
2081 * Flips in the rings have been nuked by the reset,
2082 * so complete all pending flips so that user space
2083 * will get its events and not get stuck.
2084 *
2085 * Also update the base address of all primary
2086 * planes to the the last fb to make sure we're
2087 * showing the correct fb after a reset.
2088 *
2089 * Need to make two loops over the crtcs so that we
2090 * don't try to grab a crtc mutex before the
2091 * pending_flip_queue really got woken up.
2092 */
2093
2094 list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
2095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2096 enum plane plane = intel_crtc->plane;
2097
2098 intel_prepare_page_flip(dev, plane);
2099 intel_finish_page_flip_plane(dev, plane);
2100 }
2101
2102 list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
2103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2104
2105 mutex_lock(&crtc->mutex);
2106 if (intel_crtc->active)
2107 dev_priv->display.update_plane(crtc, crtc->fb,
2108 crtc->x, crtc->y);
2109 mutex_unlock(&crtc->mutex);
2110 }
2111 }
2112
2113 static int
intel_finish_fb(struct drm_framebuffer * old_fb)2114 intel_finish_fb(struct drm_framebuffer *old_fb)
2115 {
2116 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2117 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2118 bool was_interruptible = dev_priv->mm.interruptible;
2119 int ret;
2120
2121 /* Big Hammer, we also need to ensure that any pending
2122 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2123 * current scanout is retired before unpinning the old
2124 * framebuffer.
2125 *
2126 * This should only fail upon a hung GPU, in which case we
2127 * can safely continue.
2128 */
2129 dev_priv->mm.interruptible = false;
2130 ret = i915_gem_object_finish_gpu(obj);
2131 dev_priv->mm.interruptible = was_interruptible;
2132
2133 return ret;
2134 }
2135
intel_crtc_update_sarea_pos(struct drm_crtc * crtc,int x,int y)2136 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2137 {
2138 struct drm_device *dev = crtc->dev;
2139 struct drm_i915_master_private *master_priv;
2140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2141
2142 if (!dev->primary->master)
2143 return;
2144
2145 master_priv = dev->primary->master->driver_priv;
2146 if (!master_priv->sarea_priv)
2147 return;
2148
2149 switch (intel_crtc->pipe) {
2150 case 0:
2151 master_priv->sarea_priv->pipeA_x = x;
2152 master_priv->sarea_priv->pipeA_y = y;
2153 break;
2154 case 1:
2155 master_priv->sarea_priv->pipeB_x = x;
2156 master_priv->sarea_priv->pipeB_y = y;
2157 break;
2158 default:
2159 break;
2160 }
2161 }
2162
2163 static int
intel_pipe_set_base(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * fb)2164 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2165 struct drm_framebuffer *fb)
2166 {
2167 struct drm_device *dev = crtc->dev;
2168 struct drm_i915_private *dev_priv = dev->dev_private;
2169 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2170 struct drm_framebuffer *old_fb;
2171 int ret;
2172
2173 /* no fb bound */
2174 if (!fb) {
2175 DRM_ERROR("No FB bound\n");
2176 return 0;
2177 }
2178
2179 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
2180 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2181 plane_name(intel_crtc->plane),
2182 INTEL_INFO(dev)->num_pipes);
2183 return -EINVAL;
2184 }
2185
2186 mutex_lock(&dev->struct_mutex);
2187 ret = intel_pin_and_fence_fb_obj(dev,
2188 to_intel_framebuffer(fb)->obj,
2189 NULL);
2190 if (ret != 0) {
2191 mutex_unlock(&dev->struct_mutex);
2192 DRM_ERROR("pin & fence failed\n");
2193 return ret;
2194 }
2195
2196 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2197 if (ret) {
2198 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2199 mutex_unlock(&dev->struct_mutex);
2200 DRM_ERROR("failed to update base address\n");
2201 return ret;
2202 }
2203
2204 old_fb = crtc->fb;
2205 crtc->fb = fb;
2206 crtc->x = x;
2207 crtc->y = y;
2208
2209 if (old_fb) {
2210 if (intel_crtc->active && old_fb != fb)
2211 intel_wait_for_vblank(dev, intel_crtc->pipe);
2212 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2213 }
2214
2215 intel_update_fbc(dev);
2216 mutex_unlock(&dev->struct_mutex);
2217
2218 intel_crtc_update_sarea_pos(crtc, x, y);
2219
2220 return 0;
2221 }
2222
intel_fdi_normal_train(struct drm_crtc * crtc)2223 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2224 {
2225 struct drm_device *dev = crtc->dev;
2226 struct drm_i915_private *dev_priv = dev->dev_private;
2227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2228 int pipe = intel_crtc->pipe;
2229 u32 reg, temp;
2230
2231 /* enable normal train */
2232 reg = FDI_TX_CTL(pipe);
2233 temp = I915_READ(reg);
2234 if (IS_IVYBRIDGE(dev)) {
2235 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2236 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2237 } else {
2238 temp &= ~FDI_LINK_TRAIN_NONE;
2239 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2240 }
2241 I915_WRITE(reg, temp);
2242
2243 reg = FDI_RX_CTL(pipe);
2244 temp = I915_READ(reg);
2245 if (HAS_PCH_CPT(dev)) {
2246 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2247 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2248 } else {
2249 temp &= ~FDI_LINK_TRAIN_NONE;
2250 temp |= FDI_LINK_TRAIN_NONE;
2251 }
2252 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2253
2254 /* wait one idle pattern time */
2255 POSTING_READ(reg);
2256 udelay(1000);
2257
2258 /* IVB wants error correction enabled */
2259 if (IS_IVYBRIDGE(dev))
2260 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2261 FDI_FE_ERRC_ENABLE);
2262 }
2263
pipe_has_enabled_pch(struct intel_crtc * intel_crtc)2264 static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2265 {
2266 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2267 }
2268
ivb_modeset_global_resources(struct drm_device * dev)2269 static void ivb_modeset_global_resources(struct drm_device *dev)
2270 {
2271 struct drm_i915_private *dev_priv = dev->dev_private;
2272 struct intel_crtc *pipe_B_crtc =
2273 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2274 struct intel_crtc *pipe_C_crtc =
2275 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2276 uint32_t temp;
2277
2278 /*
2279 * When everything is off disable fdi C so that we could enable fdi B
2280 * with all lanes. Note that we don't care about enabled pipes without
2281 * an enabled pch encoder.
2282 */
2283 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2284 !pipe_has_enabled_pch(pipe_C_crtc)) {
2285 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2286 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2287
2288 temp = I915_READ(SOUTH_CHICKEN1);
2289 temp &= ~FDI_BC_BIFURCATION_SELECT;
2290 DRM_DEBUG_KMS("disabling fdi C rx\n");
2291 I915_WRITE(SOUTH_CHICKEN1, temp);
2292 }
2293 }
2294
2295 /* The FDI link training functions for ILK/Ibexpeak. */
ironlake_fdi_link_train(struct drm_crtc * crtc)2296 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2297 {
2298 struct drm_device *dev = crtc->dev;
2299 struct drm_i915_private *dev_priv = dev->dev_private;
2300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2301 int pipe = intel_crtc->pipe;
2302 int plane = intel_crtc->plane;
2303 u32 reg, temp, tries;
2304
2305 /* FDI needs bits from pipe & plane first */
2306 assert_pipe_enabled(dev_priv, pipe);
2307 assert_plane_enabled(dev_priv, plane);
2308
2309 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2310 for train result */
2311 reg = FDI_RX_IMR(pipe);
2312 temp = I915_READ(reg);
2313 temp &= ~FDI_RX_SYMBOL_LOCK;
2314 temp &= ~FDI_RX_BIT_LOCK;
2315 I915_WRITE(reg, temp);
2316 POSTING_READ(reg);
2317 udelay(150);
2318
2319 /* enable CPU FDI TX and PCH FDI RX */
2320 reg = FDI_TX_CTL(pipe);
2321 temp = I915_READ(reg);
2322 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2323 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2324 temp &= ~FDI_LINK_TRAIN_NONE;
2325 temp |= FDI_LINK_TRAIN_PATTERN_1;
2326 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2327
2328 reg = FDI_RX_CTL(pipe);
2329 temp = I915_READ(reg);
2330 temp &= ~FDI_LINK_TRAIN_NONE;
2331 temp |= FDI_LINK_TRAIN_PATTERN_1;
2332 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2333
2334 POSTING_READ(reg);
2335 udelay(150);
2336
2337 /* Ironlake workaround, enable clock pointer after FDI enable*/
2338 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2339 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2340 FDI_RX_PHASE_SYNC_POINTER_EN);
2341
2342 reg = FDI_RX_IIR(pipe);
2343 for (tries = 0; tries < 5; tries++) {
2344 temp = I915_READ(reg);
2345 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2346
2347 if ((temp & FDI_RX_BIT_LOCK)) {
2348 DRM_DEBUG_KMS("FDI train 1 done.\n");
2349 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2350 break;
2351 }
2352 }
2353 if (tries == 5)
2354 DRM_ERROR("FDI train 1 fail!\n");
2355
2356 /* Train 2 */
2357 reg = FDI_TX_CTL(pipe);
2358 temp = I915_READ(reg);
2359 temp &= ~FDI_LINK_TRAIN_NONE;
2360 temp |= FDI_LINK_TRAIN_PATTERN_2;
2361 I915_WRITE(reg, temp);
2362
2363 reg = FDI_RX_CTL(pipe);
2364 temp = I915_READ(reg);
2365 temp &= ~FDI_LINK_TRAIN_NONE;
2366 temp |= FDI_LINK_TRAIN_PATTERN_2;
2367 I915_WRITE(reg, temp);
2368
2369 POSTING_READ(reg);
2370 udelay(150);
2371
2372 reg = FDI_RX_IIR(pipe);
2373 for (tries = 0; tries < 5; tries++) {
2374 temp = I915_READ(reg);
2375 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2376
2377 if (temp & FDI_RX_SYMBOL_LOCK) {
2378 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2379 DRM_DEBUG_KMS("FDI train 2 done.\n");
2380 break;
2381 }
2382 }
2383 if (tries == 5)
2384 DRM_ERROR("FDI train 2 fail!\n");
2385
2386 DRM_DEBUG_KMS("FDI train done\n");
2387
2388 }
2389
2390 static const int snb_b_fdi_train_param [] = {
2391 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2392 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2393 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2394 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2395 };
2396
2397 /* The FDI link training functions for SNB/Cougarpoint. */
gen6_fdi_link_train(struct drm_crtc * crtc)2398 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2399 {
2400 struct drm_device *dev = crtc->dev;
2401 struct drm_i915_private *dev_priv = dev->dev_private;
2402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2403 int pipe = intel_crtc->pipe;
2404 u32 reg, temp, i, retry;
2405
2406 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2407 for train result */
2408 reg = FDI_RX_IMR(pipe);
2409 temp = I915_READ(reg);
2410 temp &= ~FDI_RX_SYMBOL_LOCK;
2411 temp &= ~FDI_RX_BIT_LOCK;
2412 I915_WRITE(reg, temp);
2413
2414 POSTING_READ(reg);
2415 udelay(150);
2416
2417 /* enable CPU FDI TX and PCH FDI RX */
2418 reg = FDI_TX_CTL(pipe);
2419 temp = I915_READ(reg);
2420 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2421 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2422 temp &= ~FDI_LINK_TRAIN_NONE;
2423 temp |= FDI_LINK_TRAIN_PATTERN_1;
2424 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2425 /* SNB-B */
2426 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2427 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2428
2429 I915_WRITE(FDI_RX_MISC(pipe),
2430 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2431
2432 reg = FDI_RX_CTL(pipe);
2433 temp = I915_READ(reg);
2434 if (HAS_PCH_CPT(dev)) {
2435 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2436 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2437 } else {
2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_1;
2440 }
2441 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2442
2443 POSTING_READ(reg);
2444 udelay(150);
2445
2446 for (i = 0; i < 4; i++ ) {
2447 reg = FDI_TX_CTL(pipe);
2448 temp = I915_READ(reg);
2449 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2450 temp |= snb_b_fdi_train_param[i];
2451 I915_WRITE(reg, temp);
2452
2453 POSTING_READ(reg);
2454 udelay(500);
2455
2456 for (retry = 0; retry < 5; retry++) {
2457 reg = FDI_RX_IIR(pipe);
2458 temp = I915_READ(reg);
2459 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2460 if (temp & FDI_RX_BIT_LOCK) {
2461 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2462 DRM_DEBUG_KMS("FDI train 1 done.\n");
2463 break;
2464 }
2465 udelay(50);
2466 }
2467 if (retry < 5)
2468 break;
2469 }
2470 if (i == 4)
2471 DRM_ERROR("FDI train 1 fail!\n");
2472
2473 /* Train 2 */
2474 reg = FDI_TX_CTL(pipe);
2475 temp = I915_READ(reg);
2476 temp &= ~FDI_LINK_TRAIN_NONE;
2477 temp |= FDI_LINK_TRAIN_PATTERN_2;
2478 if (IS_GEN6(dev)) {
2479 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2480 /* SNB-B */
2481 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2482 }
2483 I915_WRITE(reg, temp);
2484
2485 reg = FDI_RX_CTL(pipe);
2486 temp = I915_READ(reg);
2487 if (HAS_PCH_CPT(dev)) {
2488 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2489 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2490 } else {
2491 temp &= ~FDI_LINK_TRAIN_NONE;
2492 temp |= FDI_LINK_TRAIN_PATTERN_2;
2493 }
2494 I915_WRITE(reg, temp);
2495
2496 POSTING_READ(reg);
2497 udelay(150);
2498
2499 for (i = 0; i < 4; i++ ) {
2500 reg = FDI_TX_CTL(pipe);
2501 temp = I915_READ(reg);
2502 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503 temp |= snb_b_fdi_train_param[i];
2504 I915_WRITE(reg, temp);
2505
2506 POSTING_READ(reg);
2507 udelay(500);
2508
2509 for (retry = 0; retry < 5; retry++) {
2510 reg = FDI_RX_IIR(pipe);
2511 temp = I915_READ(reg);
2512 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2513 if (temp & FDI_RX_SYMBOL_LOCK) {
2514 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2515 DRM_DEBUG_KMS("FDI train 2 done.\n");
2516 break;
2517 }
2518 udelay(50);
2519 }
2520 if (retry < 5)
2521 break;
2522 }
2523 if (i == 4)
2524 DRM_ERROR("FDI train 2 fail!\n");
2525
2526 DRM_DEBUG_KMS("FDI train done.\n");
2527 }
2528
2529 /* Manual link training for Ivy Bridge A0 parts */
ivb_manual_fdi_link_train(struct drm_crtc * crtc)2530 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2531 {
2532 struct drm_device *dev = crtc->dev;
2533 struct drm_i915_private *dev_priv = dev->dev_private;
2534 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2535 int pipe = intel_crtc->pipe;
2536 u32 reg, temp, i;
2537
2538 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2539 for train result */
2540 reg = FDI_RX_IMR(pipe);
2541 temp = I915_READ(reg);
2542 temp &= ~FDI_RX_SYMBOL_LOCK;
2543 temp &= ~FDI_RX_BIT_LOCK;
2544 I915_WRITE(reg, temp);
2545
2546 POSTING_READ(reg);
2547 udelay(150);
2548
2549 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2550 I915_READ(FDI_RX_IIR(pipe)));
2551
2552 /* enable CPU FDI TX and PCH FDI RX */
2553 reg = FDI_TX_CTL(pipe);
2554 temp = I915_READ(reg);
2555 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2556 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2557 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2558 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2559 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2560 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2561 temp |= FDI_COMPOSITE_SYNC;
2562 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2563
2564 I915_WRITE(FDI_RX_MISC(pipe),
2565 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2566
2567 reg = FDI_RX_CTL(pipe);
2568 temp = I915_READ(reg);
2569 temp &= ~FDI_LINK_TRAIN_AUTO;
2570 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2571 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2572 temp |= FDI_COMPOSITE_SYNC;
2573 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2574
2575 POSTING_READ(reg);
2576 udelay(150);
2577
2578 for (i = 0; i < 4; i++ ) {
2579 reg = FDI_TX_CTL(pipe);
2580 temp = I915_READ(reg);
2581 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2582 temp |= snb_b_fdi_train_param[i];
2583 I915_WRITE(reg, temp);
2584
2585 POSTING_READ(reg);
2586 udelay(500);
2587
2588 reg = FDI_RX_IIR(pipe);
2589 temp = I915_READ(reg);
2590 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2591
2592 if (temp & FDI_RX_BIT_LOCK ||
2593 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2594 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2595 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2596 break;
2597 }
2598 }
2599 if (i == 4)
2600 DRM_ERROR("FDI train 1 fail!\n");
2601
2602 /* Train 2 */
2603 reg = FDI_TX_CTL(pipe);
2604 temp = I915_READ(reg);
2605 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2606 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2607 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2608 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2609 I915_WRITE(reg, temp);
2610
2611 reg = FDI_RX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2614 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2615 I915_WRITE(reg, temp);
2616
2617 POSTING_READ(reg);
2618 udelay(150);
2619
2620 for (i = 0; i < 4; i++ ) {
2621 reg = FDI_TX_CTL(pipe);
2622 temp = I915_READ(reg);
2623 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2624 temp |= snb_b_fdi_train_param[i];
2625 I915_WRITE(reg, temp);
2626
2627 POSTING_READ(reg);
2628 udelay(500);
2629
2630 reg = FDI_RX_IIR(pipe);
2631 temp = I915_READ(reg);
2632 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2633
2634 if (temp & FDI_RX_SYMBOL_LOCK) {
2635 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2636 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2637 break;
2638 }
2639 }
2640 if (i == 4)
2641 DRM_ERROR("FDI train 2 fail!\n");
2642
2643 DRM_DEBUG_KMS("FDI train done.\n");
2644 }
2645
ironlake_fdi_pll_enable(struct intel_crtc * intel_crtc)2646 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2647 {
2648 struct drm_device *dev = intel_crtc->base.dev;
2649 struct drm_i915_private *dev_priv = dev->dev_private;
2650 int pipe = intel_crtc->pipe;
2651 u32 reg, temp;
2652
2653
2654 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2655 reg = FDI_RX_CTL(pipe);
2656 temp = I915_READ(reg);
2657 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2658 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2659 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2660 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2661
2662 POSTING_READ(reg);
2663 udelay(200);
2664
2665 /* Switch from Rawclk to PCDclk */
2666 temp = I915_READ(reg);
2667 I915_WRITE(reg, temp | FDI_PCDCLK);
2668
2669 POSTING_READ(reg);
2670 udelay(200);
2671
2672 /* Enable CPU FDI TX PLL, always on for Ironlake */
2673 reg = FDI_TX_CTL(pipe);
2674 temp = I915_READ(reg);
2675 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2676 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2677
2678 POSTING_READ(reg);
2679 udelay(100);
2680 }
2681 }
2682
ironlake_fdi_pll_disable(struct intel_crtc * intel_crtc)2683 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2684 {
2685 struct drm_device *dev = intel_crtc->base.dev;
2686 struct drm_i915_private *dev_priv = dev->dev_private;
2687 int pipe = intel_crtc->pipe;
2688 u32 reg, temp;
2689
2690 /* Switch from PCDclk to Rawclk */
2691 reg = FDI_RX_CTL(pipe);
2692 temp = I915_READ(reg);
2693 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2694
2695 /* Disable CPU FDI TX PLL */
2696 reg = FDI_TX_CTL(pipe);
2697 temp = I915_READ(reg);
2698 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2699
2700 POSTING_READ(reg);
2701 udelay(100);
2702
2703 reg = FDI_RX_CTL(pipe);
2704 temp = I915_READ(reg);
2705 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2706
2707 /* Wait for the clocks to turn off. */
2708 POSTING_READ(reg);
2709 udelay(100);
2710 }
2711
ironlake_fdi_disable(struct drm_crtc * crtc)2712 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2713 {
2714 struct drm_device *dev = crtc->dev;
2715 struct drm_i915_private *dev_priv = dev->dev_private;
2716 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2717 int pipe = intel_crtc->pipe;
2718 u32 reg, temp;
2719
2720 /* disable CPU FDI tx and PCH FDI rx */
2721 reg = FDI_TX_CTL(pipe);
2722 temp = I915_READ(reg);
2723 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2724 POSTING_READ(reg);
2725
2726 reg = FDI_RX_CTL(pipe);
2727 temp = I915_READ(reg);
2728 temp &= ~(0x7 << 16);
2729 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2730 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2731
2732 POSTING_READ(reg);
2733 udelay(100);
2734
2735 /* Ironlake workaround, disable clock pointer after downing FDI */
2736 if (HAS_PCH_IBX(dev)) {
2737 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2738 }
2739
2740 /* still set train pattern 1 */
2741 reg = FDI_TX_CTL(pipe);
2742 temp = I915_READ(reg);
2743 temp &= ~FDI_LINK_TRAIN_NONE;
2744 temp |= FDI_LINK_TRAIN_PATTERN_1;
2745 I915_WRITE(reg, temp);
2746
2747 reg = FDI_RX_CTL(pipe);
2748 temp = I915_READ(reg);
2749 if (HAS_PCH_CPT(dev)) {
2750 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2751 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2752 } else {
2753 temp &= ~FDI_LINK_TRAIN_NONE;
2754 temp |= FDI_LINK_TRAIN_PATTERN_1;
2755 }
2756 /* BPC in FDI rx is consistent with that in PIPECONF */
2757 temp &= ~(0x07 << 16);
2758 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
2759 I915_WRITE(reg, temp);
2760
2761 POSTING_READ(reg);
2762 udelay(100);
2763 }
2764
intel_crtc_has_pending_flip(struct drm_crtc * crtc)2765 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2766 {
2767 struct drm_device *dev = crtc->dev;
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2770 unsigned long flags;
2771 bool pending;
2772
2773 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2774 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
2775 return false;
2776
2777 spin_lock_irqsave(&dev->event_lock, flags);
2778 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2779 spin_unlock_irqrestore(&dev->event_lock, flags);
2780
2781 return pending;
2782 }
2783
intel_crtc_wait_for_pending_flips(struct drm_crtc * crtc)2784 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2785 {
2786 /* LINTED */
2787 int ret;
2788
2789 struct drm_device *dev = crtc->dev;
2790 struct drm_i915_private *dev_priv = dev->dev_private;
2791
2792 if (crtc->fb == NULL)
2793 return;
2794
2795 WARN_ON(mutex_is_locked(&dev_priv->pending_flip_queue.lock));
2796
2797 DRM_WAIT(ret, &dev_priv->pending_flip_queue,
2798 !intel_crtc_has_pending_flip(crtc));
2799
2800 mutex_lock(&dev->struct_mutex);
2801 intel_finish_fb(crtc->fb);
2802 mutex_unlock(&dev->struct_mutex);
2803 }
2804
2805 /* Program iCLKIP clock to the desired frequency */
lpt_program_iclkip(struct drm_crtc * crtc)2806 static void lpt_program_iclkip(struct drm_crtc *crtc)
2807 {
2808 struct drm_device *dev = crtc->dev;
2809 struct drm_i915_private *dev_priv = dev->dev_private;
2810 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2811 u32 temp;
2812
2813 mutex_lock(&dev_priv->dpio_lock);
2814
2815 /* It is necessary to ungate the pixclk gate prior to programming
2816 * the divisors, and gate it back when it is done.
2817 */
2818 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2819
2820 /* Disable SSCCTL */
2821 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2822 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2823 SBI_SSCCTL_DISABLE,
2824 SBI_ICLK);
2825
2826 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2827 if (crtc->mode.clock == 20000) {
2828 auxdiv = 1;
2829 divsel = 0x41;
2830 phaseinc = 0x20;
2831 } else {
2832 /* The iCLK virtual clock root frequency is in MHz,
2833 * but the crtc->mode.clock in in KHz. To get the divisors,
2834 * it is necessary to divide one by another, so we
2835 * convert the virtual clock precision to KHz here for higher
2836 * precision.
2837 */
2838 u32 iclk_virtual_root_freq = 172800 * 1000;
2839 u32 iclk_pi_range = 64;
2840 u32 desired_divisor, msb_divisor_value, pi_value;
2841
2842 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2843 msb_divisor_value = desired_divisor / iclk_pi_range;
2844 pi_value = desired_divisor % iclk_pi_range;
2845
2846 auxdiv = 0;
2847 divsel = msb_divisor_value - 2;
2848 phaseinc = pi_value;
2849 }
2850
2851 /* This should not happen with any sane values */
2852 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2853 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2854 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2855 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2856
2857 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2858 crtc->mode.clock,
2859 auxdiv,
2860 divsel,
2861 phasedir,
2862 phaseinc);
2863
2864 /* Program SSCDIVINTPHASE6 */
2865 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
2866 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2867 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2868 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2869 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2870 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2871 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2872 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
2873
2874 /* Program SSCAUXDIV */
2875 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
2876 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2877 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2878 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
2879
2880 /* Enable modulator and associated divider */
2881 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
2882 temp &= ~SBI_SSCCTL_DISABLE;
2883 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
2884
2885 /* Wait for initialization time */
2886 udelay(24);
2887
2888 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2889
2890 mutex_unlock(&dev_priv->dpio_lock);
2891 }
2892
ironlake_pch_transcoder_set_timings(struct intel_crtc * crtc,enum pipe pch_transcoder)2893 static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2894 enum pipe pch_transcoder)
2895 {
2896 struct drm_device *dev = crtc->base.dev;
2897 struct drm_i915_private *dev_priv = dev->dev_private;
2898 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2899
2900 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2901 I915_READ(HTOTAL(cpu_transcoder)));
2902 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2903 I915_READ(HBLANK(cpu_transcoder)));
2904 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2905 I915_READ(HSYNC(cpu_transcoder)));
2906
2907 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2908 I915_READ(VTOTAL(cpu_transcoder)));
2909 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2910 I915_READ(VBLANK(cpu_transcoder)));
2911 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2912 I915_READ(VSYNC(cpu_transcoder)));
2913 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2914 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2915 }
2916
2917 /*
2918 * Enable PCH resources required for PCH ports:
2919 * - PCH PLLs
2920 * - FDI training & RX/TX
2921 * - update transcoder timings
2922 * - DP transcoding bits
2923 * - transcoder
2924 */
ironlake_pch_enable(struct drm_crtc * crtc)2925 static void ironlake_pch_enable(struct drm_crtc *crtc)
2926 {
2927 struct drm_device *dev = crtc->dev;
2928 struct drm_i915_private *dev_priv = dev->dev_private;
2929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2930 int pipe = intel_crtc->pipe;
2931 u32 reg, temp;
2932
2933 assert_pch_transcoder_disabled(dev_priv, pipe);
2934
2935 /* Write the TU size bits before fdi link training, so that error
2936 * detection works. */
2937 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2938 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2939
2940 /* For PCH output, training FDI link */
2941 dev_priv->display.fdi_link_train(crtc);
2942
2943 /* XXX: pch pll's can be enabled any time before we enable the PCH
2944 * transcoder, and we actually should do this to not upset any PCH
2945 * transcoder that already use the clock when we share it.
2946 *
2947 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2948 * unconditionally resets the pll - we need that to have the right LVDS
2949 * enable sequence. */
2950 ironlake_enable_shared_dpll(intel_crtc);
2951
2952 if (HAS_PCH_CPT(dev)) {
2953 u32 sel;
2954
2955 temp = I915_READ(PCH_DPLL_SEL);
2956 temp |= TRANS_DPLL_ENABLE(pipe);
2957 sel = TRANS_DPLLB_SEL(pipe);
2958 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
2959 temp |= sel;
2960 else
2961 temp &= ~sel;
2962 I915_WRITE(PCH_DPLL_SEL, temp);
2963 }
2964
2965 /* set transcoder timing */
2966 assert_panel_unlocked(dev_priv, pipe);
2967 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
2968
2969 intel_fdi_normal_train(crtc);
2970
2971 /* For PCH DP, enable TRANS_DP_CTL */
2972 if (HAS_PCH_CPT(dev) &&
2973 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2974 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2975 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
2976 reg = TRANS_DP_CTL(pipe);
2977 temp = I915_READ(reg);
2978 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2979 TRANS_DP_SYNC_MASK |
2980 TRANS_DP_BPC_MASK);
2981 temp |= (TRANS_DP_OUTPUT_ENABLE |
2982 TRANS_DP_ENH_FRAMING);
2983 temp |= bpc << 9; /* same format but at 11:9 */
2984
2985 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2986 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2987 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2988 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2989
2990 switch (intel_trans_dp_port_sel(crtc)) {
2991 case PCH_DP_B:
2992 temp |= TRANS_DP_PORT_SEL_B;
2993 break;
2994 case PCH_DP_C:
2995 temp |= TRANS_DP_PORT_SEL_C;
2996 break;
2997 case PCH_DP_D:
2998 temp |= TRANS_DP_PORT_SEL_D;
2999 break;
3000 default:
3001 BUG();
3002 }
3003
3004 I915_WRITE(reg, temp);
3005 }
3006
3007 ironlake_enable_pch_transcoder(dev_priv, pipe);
3008 }
3009
lpt_pch_enable(struct drm_crtc * crtc)3010 static void lpt_pch_enable(struct drm_crtc *crtc)
3011 {
3012 struct drm_device *dev = crtc->dev;
3013 struct drm_i915_private *dev_priv = dev->dev_private;
3014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3015 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3016
3017 assert_pch_transcoder_disabled(dev_priv, (enum pipe) TRANSCODER_A);
3018
3019 lpt_program_iclkip(crtc);
3020
3021 /* Set transcoder timing. */
3022 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
3023
3024 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3025 }
3026
intel_put_shared_dpll(struct intel_crtc * crtc)3027 static void intel_put_shared_dpll(struct intel_crtc *crtc)
3028 {
3029 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3030
3031 if (pll == NULL)
3032 return;
3033
3034 if (pll->refcount == 0) {
3035 DRM_ERROR("bad PCH PLL refcount\n");
3036 return;
3037 }
3038
3039 if (--pll->refcount == 0) {
3040 WARN_ON(pll->on);
3041 WARN_ON(pll->active);
3042 if (pll->on || pll->active)
3043 DRM_ERROR("PCH PLL refcount is 0, but it's still active");
3044 }
3045
3046 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
3047 }
3048
intel_get_shared_dpll(struct intel_crtc * crtc,u32 dpll,u32 fp)3049 static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc, u32 dpll, u32 fp)
3050 {
3051 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3052 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3053 enum intel_dpll_id i;
3054
3055 if (pll) {
3056 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3057 crtc->base.base.id, pll->name);
3058 intel_put_shared_dpll(crtc);
3059 }
3060
3061 if (HAS_PCH_IBX(dev_priv->dev)) {
3062 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3063 i = (enum intel_dpll_id)crtc->pipe;
3064 pll = &dev_priv->shared_dplls[i];
3065
3066 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3067 crtc->base.base.id, pll->name);
3068
3069 goto found;
3070 }
3071
3072 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3073 pll = &dev_priv->shared_dplls[i];
3074
3075 /* Only want to check enabled timings first */
3076 if (pll->refcount == 0)
3077 continue;
3078
3079 if ((dpll & 0x7fffffff) == (I915_READ(PCH_DPLL(pll->id)) & 0x7fffffff) &&
3080 fp == I915_READ(PCH_FP0(pll->id))) {
3081 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
3082 crtc->base.base.id,
3083 pll->name, pll->refcount, pll->active);
3084
3085 goto found;
3086 }
3087 }
3088
3089 /* Ok no matching timings, maybe there's a free one? */
3090 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3091 pll = &dev_priv->shared_dplls[i];
3092 if (pll->refcount == 0) {
3093 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3094 crtc->base.base.id, pll->name);
3095 goto found;
3096 }
3097 }
3098
3099 return NULL;
3100
3101 found:
3102 crtc->config.shared_dpll = i;
3103 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3104 pipe_name(crtc->pipe));
3105
3106 if (pll->active == 0) {
3107 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3108 sizeof(pll->hw_state));
3109
3110 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
3111 WARN_ON(pll->on);
3112 assert_shared_dpll_disabled(dev_priv, pll);
3113
3114 /* Wait for the clocks to stabilize before rewriting the regs */
3115 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3116 POSTING_READ(PCH_DPLL(pll->id));
3117 udelay(150);
3118
3119 I915_WRITE(PCH_FP0(pll->id), fp);
3120 I915_WRITE(PCH_DPLL(pll->id), dpll & ~DPLL_VCO_ENABLE);
3121 }
3122 pll->refcount++;
3123
3124 return pll;
3125 }
3126
cpt_verify_modeset(struct drm_device * dev,int pipe)3127 static void cpt_verify_modeset(struct drm_device *dev, int pipe)
3128 {
3129 struct drm_i915_private *dev_priv = dev->dev_private;
3130 int dslreg = PIPEDSL(pipe);
3131 u32 temp;
3132
3133 temp = I915_READ(dslreg);
3134 udelay(500);
3135 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3136 if (wait_for(I915_READ(dslreg) != temp, 5))
3137 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
3138 }
3139 }
3140
ironlake_pfit_enable(struct intel_crtc * crtc)3141 static void ironlake_pfit_enable(struct intel_crtc *crtc)
3142 {
3143 struct drm_device *dev = crtc->base.dev;
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3145 int pipe = crtc->pipe;
3146
3147 if (crtc->config.pch_pfit.size) {
3148 /* Force use of hard-coded filter coefficients
3149 * as some pre-programmed values are broken,
3150 * e.g. x201.
3151 */
3152 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3153 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3154 PF_PIPE_SEL_IVB(pipe));
3155 else
3156 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3157 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3158 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3159 }
3160 }
3161
intel_enable_planes(struct drm_crtc * crtc)3162 static void intel_enable_planes(struct drm_crtc *crtc)
3163 {
3164 struct drm_device *dev = crtc->dev;
3165 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3166 struct intel_plane *intel_plane;
3167
3168 list_for_each_entry(intel_plane, struct intel_plane, &dev->mode_config.plane_list, base.head)
3169 if (intel_plane->pipe == pipe)
3170 intel_plane_restore(&intel_plane->base);
3171 }
3172
intel_disable_planes(struct drm_crtc * crtc)3173 static void intel_disable_planes(struct drm_crtc *crtc)
3174 {
3175 struct drm_device *dev = crtc->dev;
3176 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3177 struct intel_plane *intel_plane;
3178
3179 list_for_each_entry(intel_plane, struct intel_plane, &dev->mode_config.plane_list, base.head)
3180 if (intel_plane->pipe == pipe)
3181 intel_plane_disable(&intel_plane->base);
3182 }
3183
ironlake_crtc_enable(struct drm_crtc * crtc)3184 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3185 {
3186 struct drm_device *dev = crtc->dev;
3187 struct drm_i915_private *dev_priv = dev->dev_private;
3188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3189 struct intel_encoder *encoder;
3190 int pipe = intel_crtc->pipe;
3191 int plane = intel_crtc->plane;
3192 u32 temp;
3193
3194 WARN_ON(!crtc->enabled);
3195
3196 if (intel_crtc->active)
3197 return;
3198
3199 intel_crtc->active = true;
3200
3201 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3202 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3203
3204 intel_update_watermarks(dev);
3205
3206 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3207 temp = I915_READ(PCH_LVDS);
3208 if ((temp & LVDS_PORT_EN) == 0)
3209 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3210 }
3211
3212
3213 if (intel_crtc->config.has_pch_encoder) {
3214 /* Note: FDI PLL enabling _must_ be done before we enable the
3215 * cpu pipes, hence this is separate from all the other fdi/pch
3216 * enabling. */
3217 ironlake_fdi_pll_enable(intel_crtc);
3218 } else {
3219 assert_fdi_tx_disabled(dev_priv, pipe);
3220 assert_fdi_rx_disabled(dev_priv, pipe);
3221 }
3222
3223 for_each_encoder_on_crtc(dev, crtc, encoder)
3224 if (encoder->pre_enable)
3225 encoder->pre_enable(encoder);
3226
3227 ironlake_pfit_enable(intel_crtc);
3228
3229 /*
3230 * On ILK+ LUT must be loaded before the pipe is running but with
3231 * clocks enabled
3232 */
3233 intel_crtc_load_lut(crtc);
3234
3235 intel_enable_pipe(dev_priv, pipe,
3236 intel_crtc->config.has_pch_encoder);
3237 intel_enable_plane(dev_priv, plane, pipe);
3238 intel_enable_planes(crtc);
3239 intel_crtc_update_cursor(crtc, true);
3240
3241 if (intel_crtc->config.has_pch_encoder)
3242 ironlake_pch_enable(crtc);
3243
3244 mutex_lock(&dev->struct_mutex);
3245 intel_update_fbc(dev);
3246 mutex_unlock(&dev->struct_mutex);
3247
3248 for_each_encoder_on_crtc(dev, crtc, encoder)
3249 encoder->enable(encoder);
3250
3251 if (HAS_PCH_CPT(dev))
3252 cpt_verify_modeset(dev, intel_crtc->pipe);
3253
3254 /*
3255 * There seems to be a race in PCH platform hw (at least on some
3256 * outputs) where an enabled pipe still completes any pageflip right
3257 * away (as if the pipe is off) instead of waiting for vblank. As soon
3258 * as the first vblank happend, everything works as expected. Hence just
3259 * wait for one vblank before returning to avoid strange things
3260 * happening.
3261 */
3262 intel_wait_for_vblank(dev, intel_crtc->pipe);
3263 }
3264
3265 /* IPS only exists on ULT machines and is tied to pipe A. */
hsw_crtc_supports_ips(struct intel_crtc * crtc)3266 static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3267 {
3268 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
3269 }
3270
hsw_enable_ips(struct intel_crtc * crtc)3271 static void hsw_enable_ips(struct intel_crtc *crtc)
3272 {
3273 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3274
3275 if (!crtc->config.ips_enabled)
3276 return;
3277
3278 /* We can only enable IPS after we enable a plane and wait for a vblank.
3279 * We guarantee that the plane is enabled by calling intel_enable_ips
3280 * only after intel_enable_plane. And intel_enable_plane already waits
3281 * for a vblank, so all we need to do here is to enable the IPS bit. */
3282 assert_plane_enabled(dev_priv, crtc->plane);
3283 I915_WRITE(IPS_CTL, IPS_ENABLE);
3284 }
3285
hsw_disable_ips(struct intel_crtc * crtc)3286 static void hsw_disable_ips(struct intel_crtc *crtc)
3287 {
3288 struct drm_device *dev = crtc->base.dev;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290
3291 if (!crtc->config.ips_enabled)
3292 return;
3293
3294 assert_plane_enabled(dev_priv, crtc->plane);
3295 I915_WRITE(IPS_CTL, 0);
3296
3297 /* We need to wait for a vblank before we can disable the plane. */
3298 intel_wait_for_vblank(dev, crtc->pipe);
3299 }
3300
haswell_crtc_enable(struct drm_crtc * crtc)3301 static void haswell_crtc_enable(struct drm_crtc *crtc)
3302 {
3303 struct drm_device *dev = crtc->dev;
3304 struct drm_i915_private *dev_priv = dev->dev_private;
3305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3306 struct intel_encoder *encoder;
3307 int pipe = intel_crtc->pipe;
3308 int plane = intel_crtc->plane;
3309
3310 WARN_ON(!crtc->enabled);
3311
3312 if (intel_crtc->active)
3313 return;
3314
3315 intel_crtc->active = true;
3316
3317 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3318 if (intel_crtc->config.has_pch_encoder)
3319 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3320
3321 intel_update_watermarks(dev);
3322
3323 if (intel_crtc->config.has_pch_encoder)
3324 dev_priv->display.fdi_link_train(crtc);
3325
3326 for_each_encoder_on_crtc(dev, crtc, encoder)
3327 if (encoder->pre_enable)
3328 encoder->pre_enable(encoder);
3329
3330 intel_ddi_enable_pipe_clock(intel_crtc);
3331
3332 ironlake_pfit_enable(intel_crtc);
3333
3334 /*
3335 * On ILK+ LUT must be loaded before the pipe is running but with
3336 * clocks enabled
3337 */
3338 intel_crtc_load_lut(crtc);
3339
3340 intel_ddi_set_pipe_settings(crtc);
3341 intel_ddi_enable_transcoder_func(crtc);
3342
3343 intel_enable_pipe(dev_priv, pipe,
3344 intel_crtc->config.has_pch_encoder);
3345 intel_enable_plane(dev_priv, plane, pipe);
3346 intel_enable_planes(crtc);
3347 intel_crtc_update_cursor(crtc, true);
3348
3349 hsw_enable_ips(intel_crtc);
3350
3351 if (intel_crtc->config.has_pch_encoder)
3352 lpt_pch_enable(crtc);
3353
3354 mutex_lock(&dev->struct_mutex);
3355 intel_update_fbc(dev);
3356 mutex_unlock(&dev->struct_mutex);
3357
3358 for_each_encoder_on_crtc(dev, crtc, encoder)
3359 encoder->enable(encoder);
3360
3361 /*
3362 * There seems to be a race in PCH platform hw (at least on some
3363 * outputs) where an enabled pipe still completes any pageflip right
3364 * away (as if the pipe is off) instead of waiting for vblank. As soon
3365 * as the first vblank happend, everything works as expected. Hence just
3366 * wait for one vblank before returning to avoid strange things
3367 * happening.
3368 */
3369 intel_wait_for_vblank(dev, intel_crtc->pipe);
3370 }
3371
ironlake_pfit_disable(struct intel_crtc * crtc)3372 static void ironlake_pfit_disable(struct intel_crtc *crtc)
3373 {
3374 struct drm_device *dev = crtc->base.dev;
3375 struct drm_i915_private *dev_priv = dev->dev_private;
3376 int pipe = crtc->pipe;
3377
3378 /* To avoid upsetting the power well on haswell only disable the pfit if
3379 * it's in use. The hw state code will make sure we get this right. */
3380 if (crtc->config.pch_pfit.size) {
3381 I915_WRITE(PF_CTL(pipe), 0);
3382 I915_WRITE(PF_WIN_POS(pipe), 0);
3383 I915_WRITE(PF_WIN_SZ(pipe), 0);
3384 }
3385 }
3386
ironlake_crtc_disable(struct drm_crtc * crtc)3387 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3388 {
3389 struct drm_device *dev = crtc->dev;
3390 struct drm_i915_private *dev_priv = dev->dev_private;
3391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3392 struct intel_encoder *encoder;
3393 int pipe = intel_crtc->pipe;
3394 int plane = intel_crtc->plane;
3395 u32 reg, temp;
3396
3397
3398 if (!intel_crtc->active)
3399 return;
3400
3401 for_each_encoder_on_crtc(dev, crtc, encoder)
3402 encoder->disable(encoder);
3403
3404 intel_crtc_wait_for_pending_flips(crtc);
3405 drm_vblank_off(dev, pipe);
3406
3407 if (dev_priv->cfb_plane == plane)
3408 intel_disable_fbc(dev);
3409
3410 intel_crtc_update_cursor(crtc, false);
3411 intel_disable_planes(crtc);
3412 intel_disable_plane(dev_priv, plane, pipe);
3413
3414 if (intel_crtc->config.has_pch_encoder)
3415 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3416
3417 intel_disable_pipe(dev_priv, pipe);
3418
3419 ironlake_pfit_disable(intel_crtc);
3420
3421 for_each_encoder_on_crtc(dev, crtc, encoder)
3422 if (encoder->post_disable)
3423 encoder->post_disable(encoder);
3424
3425 if (intel_crtc->config.has_pch_encoder) {
3426 ironlake_fdi_disable(crtc);
3427
3428 ironlake_disable_pch_transcoder(dev_priv, pipe);
3429 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3430
3431 if (HAS_PCH_CPT(dev)) {
3432 /* disable TRANS_DP_CTL */
3433 reg = TRANS_DP_CTL(pipe);
3434 temp = I915_READ(reg);
3435 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3436 TRANS_DP_PORT_SEL_MASK);
3437 temp |= TRANS_DP_PORT_SEL_NONE;
3438 I915_WRITE(reg, temp);
3439
3440 /* disable DPLL_SEL */
3441 temp = I915_READ(PCH_DPLL_SEL);
3442 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
3443 I915_WRITE(PCH_DPLL_SEL, temp);
3444 }
3445
3446 /* disable PCH DPLL */
3447 intel_disable_shared_dpll(intel_crtc);
3448
3449 ironlake_fdi_pll_disable(intel_crtc);
3450 }
3451
3452 intel_crtc->active = false;
3453 intel_update_watermarks(dev);
3454
3455 mutex_lock(&dev->struct_mutex);
3456 intel_update_fbc(dev);
3457 mutex_unlock(&dev->struct_mutex);
3458 }
3459
haswell_crtc_disable(struct drm_crtc * crtc)3460 static void haswell_crtc_disable(struct drm_crtc *crtc)
3461 {
3462 struct drm_device *dev = crtc->dev;
3463 struct drm_i915_private *dev_priv = dev->dev_private;
3464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3465 struct intel_encoder *encoder;
3466 int pipe = intel_crtc->pipe;
3467 int plane = intel_crtc->plane;
3468 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
3469
3470 if (!intel_crtc->active)
3471 return;
3472
3473 for_each_encoder_on_crtc(dev, crtc, encoder)
3474 encoder->disable(encoder);
3475
3476 intel_crtc_wait_for_pending_flips(crtc);
3477 drm_vblank_off(dev, pipe);
3478
3479 /* FBC must be disabled before disabling the plane on HSW. */
3480 if (dev_priv->cfb_plane == plane)
3481 intel_disable_fbc(dev);
3482
3483 hsw_disable_ips(intel_crtc);
3484
3485 intel_crtc_update_cursor(crtc, false);
3486 intel_disable_planes(crtc);
3487 intel_disable_plane(dev_priv, plane, pipe);
3488
3489 if (intel_crtc->config.has_pch_encoder)
3490 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
3491 intel_disable_pipe(dev_priv, pipe);
3492
3493 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3494
3495 ironlake_pfit_disable(intel_crtc);
3496
3497 intel_ddi_disable_pipe_clock(intel_crtc);
3498
3499 for_each_encoder_on_crtc(dev, crtc, encoder)
3500 if (encoder->post_disable)
3501 encoder->post_disable(encoder);
3502
3503 if (intel_crtc->config.has_pch_encoder) {
3504 lpt_disable_pch_transcoder(dev_priv);
3505 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3506 intel_ddi_fdi_disable(crtc);
3507 }
3508
3509 intel_crtc->active = false;
3510 intel_update_watermarks(dev);
3511
3512 mutex_lock(&dev->struct_mutex);
3513 intel_update_fbc(dev);
3514 mutex_unlock(&dev->struct_mutex);
3515 }
3516
ironlake_crtc_off(struct drm_crtc * crtc)3517 static void ironlake_crtc_off(struct drm_crtc *crtc)
3518 {
3519 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3520 intel_put_shared_dpll(intel_crtc);
3521 }
3522
haswell_crtc_off(struct drm_crtc * crtc)3523 static void haswell_crtc_off(struct drm_crtc *crtc)
3524 {
3525 intel_ddi_put_crtc_pll(crtc);
3526 }
3527
intel_crtc_dpms_overlay(struct intel_crtc * intel_crtc,bool enable)3528 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3529 {
3530 if (!enable && intel_crtc->overlay) {
3531 struct drm_device *dev = intel_crtc->base.dev;
3532 struct drm_i915_private *dev_priv = dev->dev_private;
3533
3534 mutex_lock(&dev->struct_mutex);
3535 dev_priv->mm.interruptible = false;
3536 (void) intel_overlay_switch_off(intel_crtc->overlay);
3537 dev_priv->mm.interruptible = true;
3538 mutex_unlock(&dev->struct_mutex);
3539 }
3540
3541 /* Let userspace switch the overlay on again. In most cases userspace
3542 * has to recompute where to put it anyway.
3543 */
3544 }
3545
3546 /**
3547 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3548 * cursor plane briefly if not already running after enabling the display
3549 * plane.
3550 * This workaround avoids occasional blank screens when self refresh is
3551 * enabled.
3552 */
3553 static void
g4x_fixup_plane(struct drm_i915_private * dev_priv,enum pipe pipe)3554 g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3555 {
3556 u32 cntl = I915_READ(CURCNTR(pipe));
3557
3558 if ((cntl & CURSOR_MODE) == 0) {
3559 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3560
3561 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3562 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3563 intel_wait_for_vblank(dev_priv->dev, pipe);
3564 I915_WRITE(CURCNTR(pipe), cntl);
3565 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3566 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3567 }
3568 }
3569
i9xx_pfit_enable(struct intel_crtc * crtc)3570 static void i9xx_pfit_enable(struct intel_crtc *crtc)
3571 {
3572 struct drm_device *dev = crtc->base.dev;
3573 struct drm_i915_private *dev_priv = dev->dev_private;
3574 struct intel_crtc_config *pipe_config = &crtc->config;
3575
3576 if (!crtc->config.gmch_pfit.control)
3577 return;
3578
3579 /*
3580 * The panel fitter should only be adjusted whilst the pipe is disabled,
3581 * according to register description and PRM.
3582 */
3583 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3584 assert_pipe_disabled(dev_priv, crtc->pipe);
3585
3586 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3587 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
3588
3589 /* Border color in case we don't scale up to the full screen. Black by
3590 * default, change to something else for debugging. */
3591 I915_WRITE(BCLRPAT(crtc->pipe), 0);
3592 }
3593
valleyview_crtc_enable(struct drm_crtc * crtc)3594 static void valleyview_crtc_enable(struct drm_crtc *crtc)
3595 {
3596 struct drm_device *dev = crtc->dev;
3597 struct drm_i915_private *dev_priv = dev->dev_private;
3598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3599 struct intel_encoder *encoder;
3600 int pipe = intel_crtc->pipe;
3601 int plane = intel_crtc->plane;
3602
3603 WARN_ON(!crtc->enabled);
3604
3605 if (intel_crtc->active)
3606 return;
3607
3608 intel_crtc->active = true;
3609 intel_update_watermarks(dev);
3610
3611 mutex_lock(&dev_priv->dpio_lock);
3612
3613 for_each_encoder_on_crtc(dev, crtc, encoder)
3614 if (encoder->pre_pll_enable)
3615 encoder->pre_pll_enable(encoder);
3616
3617 intel_enable_pll(dev_priv, pipe);
3618
3619 for_each_encoder_on_crtc(dev, crtc, encoder)
3620 if (encoder->pre_enable)
3621 encoder->pre_enable(encoder);
3622
3623 /* VLV wants encoder enabling _before_ the pipe is up. */
3624 for_each_encoder_on_crtc(dev, crtc, encoder)
3625 encoder->enable(encoder);
3626
3627 i9xx_pfit_enable(intel_crtc);
3628
3629 intel_crtc_load_lut(crtc);
3630
3631 intel_enable_pipe(dev_priv, pipe, false);
3632 intel_enable_plane(dev_priv, plane, pipe);
3633 intel_enable_planes(crtc);
3634 intel_crtc_update_cursor(crtc, true);
3635
3636 intel_update_fbc(dev);
3637
3638 mutex_unlock(&dev_priv->dpio_lock);
3639 }
3640
i9xx_crtc_enable(struct drm_crtc * crtc)3641 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3642 {
3643 struct drm_device *dev = crtc->dev;
3644 struct drm_i915_private *dev_priv = dev->dev_private;
3645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3646 struct intel_encoder *encoder;
3647 int pipe = intel_crtc->pipe;
3648 int plane = intel_crtc->plane;
3649
3650 WARN_ON(!crtc->enabled);
3651
3652 if (intel_crtc->active)
3653 return;
3654
3655 intel_crtc->active = true;
3656 intel_update_watermarks(dev);
3657
3658 intel_enable_pll(dev_priv, pipe);
3659
3660 for_each_encoder_on_crtc(dev, crtc, encoder)
3661 if (encoder->pre_enable)
3662 encoder->pre_enable(encoder);
3663
3664 i9xx_pfit_enable(intel_crtc);
3665
3666 intel_crtc_load_lut(crtc);
3667
3668 intel_enable_pipe(dev_priv, pipe, false);
3669 intel_enable_plane(dev_priv, plane, pipe);
3670 intel_enable_planes(crtc);
3671 /* The fixup needs to happen before cursor is enabled */
3672 if (IS_G4X(dev))
3673 g4x_fixup_plane(dev_priv, pipe);
3674 intel_crtc_update_cursor(crtc, true);
3675
3676 /* Give the overlay scaler a chance to enable if it's on this pipe */
3677 intel_crtc_dpms_overlay(intel_crtc, true);
3678
3679 intel_update_fbc(dev);
3680
3681 for_each_encoder_on_crtc(dev, crtc, encoder)
3682 encoder->enable(encoder);
3683 }
3684
i9xx_pfit_disable(struct intel_crtc * crtc)3685 static void i9xx_pfit_disable(struct intel_crtc *crtc)
3686 {
3687 struct drm_device *dev = crtc->base.dev;
3688 struct drm_i915_private *dev_priv = dev->dev_private;
3689
3690 if (!crtc->config.gmch_pfit.control)
3691 return;
3692
3693 assert_pipe_disabled(dev_priv, crtc->pipe);
3694
3695 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3696 I915_READ(PFIT_CONTROL));
3697 I915_WRITE(PFIT_CONTROL, 0);
3698 }
3699
i9xx_crtc_disable(struct drm_crtc * crtc)3700 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3701 {
3702 struct drm_device *dev = crtc->dev;
3703 struct drm_i915_private *dev_priv = dev->dev_private;
3704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3705 struct intel_encoder *encoder;
3706 int pipe = intel_crtc->pipe;
3707 int plane = intel_crtc->plane;
3708
3709 if (!intel_crtc->active)
3710 return;
3711
3712 for_each_encoder_on_crtc(dev, crtc, encoder)
3713 encoder->disable(encoder);
3714
3715 /* Give the overlay scaler a chance to disable if it's on this pipe */
3716 intel_crtc_wait_for_pending_flips(crtc);
3717 drm_vblank_off(dev, pipe);
3718
3719 if (dev_priv->cfb_plane == plane)
3720 intel_disable_fbc(dev);
3721
3722 intel_crtc_dpms_overlay(intel_crtc, false);
3723 intel_crtc_update_cursor(crtc, false);
3724 intel_disable_planes(crtc);
3725 intel_disable_plane(dev_priv, plane, pipe);
3726
3727 intel_disable_pipe(dev_priv, pipe);
3728
3729 i9xx_pfit_disable(intel_crtc);
3730
3731 for_each_encoder_on_crtc(dev, crtc, encoder)
3732 if (encoder->post_disable)
3733 encoder->post_disable(encoder);
3734
3735 intel_disable_pll(dev_priv, pipe);
3736
3737 intel_crtc->active = false;
3738 intel_update_fbc(dev);
3739 intel_update_watermarks(dev);
3740 }
3741
i9xx_crtc_off(struct drm_crtc * crtc)3742 static void i9xx_crtc_off(struct drm_crtc *crtc)
3743 {
3744 }
3745
intel_crtc_update_sarea(struct drm_crtc * crtc,bool enabled)3746 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3747 bool enabled)
3748 {
3749 struct drm_device *dev = crtc->dev;
3750 struct drm_i915_master_private *master_priv;
3751 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3752 int pipe = intel_crtc->pipe;
3753
3754 if (!dev->primary->master)
3755 return;
3756
3757 master_priv = dev->primary->master->driver_priv;
3758 if (!master_priv->sarea_priv)
3759 return;
3760
3761 switch (pipe) {
3762 case 0:
3763 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3764 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3765 break;
3766 case 1:
3767 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3768 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3769 break;
3770 default:
3771 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3772 break;
3773 }
3774 }
3775
3776 /**
3777 * Sets the power management mode of the pipe and plane.
3778 */
intel_crtc_update_dpms(struct drm_crtc * crtc)3779 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3780 {
3781 struct drm_device *dev = crtc->dev;
3782 struct drm_i915_private *dev_priv = dev->dev_private;
3783 struct intel_encoder *intel_encoder;
3784 bool enable = false;
3785
3786 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3787 enable |= intel_encoder->connectors_active;
3788
3789 if (enable)
3790 dev_priv->display.crtc_enable(crtc);
3791 else
3792 dev_priv->display.crtc_disable(crtc);
3793
3794 intel_crtc_update_sarea(crtc, enable);
3795 }
3796
intel_crtc_disable(struct drm_crtc * crtc)3797 static void intel_crtc_disable(struct drm_crtc *crtc)
3798 {
3799 struct drm_device *dev = crtc->dev;
3800 struct drm_connector *connector;
3801 struct drm_i915_private *dev_priv = dev->dev_private;
3802 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3803
3804 /* crtc should still be enabled when we disable it. */
3805 WARN_ON(!crtc->enabled);
3806
3807 dev_priv->display.crtc_disable(crtc);
3808 intel_crtc->eld_vld = false;
3809 intel_crtc_update_sarea(crtc, false);
3810 dev_priv->display.off(crtc);
3811
3812 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3813 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3814
3815 if (crtc->fb) {
3816 mutex_lock(&dev->struct_mutex);
3817 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3818 mutex_unlock(&dev->struct_mutex);
3819 crtc->fb = NULL;
3820 }
3821
3822 /* Update computed state. */
3823 list_for_each_entry(connector, struct drm_connector, &dev->mode_config.connector_list, head) {
3824 if (!connector->encoder || !connector->encoder->crtc)
3825 continue;
3826
3827 if (connector->encoder->crtc != crtc)
3828 continue;
3829
3830 connector->dpms = DRM_MODE_DPMS_OFF;
3831 to_intel_encoder(connector->encoder)->connectors_active = false;
3832 }
3833 }
3834
intel_modeset_disable(struct drm_device * dev)3835 void intel_modeset_disable(struct drm_device *dev)
3836 {
3837 struct drm_crtc *crtc;
3838
3839 list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
3840 if (crtc->enabled)
3841 intel_crtc_disable(crtc);
3842 }
3843 }
3844
intel_encoder_destroy(struct drm_encoder * encoder)3845 void intel_encoder_destroy(struct drm_encoder *encoder)
3846 {
3847 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3848
3849 drm_encoder_cleanup(encoder);
3850 kfree(intel_encoder, intel_encoder->type_size);
3851 }
3852
3853 /* Simple dpms helper for encodres with just one connector, no cloning and only
3854 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3855 * state of the entire output pipe. */
intel_encoder_dpms(struct intel_encoder * encoder,int mode)3856 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3857 {
3858 if (mode == DRM_MODE_DPMS_ON) {
3859 encoder->connectors_active = true;
3860
3861 intel_crtc_update_dpms(encoder->base.crtc);
3862 } else {
3863 encoder->connectors_active = false;
3864
3865 intel_crtc_update_dpms(encoder->base.crtc);
3866 }
3867 }
3868
3869 /* Cross check the actual hw state with our own modeset state tracking (and it's
3870 * internal consistency). */
intel_connector_check_state(struct intel_connector * connector)3871 static void intel_connector_check_state(struct intel_connector *connector)
3872 {
3873 if (connector->get_hw_state(connector)) {
3874 struct intel_encoder *encoder = connector->encoder;
3875 struct drm_crtc *crtc;
3876 bool encoder_enabled;
3877 enum pipe pipe;
3878
3879 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3880 connector->base.base.id,
3881 drm_get_connector_name(&connector->base));
3882
3883 if (connector->base.dpms == DRM_MODE_DPMS_OFF)
3884 DRM_ERROR("wrong connector dpms state\n");
3885 if (connector->base.encoder != &encoder->base)
3886 DRM_ERROR("active connector not linked to encoder\n");
3887 if (!encoder->connectors_active)
3888 DRM_ERROR("encoder->connectors_active not set\n");
3889
3890 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3891 if (!encoder_enabled)
3892 DRM_ERROR("encoder not enabled\n");
3893 if (!encoder->base.crtc) {
3894 DRM_ERROR("crtc is NULL");
3895 return;
3896 }
3897
3898 crtc = encoder->base.crtc;
3899
3900 if (!crtc->enabled)
3901 DRM_ERROR("crtc not enabled\n");
3902 if (!to_intel_crtc(crtc)->active)
3903 DRM_ERROR("crtc not active\n");
3904 if (pipe != to_intel_crtc(crtc)->pipe)
3905 DRM_ERROR("encoder active on the wrong pipe\n");
3906 }
3907 }
3908
3909 /* Even simpler default implementation, if there's really no special case to
3910 * consider. */
intel_connector_dpms(struct drm_connector * connector,int mode)3911 void intel_connector_dpms(struct drm_connector *connector, int mode)
3912 {
3913 struct intel_encoder *encoder = intel_attached_encoder(connector);
3914
3915 /* All the simple cases only support two dpms states. */
3916 if (mode != DRM_MODE_DPMS_ON)
3917 mode = DRM_MODE_DPMS_OFF;
3918
3919 if (mode == connector->dpms)
3920 return;
3921
3922 connector->dpms = mode;
3923
3924 /* Only need to change hw state when actually enabled */
3925 if (encoder->base.crtc)
3926 intel_encoder_dpms(encoder, mode);
3927 /* LINTED */
3928 else
3929 WARN_ON(encoder->connectors_active != false);
3930
3931 intel_modeset_check_state(connector->dev);
3932 }
3933
3934 /* Simple connector->get_hw_state implementation for encoders that support only
3935 * one connector and no cloning and hence the encoder state determines the state
3936 * of the connector. */
intel_connector_get_hw_state(struct intel_connector * connector)3937 bool intel_connector_get_hw_state(struct intel_connector *connector)
3938 {
3939 enum pipe pipe = 0;
3940 struct intel_encoder *encoder = connector->encoder;
3941
3942 return encoder->get_hw_state(encoder, &pipe);
3943 }
3944
ironlake_check_fdi_lanes(struct drm_device * dev,enum pipe pipe,struct intel_crtc_config * pipe_config)3945 static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3946 struct intel_crtc_config *pipe_config)
3947 {
3948 struct drm_i915_private *dev_priv = dev->dev_private;
3949 struct intel_crtc *pipe_B_crtc =
3950 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3951
3952 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3953 pipe_name(pipe), pipe_config->fdi_lanes);
3954 if (pipe_config->fdi_lanes > 4) {
3955 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3956 pipe_name(pipe), pipe_config->fdi_lanes);
3957 return false;
3958 }
3959
3960 if (IS_HASWELL(dev)) {
3961 if (pipe_config->fdi_lanes > 2) {
3962 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3963 pipe_config->fdi_lanes);
3964 return false;
3965 } else {
3966 return true;
3967 }
3968 }
3969
3970 if (INTEL_INFO(dev)->num_pipes == 2)
3971 return true;
3972
3973 /* Ivybridge 3 pipe is really complicated */
3974 switch (pipe) {
3975 case PIPE_A:
3976 return true;
3977 case PIPE_B:
3978 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3979 pipe_config->fdi_lanes > 2) {
3980 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3981 pipe_name(pipe), pipe_config->fdi_lanes);
3982 return false;
3983 }
3984 return true;
3985 case PIPE_C:
3986 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
3987 pipe_B_crtc->config.fdi_lanes <= 2) {
3988 if (pipe_config->fdi_lanes > 2) {
3989 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3990 pipe_name(pipe), pipe_config->fdi_lanes);
3991 return false;
3992 }
3993 } else {
3994 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3995 return false;
3996 }
3997 return true;
3998 default:
3999 BUG();
4000 }
4001 return false;
4002 }
4003
4004 int i915_lane_workaround = 0;
4005 int i915_default_lanes = 4;
4006
4007 #define RETRY 1
ironlake_fdi_compute_config(struct intel_crtc * intel_crtc,struct intel_crtc_config * pipe_config)4008 static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4009 struct intel_crtc_config *pipe_config)
4010 {
4011 struct drm_device *dev = intel_crtc->base.dev;
4012 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4013 int lane, link_bw, fdi_dotclock;
4014 bool setup_ok, needs_recompute = false;
4015
4016 retry:
4017 /* FDI is a binary signal running at ~2.7GHz, encoding
4018 * each output octet as 10 bits. The actual frequency
4019 * is stored as a divider into a 100MHz clock, and the
4020 * mode pixel clock is stored in units of 1KHz.
4021 * Hence the bw of each lane in terms of the mode signal
4022 * is:
4023 */
4024 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4025
4026 fdi_dotclock = adjusted_mode->clock;
4027 fdi_dotclock /= pipe_config->pixel_multiplier;
4028
4029 if (i915_lane_workaround)
4030 lane = i915_default_lanes;
4031 else
4032 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
4033 pipe_config->pipe_bpp);
4034
4035 pipe_config->fdi_lanes = lane;
4036
4037 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
4038 link_bw, &pipe_config->fdi_m_n);
4039
4040 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4041 intel_crtc->pipe, pipe_config);
4042 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4043 pipe_config->pipe_bpp -= 2*3;
4044 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4045 pipe_config->pipe_bpp);
4046 needs_recompute = true;
4047 pipe_config->bw_constrained = true;
4048
4049 goto retry;
4050 }
4051
4052 if (needs_recompute)
4053 return RETRY;
4054
4055 return setup_ok ? 0 : -EINVAL;
4056 }
4057
hsw_compute_ips_config(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config)4058 static void hsw_compute_ips_config(struct intel_crtc *crtc,
4059 struct intel_crtc_config *pipe_config)
4060 {
4061 pipe_config->ips_enabled = i915_enable_ips &&
4062 hsw_crtc_supports_ips(crtc) &&
4063 pipe_config->pipe_bpp == 24;
4064 }
4065
intel_crtc_compute_config(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config)4066 static int intel_crtc_compute_config(struct intel_crtc *crtc,
4067 struct intel_crtc_config *pipe_config)
4068 {
4069 struct drm_device *dev = crtc->base.dev;
4070 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4071
4072 if (HAS_PCH_SPLIT(dev)) {
4073 /* FDI link clock is fixed at 2.7G */
4074 if (pipe_config->requested_mode.clock * 3
4075 > IRONLAKE_FDI_FREQ * 4)
4076 return -EINVAL;
4077 }
4078
4079 /* All interlaced capable intel hw wants timings in frames. Note though
4080 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4081 * timings, so we need to be careful not to clobber these.*/
4082 if (!pipe_config->timings_set)
4083 drm_mode_set_crtcinfo(adjusted_mode, 0);
4084
4085 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4086 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
4087 */
4088 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4089 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4090 return -EINVAL;
4091
4092 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
4093 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
4094 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
4095 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4096 * for lvds. */
4097 pipe_config->pipe_bpp = 8*3;
4098 }
4099
4100 if (HAS_IPS(dev))
4101 hsw_compute_ips_config(crtc, pipe_config);
4102
4103 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4104 * clock survives for now. */
4105 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4106 pipe_config->shared_dpll = crtc->config.shared_dpll;
4107
4108 if (pipe_config->has_pch_encoder)
4109 return ironlake_fdi_compute_config(crtc, pipe_config);
4110
4111 return 0;
4112 }
4113
valleyview_get_display_clock_speed(struct drm_device * dev)4114 static int valleyview_get_display_clock_speed(struct drm_device *dev)
4115 {
4116 return 400000; /* FIXME */
4117 }
4118
4119 /* LINTED */
i945_get_display_clock_speed(struct drm_device * dev)4120 static int i945_get_display_clock_speed(struct drm_device *dev)
4121 {
4122 return 400000;
4123 }
4124
4125 /* LINTED */
i915_get_display_clock_speed(struct drm_device * dev)4126 static int i915_get_display_clock_speed(struct drm_device *dev)
4127 {
4128 return 333000;
4129 }
4130
4131 /* LINTED */
i9xx_misc_get_display_clock_speed(struct drm_device * dev)4132 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4133 {
4134 return 200000;
4135 }
4136
i915gm_get_display_clock_speed(struct drm_device * dev)4137 static int i915gm_get_display_clock_speed(struct drm_device *dev)
4138 {
4139 u16 gcfgc = 0;
4140
4141 (void) pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4142
4143 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4144 return 133000;
4145 else {
4146 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4147 case GC_DISPLAY_CLOCK_333_MHZ:
4148 return 333000;
4149 default:
4150 case GC_DISPLAY_CLOCK_190_200_MHZ:
4151 return 190000;
4152 }
4153 }
4154 }
4155
4156 /* LINTED */
i865_get_display_clock_speed(struct drm_device * dev)4157 static int i865_get_display_clock_speed(struct drm_device *dev)
4158 {
4159 return 266000;
4160 }
4161
4162 /* LINTED */
i855_get_display_clock_speed(struct drm_device * dev)4163 static int i855_get_display_clock_speed(struct drm_device *dev)
4164 {
4165 u16 hpllcc = 0;
4166 /* Assume that the hardware is in the high speed state. This
4167 * should be the default.
4168 */
4169 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4170 case GC_CLOCK_133_200:
4171 case GC_CLOCK_100_200:
4172 return 200000;
4173 case GC_CLOCK_166_250:
4174 return 250000;
4175 case GC_CLOCK_100_133:
4176 return 133000;
4177 }
4178
4179 /* Shouldn't happen */
4180 return 0;
4181 }
4182
4183 /* LINTED */
i830_get_display_clock_speed(struct drm_device * dev)4184 static int i830_get_display_clock_speed(struct drm_device *dev)
4185 {
4186 return 133000;
4187 }
4188
4189 static void
intel_reduce_m_n_ratio(uint32_t * num,uint32_t * den)4190 intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
4191 {
4192 while (*num > DATA_LINK_M_N_MASK ||
4193 *den > DATA_LINK_M_N_MASK) {
4194 *num >>= 1;
4195 *den >>= 1;
4196 }
4197 }
4198
4199 static unsigned int
roundup_pow_of_two(unsigned int n)4200 roundup_pow_of_two(unsigned int n)
4201 {
4202 unsigned int ret_val = 0;
4203 unsigned int temp = n;
4204
4205 if (n == 0)
4206 return 0;
4207
4208 while (temp != 1) {
4209 ret_val++;
4210 temp = temp >> 1;
4211 }
4212
4213 if ((1 << ret_val) ^ n)
4214 ret_val++;
4215
4216 return (1 << ret_val);
4217 }
4218
compute_m_n(unsigned int m,unsigned int n,uint32_t * ret_m,uint32_t * ret_n)4219 static void compute_m_n(unsigned int m, unsigned int n,
4220 uint32_t *ret_m, uint32_t *ret_n)
4221 {
4222 *ret_n = min(roundup_pow_of_two(n), DATA_LINK_N_MAX);
4223 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4224 intel_reduce_m_n_ratio(ret_m, ret_n);
4225 }
4226
4227 void
intel_link_compute_m_n(int bits_per_pixel,int nlanes,int pixel_clock,int link_clock,struct intel_link_m_n * m_n)4228 intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4229 int pixel_clock, int link_clock,
4230 struct intel_link_m_n *m_n)
4231 {
4232 m_n->tu = 64;
4233 compute_m_n(bits_per_pixel * pixel_clock,
4234 link_clock * nlanes * 8,
4235 &m_n->gmch_m, &m_n->gmch_n);
4236
4237 compute_m_n(pixel_clock, link_clock,
4238 &m_n->link_m, &m_n->link_n);
4239 }
4240
intel_panel_use_ssc(struct drm_i915_private * dev_priv)4241 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4242 {
4243 if (i915_panel_use_ssc >= 0)
4244 return i915_panel_use_ssc != 0;
4245 return dev_priv->vbt.lvds_use_ssc
4246 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4247 }
4248
4249 /* LINTED */
vlv_get_refclk(struct drm_crtc * crtc)4250 static int vlv_get_refclk(struct drm_crtc *crtc)
4251 {
4252 #if 0
4253 struct drm_device *dev = crtc->dev;
4254 struct drm_i915_private *dev_priv = dev->dev_private;
4255 int refclk = 27000; /* for DP & HDMI */
4256 #endif
4257 return 100000; /* only one validated so far */
4258 /*
4259 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4260 refclk = 96000;
4261 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4262 if (intel_panel_use_ssc(dev_priv))
4263 refclk = 100000;
4264 else
4265 refclk = 96000;
4266 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4267 refclk = 100000;
4268 }
4269 return refclk;
4270 */
4271 }
4272
i9xx_get_refclk(struct drm_crtc * crtc,int num_connectors)4273 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4274 {
4275 struct drm_device *dev = crtc->dev;
4276 struct drm_i915_private *dev_priv = dev->dev_private;
4277 int refclk;
4278
4279 if (IS_VALLEYVIEW(dev)) {
4280 refclk = vlv_get_refclk(crtc);
4281 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4282 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4283 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
4284 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4285 refclk / 1000);
4286 } else if (!IS_GEN2(dev)) {
4287 refclk = 96000;
4288 } else {
4289 refclk = 48000;
4290 }
4291
4292 return refclk;
4293 }
4294
pnv_dpll_compute_fp(struct dpll * dpll)4295 static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4296 {
4297 return (1 << dpll->n) << 16 | dpll->m2;
4298 }
4299
i9xx_dpll_compute_fp(struct dpll * dpll)4300 static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4301 {
4302 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4303 }
4304
i9xx_update_pll_dividers(struct intel_crtc * crtc,intel_clock_t * reduced_clock)4305 static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
4306 intel_clock_t *reduced_clock)
4307 {
4308 struct drm_device *dev = crtc->base.dev;
4309 struct drm_i915_private *dev_priv = dev->dev_private;
4310 int pipe = crtc->pipe;
4311 u32 fp, fp2 = 0;
4312
4313 if (IS_PINEVIEW(dev)) {
4314 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
4315 if (reduced_clock)
4316 fp2 = pnv_dpll_compute_fp(reduced_clock);
4317 } else {
4318 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
4319 if (reduced_clock)
4320 fp2 = i9xx_dpll_compute_fp(reduced_clock);
4321 }
4322
4323 I915_WRITE(FP0(pipe), fp);
4324
4325 crtc->lowfreq_avail = false;
4326 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4327 reduced_clock && i915_powersave) {
4328 I915_WRITE(FP1(pipe), fp2);
4329 crtc->lowfreq_avail = true;
4330 } else {
4331 I915_WRITE(FP1(pipe), fp);
4332 }
4333 }
4334
vlv_pllb_recal_opamp(struct drm_i915_private * dev_priv)4335 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4336 {
4337 u32 reg_val;
4338
4339 /*
4340 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4341 * and set it to a reasonable value instead.
4342 */
4343 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4344 reg_val &= 0xffffff00;
4345 reg_val |= 0x00000030;
4346 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4347
4348 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4349 reg_val &= 0x8cffffff;
4350 reg_val = 0x8c000000;
4351 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4352
4353 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
4354 reg_val &= 0xffffff00;
4355 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4356
4357 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
4358 reg_val &= 0x00ffffff;
4359 reg_val |= 0xb0000000;
4360 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4361 }
4362
intel_pch_transcoder_set_m_n(struct intel_crtc * crtc,struct intel_link_m_n * m_n)4363 static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4364 struct intel_link_m_n *m_n)
4365 {
4366 struct drm_device *dev = crtc->base.dev;
4367 struct drm_i915_private *dev_priv = dev->dev_private;
4368 int pipe = crtc->pipe;
4369
4370 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4371 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4372 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4373 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
4374 }
4375
intel_cpu_transcoder_set_m_n(struct intel_crtc * crtc,struct intel_link_m_n * m_n)4376 static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4377 struct intel_link_m_n *m_n)
4378 {
4379 struct drm_device *dev = crtc->base.dev;
4380 struct drm_i915_private *dev_priv = dev->dev_private;
4381 int pipe = crtc->pipe;
4382 enum transcoder transcoder = crtc->config.cpu_transcoder;
4383
4384 if (INTEL_INFO(dev)->gen >= 5) {
4385 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4386 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4387 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4388 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4389 } else {
4390 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4391 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4392 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4393 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
4394 }
4395 }
4396
intel_dp_set_m_n(struct intel_crtc * crtc)4397 static void intel_dp_set_m_n(struct intel_crtc *crtc)
4398 {
4399 if (crtc->config.has_pch_encoder)
4400 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4401 else
4402 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4403 }
4404
vlv_update_pll(struct intel_crtc * crtc)4405 static void vlv_update_pll(struct intel_crtc *crtc)
4406 {
4407 struct drm_device *dev = crtc->base.dev;
4408 struct drm_i915_private *dev_priv = dev->dev_private;
4409 struct intel_encoder *encoder;
4410 int pipe = crtc->pipe;
4411 u32 dpll, mdiv;
4412 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4413 u32 coreclk, reg_val, dpll_md;
4414
4415 mutex_lock(&dev_priv->dpio_lock);
4416
4417 bestn = crtc->config.dpll.n;
4418 bestm1 = crtc->config.dpll.m1;
4419 bestm2 = crtc->config.dpll.m2;
4420 bestp1 = crtc->config.dpll.p1;
4421 bestp2 = crtc->config.dpll.p2;
4422
4423 /* See eDP HDMI DPIO driver vbios notes doc */
4424
4425 /* PLL B needs special handling */
4426 if (pipe)
4427 vlv_pllb_recal_opamp(dev_priv);
4428
4429 /* Set up Tx target for periodic Rcomp update */
4430 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4431
4432 /* Disable target IRef on PLL */
4433 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4434 reg_val &= 0x00ffffff;
4435 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4436
4437 /* Disable fast lock */
4438 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4439
4440 /* Set idtafcrecal before PLL is enabled */
4441 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4442 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4443 mdiv |= ((bestn << DPIO_N_SHIFT));
4444 mdiv |= (1 << DPIO_K_SHIFT);
4445
4446 /*
4447 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4448 * but we don't support that).
4449 * Note: don't use the DAC post divider as it seems unstable.
4450 */
4451 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
4452 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4453
4454 mdiv |= DPIO_ENABLE_CALIBRATION;
4455 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4456
4457 /* Set HBR and RBR LPF coefficients */
4458 if (crtc->config.port_clock == 162000 ||
4459 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
4460 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4461 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4462 0x005f0021);
4463 else
4464 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
4465 0x00d0000f);
4466
4467 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4468 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4469 /* Use SSC source */
4470 if (!pipe)
4471 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4472 0x0df40000);
4473 else
4474 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4475 0x0df70000);
4476 } else { /* HDMI or VGA */
4477 /* Use bend source */
4478 if (!pipe)
4479 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4480 0x0df70000);
4481 else
4482 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4483 0x0df40000);
4484 }
4485
4486 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4487 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4488 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4489 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4490 coreclk |= 0x01000000;
4491 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
4492
4493 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
4494
4495 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4496 if (encoder->pre_pll_enable)
4497 encoder->pre_pll_enable(encoder);
4498
4499 /* Enable DPIO clock input */
4500 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4501 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4502 if (pipe)
4503 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
4504
4505 dpll |= DPLL_VCO_ENABLE;
4506 I915_WRITE(DPLL(pipe), dpll);
4507 POSTING_READ(DPLL(pipe));
4508 udelay(150);
4509
4510 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4511 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4512
4513 dpll_md = (crtc->config.pixel_multiplier - 1)
4514 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4515 I915_WRITE(DPLL_MD(pipe), dpll_md);
4516 POSTING_READ(DPLL_MD(pipe));
4517
4518 if (crtc->config.has_dp_encoder)
4519 intel_dp_set_m_n(crtc);
4520
4521 mutex_unlock(&dev_priv->dpio_lock);
4522 }
4523
i9xx_update_pll(struct intel_crtc * crtc,intel_clock_t * reduced_clock,int num_connectors)4524 static void i9xx_update_pll(struct intel_crtc *crtc,
4525 intel_clock_t *reduced_clock,
4526 int num_connectors)
4527 {
4528 struct drm_device *dev = crtc->base.dev;
4529 struct drm_i915_private *dev_priv = dev->dev_private;
4530 struct intel_encoder *encoder;
4531 int pipe = crtc->pipe;
4532 u32 dpll;
4533 bool is_sdvo;
4534 struct dpll *clock = &crtc->config.dpll;
4535
4536 i9xx_update_pll_dividers(crtc, reduced_clock);
4537
4538 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4539 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
4540
4541 dpll = DPLL_VGA_MODE_DIS;
4542
4543 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
4544 dpll |= DPLLB_MODE_LVDS;
4545 else
4546 dpll |= DPLLB_MODE_DAC_SERIAL;
4547
4548 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4549 dpll |= (crtc->config.pixel_multiplier - 1)
4550 << SDVO_MULTIPLIER_SHIFT_HIRES;
4551 }
4552
4553 if (is_sdvo)
4554 dpll |= DPLL_DVO_HIGH_SPEED;
4555
4556 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4557 dpll |= DPLL_DVO_HIGH_SPEED;
4558
4559 /* compute bitmask from p1 value */
4560 if (IS_PINEVIEW(dev))
4561 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4562 else {
4563 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4564 if (IS_G4X(dev) && reduced_clock)
4565 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4566 }
4567 switch (clock->p2) {
4568 case 5:
4569 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4570 break;
4571 case 7:
4572 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4573 break;
4574 case 10:
4575 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4576 break;
4577 case 14:
4578 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4579 break;
4580 }
4581 if (INTEL_INFO(dev)->gen >= 4)
4582 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4583
4584 if (crtc->config.sdvo_tv_clock)
4585 dpll |= PLL_REF_INPUT_TVCLKINBC;
4586 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4587 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4588 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4589 else
4590 dpll |= PLL_REF_INPUT_DREFCLK;
4591
4592 dpll |= DPLL_VCO_ENABLE;
4593 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4594 POSTING_READ(DPLL(pipe));
4595 udelay(150);
4596
4597 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4598 if (encoder->pre_pll_enable)
4599 encoder->pre_pll_enable(encoder);
4600
4601 if (crtc->config.has_dp_encoder)
4602 intel_dp_set_m_n(crtc);
4603
4604 I915_WRITE(DPLL(pipe), dpll);
4605
4606 /* Wait for the clocks to stabilize. */
4607 POSTING_READ(DPLL(pipe));
4608 udelay(150);
4609
4610 if (INTEL_INFO(dev)->gen >= 4) {
4611 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4612 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4613 I915_WRITE(DPLL_MD(pipe), dpll_md);
4614 } else {
4615 /* The pixel multiplier can only be updated once the
4616 * DPLL is enabled and the clocks are stable.
4617 *
4618 * So write it again.
4619 */
4620 I915_WRITE(DPLL(pipe), dpll);
4621 }
4622 }
4623
i8xx_update_pll(struct intel_crtc * crtc,intel_clock_t * reduced_clock,int num_connectors)4624 static void i8xx_update_pll(struct intel_crtc *crtc,
4625 intel_clock_t *reduced_clock,
4626 int num_connectors)
4627 {
4628 struct drm_device *dev = crtc->base.dev;
4629 struct drm_i915_private *dev_priv = dev->dev_private;
4630 struct intel_encoder *encoder;
4631 int pipe = crtc->pipe;
4632 u32 dpll;
4633 struct dpll *clock = &crtc->config.dpll;
4634
4635 i9xx_update_pll_dividers(crtc, reduced_clock);
4636
4637 dpll = DPLL_VGA_MODE_DIS;
4638
4639 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
4640 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4641 } else {
4642 if (clock->p1 == 2)
4643 dpll |= PLL_P1_DIVIDE_BY_TWO;
4644 else
4645 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4646 if (clock->p2 == 4)
4647 dpll |= PLL_P2_DIVIDE_BY_4;
4648 }
4649
4650 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4651 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4652 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4653 else
4654 dpll |= PLL_REF_INPUT_DREFCLK;
4655
4656 dpll |= DPLL_VCO_ENABLE;
4657 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4658 POSTING_READ(DPLL(pipe));
4659 udelay(150);
4660
4661 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4662 if (encoder->pre_pll_enable)
4663 encoder->pre_pll_enable(encoder);
4664
4665 I915_WRITE(DPLL(pipe), dpll);
4666
4667 /* Wait for the clocks to stabilize. */
4668 POSTING_READ(DPLL(pipe));
4669 udelay(150);
4670
4671 /* The pixel multiplier can only be updated once the
4672 * DPLL is enabled and the clocks are stable.
4673 *
4674 * So write it again.
4675 */
4676 I915_WRITE(DPLL(pipe), dpll);
4677 }
4678
intel_set_pipe_timings(struct intel_crtc * intel_crtc)4679 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
4680 {
4681 struct drm_device *dev = intel_crtc->base.dev;
4682 struct drm_i915_private *dev_priv = dev->dev_private;
4683 enum pipe pipe = intel_crtc->pipe;
4684 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4685 struct drm_display_mode *adjusted_mode =
4686 &intel_crtc->config.adjusted_mode;
4687 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4688 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4689
4690 /* We need to be careful not to changed the adjusted mode, for otherwise
4691 * the hw state checker will get angry at the mismatch. */
4692 crtc_vtotal = adjusted_mode->crtc_vtotal;
4693 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
4694
4695 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4696 /* the chip adds 2 halflines automatically */
4697 crtc_vtotal -= 1;
4698 crtc_vblank_end -= 1;
4699 vsyncshift = adjusted_mode->crtc_hsync_start
4700 - adjusted_mode->crtc_htotal / 2;
4701 } else {
4702 vsyncshift = 0;
4703 }
4704
4705 if (INTEL_INFO(dev)->gen > 3)
4706 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4707
4708 I915_WRITE(HTOTAL(cpu_transcoder),
4709 (adjusted_mode->crtc_hdisplay - 1) |
4710 ((adjusted_mode->crtc_htotal - 1) << 16));
4711 I915_WRITE(HBLANK(cpu_transcoder),
4712 (adjusted_mode->crtc_hblank_start - 1) |
4713 ((adjusted_mode->crtc_hblank_end - 1) << 16));
4714 I915_WRITE(HSYNC(cpu_transcoder),
4715 (adjusted_mode->crtc_hsync_start - 1) |
4716 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4717
4718 I915_WRITE(VTOTAL(cpu_transcoder),
4719 (adjusted_mode->crtc_vdisplay - 1) |
4720 ((crtc_vtotal - 1) << 16));
4721 I915_WRITE(VBLANK(cpu_transcoder),
4722 (adjusted_mode->crtc_vblank_start - 1) |
4723 ((crtc_vblank_end - 1) << 16));
4724 I915_WRITE(VSYNC(cpu_transcoder),
4725 (adjusted_mode->crtc_vsync_start - 1) |
4726 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4727
4728 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4729 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4730 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4731 * bits. */
4732 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4733 (pipe == PIPE_B || pipe == PIPE_C))
4734 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4735
4736 /* pipesrc controls the size that is scaled from, which should
4737 * always be the user's requested size.
4738 */
4739 I915_WRITE(PIPESRC(pipe),
4740 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4741 }
4742
intel_get_pipe_timings(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config)4743 static void intel_get_pipe_timings(struct intel_crtc *crtc,
4744 struct intel_crtc_config *pipe_config)
4745 {
4746 struct drm_device *dev = crtc->base.dev;
4747 struct drm_i915_private *dev_priv = dev->dev_private;
4748 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4749 uint32_t tmp;
4750
4751 tmp = I915_READ(HTOTAL(cpu_transcoder));
4752 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4753 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4754 tmp = I915_READ(HBLANK(cpu_transcoder));
4755 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4756 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4757 tmp = I915_READ(HSYNC(cpu_transcoder));
4758 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4759 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4760
4761 tmp = I915_READ(VTOTAL(cpu_transcoder));
4762 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4763 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4764 tmp = I915_READ(VBLANK(cpu_transcoder));
4765 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4766 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4767 tmp = I915_READ(VSYNC(cpu_transcoder));
4768 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4769 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4770
4771 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4772 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4773 pipe_config->adjusted_mode.crtc_vtotal += 1;
4774 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4775 }
4776
4777 tmp = I915_READ(PIPESRC(crtc->pipe));
4778 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4779 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4780 }
4781
i9xx_set_pipeconf(struct intel_crtc * intel_crtc)4782 static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4783 {
4784 struct drm_device *dev = intel_crtc->base.dev;
4785 struct drm_i915_private *dev_priv = dev->dev_private;
4786 uint32_t pipeconf;
4787
4788 pipeconf = 0;
4789
4790 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4791 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4792 * core speed.
4793 *
4794 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4795 * pipe == 0 check?
4796 */
4797 if (intel_crtc->config.requested_mode.clock >
4798 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4799 pipeconf |= PIPECONF_DOUBLE_WIDE;
4800 }
4801
4802 /* only g4x and later have fancy bpc/dither controls */
4803 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4804 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4805 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4806 pipeconf |= PIPECONF_DITHER_EN |
4807 PIPECONF_DITHER_TYPE_SP;
4808
4809 switch (intel_crtc->config.pipe_bpp) {
4810 case 18:
4811 pipeconf |= PIPECONF_6BPC;
4812 break;
4813 case 24:
4814 pipeconf |= PIPECONF_8BPC;
4815 break;
4816 case 30:
4817 pipeconf |= PIPECONF_10BPC;
4818 break;
4819 default:
4820 /* Case prevented by intel_choose_pipe_bpp_dither. */
4821 BUG();
4822 }
4823 }
4824
4825 if (HAS_PIPE_CXSR(dev)) {
4826 if (intel_crtc->lowfreq_avail) {
4827 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4828 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4829 } else {
4830 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4831 }
4832 }
4833
4834 if (!IS_GEN2(dev) &&
4835 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4836 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4837 else
4838 pipeconf |= PIPECONF_PROGRESSIVE;
4839
4840 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4841 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4842
4843 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4844 POSTING_READ(PIPECONF(intel_crtc->pipe));
4845 }
4846
i9xx_crtc_mode_set(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * fb)4847 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4848 int x, int y,
4849 struct drm_framebuffer *fb)
4850 {
4851 struct drm_device *dev = crtc->dev;
4852 struct drm_i915_private *dev_priv = dev->dev_private;
4853 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4854 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4855 int pipe = intel_crtc->pipe;
4856 int plane = intel_crtc->plane;
4857 int refclk, num_connectors = 0;
4858 intel_clock_t clock, reduced_clock;
4859 u32 dspcntr;
4860 bool ok, has_reduced_clock = false;
4861 bool is_lvds = false;
4862 struct intel_encoder *encoder;
4863 const intel_limit_t *limit;
4864 int ret;
4865
4866 for_each_encoder_on_crtc(dev, crtc, encoder) {
4867 switch (encoder->type) {
4868 case INTEL_OUTPUT_LVDS:
4869 is_lvds = true;
4870 break;
4871 }
4872
4873 num_connectors++;
4874 }
4875
4876 refclk = i9xx_get_refclk(crtc, num_connectors);
4877
4878 /*
4879 * Returns a set of divisors for the desired target clock with the given
4880 * refclk, or FALSE. The returned values represent the clock equation:
4881 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4882 */
4883 limit = intel_limit(crtc, refclk);
4884 ok = dev_priv->display.find_dpll(limit, crtc,
4885 intel_crtc->config.port_clock,
4886 refclk, NULL, &clock);
4887 if (!ok && !intel_crtc->config.clock_set) {
4888 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4889 return -EINVAL;
4890 }
4891
4892 /* Ensure that the cursor is valid for the new mode before changing... */
4893 intel_crtc_update_cursor(crtc, true);
4894
4895 if (is_lvds && dev_priv->lvds_downclock_avail) {
4896 /*
4897 * Ensure we match the reduced clock's P to the target clock.
4898 * If the clocks don't match, we can't switch the display clock
4899 * by using the FP0/FP1. In such case we will disable the LVDS
4900 * downclock feature.
4901 */
4902 has_reduced_clock =
4903 dev_priv->display.find_dpll(limit, crtc,
4904 dev_priv->lvds_downclock,
4905 refclk, &clock,
4906 &reduced_clock);
4907 }
4908 /* Compat-code for transition, will disappear. */
4909 if (!intel_crtc->config.clock_set) {
4910 intel_crtc->config.dpll.n = clock.n;
4911 intel_crtc->config.dpll.m1 = clock.m1;
4912 intel_crtc->config.dpll.m2 = clock.m2;
4913 intel_crtc->config.dpll.p1 = clock.p1;
4914 intel_crtc->config.dpll.p2 = clock.p2;
4915 }
4916
4917 if (IS_GEN2(dev))
4918 i8xx_update_pll(intel_crtc,
4919 has_reduced_clock ? &reduced_clock : NULL,
4920 num_connectors);
4921 else if (IS_VALLEYVIEW(dev))
4922 vlv_update_pll(intel_crtc);
4923 else
4924 i9xx_update_pll(intel_crtc,
4925 has_reduced_clock ? &reduced_clock : NULL,
4926 num_connectors);
4927
4928 /* Set up the display plane register */
4929 dspcntr = DISPPLANE_GAMMA_ENABLE;
4930
4931 if (!IS_VALLEYVIEW(dev)) {
4932 if (pipe == 0)
4933 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4934 else
4935 dspcntr |= DISPPLANE_SEL_PIPE_B;
4936 }
4937
4938 intel_set_pipe_timings(intel_crtc);
4939
4940 /* pipesrc and dspsize control the size that is scaled from,
4941 * which should always be the user's requested size.
4942 */
4943 I915_WRITE(DSPSIZE(plane),
4944 ((mode->vdisplay - 1) << 16) |
4945 (mode->hdisplay - 1));
4946 I915_WRITE(DSPPOS(plane), 0);
4947
4948 i9xx_set_pipeconf(intel_crtc);
4949
4950 I915_WRITE(DSPCNTR(plane), dspcntr);
4951 POSTING_READ(DSPCNTR(plane));
4952
4953 ret = intel_pipe_set_base(crtc, x, y, fb);
4954
4955 intel_update_watermarks(dev);
4956
4957 return ret;
4958 }
4959
i9xx_get_pfit_config(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config)4960 static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4961 struct intel_crtc_config *pipe_config)
4962 {
4963 struct drm_device *dev = crtc->base.dev;
4964 struct drm_i915_private *dev_priv = dev->dev_private;
4965 uint32_t tmp;
4966
4967 tmp = I915_READ(PFIT_CONTROL);
4968 if (!(tmp & PFIT_ENABLE))
4969 return;
4970
4971 /* Check whether the pfit is attached to our pipe. */
4972 if (INTEL_INFO(dev)->gen < 4) {
4973 if (crtc->pipe != PIPE_B)
4974 return;
4975 } else {
4976 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4977 return;
4978 }
4979
4980 pipe_config->gmch_pfit.control = tmp;
4981 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4982 if (INTEL_INFO(dev)->gen < 5)
4983 pipe_config->gmch_pfit.lvds_border_bits =
4984 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4985 }
4986
i9xx_get_pipe_config(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config)4987 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4988 struct intel_crtc_config *pipe_config)
4989 {
4990 struct drm_device *dev = crtc->base.dev;
4991 struct drm_i915_private *dev_priv = dev->dev_private;
4992 uint32_t tmp;
4993
4994 pipe_config->cpu_transcoder = (enum transcoder)crtc->pipe;
4995 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
4996
4997 tmp = I915_READ(PIPECONF(crtc->pipe));
4998 if (!(tmp & PIPECONF_ENABLE))
4999 return false;
5000
5001 intel_get_pipe_timings(crtc, pipe_config);
5002
5003 i9xx_get_pfit_config(crtc, pipe_config);
5004
5005 if (INTEL_INFO(dev)->gen >= 4) {
5006 tmp = I915_READ(DPLL_MD(crtc->pipe));
5007 pipe_config->pixel_multiplier =
5008 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5009 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
5010 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5011 tmp = I915_READ(DPLL(crtc->pipe));
5012 pipe_config->pixel_multiplier =
5013 ((tmp & SDVO_MULTIPLIER_MASK)
5014 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5015 } else {
5016 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5017 * port and will be fixed up in the encoder->get_config
5018 * function. */
5019 pipe_config->pixel_multiplier = 1;
5020 }
5021
5022 return true;
5023 }
5024
ironlake_init_pch_refclk(struct drm_device * dev)5025 static void ironlake_init_pch_refclk(struct drm_device *dev)
5026 {
5027 struct drm_i915_private *dev_priv = dev->dev_private;
5028 struct drm_mode_config *mode_config = &dev->mode_config;
5029 struct intel_encoder *encoder;
5030 u32 val, final;
5031 bool has_lvds = false;
5032 bool has_cpu_edp = false;
5033 bool has_panel = false;
5034 bool has_ck505 = false;
5035 bool can_ssc = false;
5036
5037 /* We need to take the global config into account */
5038 list_for_each_entry(encoder, struct intel_encoder, &mode_config->encoder_list,
5039 base.head) {
5040 switch (encoder->type) {
5041 case INTEL_OUTPUT_LVDS:
5042 has_panel = true;
5043 has_lvds = true;
5044 break;
5045 case INTEL_OUTPUT_EDP:
5046 has_panel = true;
5047 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
5048 has_cpu_edp = true;
5049 break;
5050 }
5051 }
5052
5053 if (HAS_PCH_IBX(dev)) {
5054 has_ck505 = dev_priv->vbt.display_clock_mode;
5055 can_ssc = has_ck505;
5056 } else {
5057 has_ck505 = false;
5058 can_ssc = true;
5059 }
5060
5061 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5062 has_panel, has_lvds, has_ck505);
5063
5064 /* Ironlake: try to setup display ref clock before DPLL
5065 * enabling. This is only under driver's control after
5066 * PCH B stepping, previous chipset stepping should be
5067 * ignoring this setting.
5068 */
5069 val = I915_READ(PCH_DREF_CONTROL);
5070
5071 /* As we must carefully and slowly disable/enable each source in turn,
5072 * compute the final state we want first and check if we need to
5073 * make any changes at all.
5074 */
5075 final = val;
5076 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5077 if (has_ck505)
5078 final |= DREF_NONSPREAD_CK505_ENABLE;
5079 else
5080 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5081
5082 final &= ~DREF_SSC_SOURCE_MASK;
5083 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5084 final &= ~DREF_SSC1_ENABLE;
5085
5086 if (has_panel) {
5087 final |= DREF_SSC_SOURCE_ENABLE;
5088
5089 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5090 final |= DREF_SSC1_ENABLE;
5091
5092 if (has_cpu_edp) {
5093 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5094 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5095 else
5096 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5097 } else
5098 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5099 } else {
5100 final |= DREF_SSC_SOURCE_DISABLE;
5101 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5102 }
5103
5104 if (final == val)
5105 return;
5106
5107 /* Always enable nonspread source */
5108 val &= ~DREF_NONSPREAD_SOURCE_MASK;
5109
5110 if (has_ck505)
5111 val |= DREF_NONSPREAD_CK505_ENABLE;
5112 else
5113 val |= DREF_NONSPREAD_SOURCE_ENABLE;
5114
5115 if (has_panel) {
5116 val &= ~DREF_SSC_SOURCE_MASK;
5117 val |= DREF_SSC_SOURCE_ENABLE;
5118
5119 /* SSC must be turned on before enabling the CPU output */
5120 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5121 DRM_DEBUG_KMS("Using SSC on panel\n");
5122 val |= DREF_SSC1_ENABLE;
5123 } else
5124 val &= ~DREF_SSC1_ENABLE;
5125
5126 /* Get SSC going before enabling the outputs */
5127 I915_WRITE(PCH_DREF_CONTROL, val);
5128 POSTING_READ(PCH_DREF_CONTROL);
5129 udelay(200);
5130
5131 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5132
5133 /* Enable CPU source on CPU attached eDP */
5134 if (has_cpu_edp) {
5135 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
5136 DRM_DEBUG_KMS("Using SSC on eDP\n");
5137 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5138 }
5139 else
5140 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5141 } else
5142 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5143
5144 I915_WRITE(PCH_DREF_CONTROL, val);
5145 POSTING_READ(PCH_DREF_CONTROL);
5146 udelay(200);
5147 } else {
5148 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5149
5150 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5151
5152 /* Turn off CPU output */
5153 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5154
5155 I915_WRITE(PCH_DREF_CONTROL, val);
5156 POSTING_READ(PCH_DREF_CONTROL);
5157 udelay(200);
5158
5159 /* Turn off the SSC source */
5160 val &= ~DREF_SSC_SOURCE_MASK;
5161 val |= DREF_SSC_SOURCE_DISABLE;
5162
5163 /* Turn off SSC1 */
5164 val &= ~DREF_SSC1_ENABLE;
5165
5166 I915_WRITE(PCH_DREF_CONTROL, val);
5167 POSTING_READ(PCH_DREF_CONTROL);
5168 udelay(200);
5169 }
5170
5171 BUG_ON(val != final);
5172 }
5173
5174 /* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
lpt_init_pch_refclk(struct drm_device * dev)5175 static void lpt_init_pch_refclk(struct drm_device *dev)
5176 {
5177 struct drm_i915_private *dev_priv = dev->dev_private;
5178 struct drm_mode_config *mode_config = &dev->mode_config;
5179 struct intel_encoder *encoder;
5180 bool has_vga = false;
5181 bool is_sdv = false;
5182 u32 tmp;
5183
5184 list_for_each_entry(encoder, struct intel_encoder, &mode_config->encoder_list, base.head) {
5185 switch (encoder->type) {
5186 case INTEL_OUTPUT_ANALOG:
5187 has_vga = true;
5188 break;
5189 }
5190 }
5191
5192 if (!has_vga)
5193 return;
5194
5195 mutex_lock(&dev_priv->dpio_lock);
5196
5197 /* XXX: Rip out SDV support once Haswell ships for real. */
5198 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5199 is_sdv = true;
5200
5201 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5202 tmp &= ~SBI_SSCCTL_DISABLE;
5203 tmp |= SBI_SSCCTL_PATHALT;
5204 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5205
5206 udelay(24);
5207
5208 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5209 tmp &= ~SBI_SSCCTL_PATHALT;
5210 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5211
5212 if (!is_sdv) {
5213 tmp = I915_READ(SOUTH_CHICKEN2);
5214 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5215 I915_WRITE(SOUTH_CHICKEN2, tmp);
5216
5217 if (wait_for_atomic(I915_READ(SOUTH_CHICKEN2) &
5218 FDI_MPHY_IOSFSB_RESET_STATUS, 1))
5219 DRM_ERROR("FDI mPHY reset assert timeout\n");
5220
5221 tmp = I915_READ(SOUTH_CHICKEN2);
5222 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5223 I915_WRITE(SOUTH_CHICKEN2, tmp);
5224
5225 if (wait_for_atomic((I915_READ(SOUTH_CHICKEN2) &
5226 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5227 1))
5228 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5229 }
5230
5231 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5232 tmp &= ~(0xFFUL << 24);
5233 tmp |= (0x12 << 24);
5234 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5235
5236 if (is_sdv) {
5237 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5238 tmp |= 0x7FFF;
5239 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5240 }
5241
5242 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5243 tmp |= (1 << 11);
5244 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5245
5246 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5247 tmp |= (1 << 11);
5248 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5249
5250 if (is_sdv) {
5251 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5252 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5253 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5254
5255 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5256 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5257 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5258
5259 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5260 tmp |= (0x3F << 8);
5261 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5262
5263 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5264 tmp |= (0x3F << 8);
5265 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5266 }
5267
5268 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5269 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5270 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5271
5272 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5273 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5274 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5275
5276 if (!is_sdv) {
5277 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5278 tmp &= ~(7 << 13);
5279 tmp |= (5 << 13);
5280 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5281
5282 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5283 tmp &= ~(7 << 13);
5284 tmp |= (5 << 13);
5285 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5286 }
5287
5288 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5289 tmp &= ~0xFF;
5290 tmp |= 0x1C;
5291 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5292
5293 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5294 tmp &= ~0xFF;
5295 tmp |= 0x1C;
5296 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5297
5298 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5299 tmp &= ~(0xFF << 16);
5300 tmp |= (0x1C << 16);
5301 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5302
5303 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5304 tmp &= ~(0xFF << 16);
5305 tmp |= (0x1C << 16);
5306 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5307
5308 if (!is_sdv) {
5309 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5310 tmp |= (1 << 27);
5311 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5312
5313 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5314 tmp |= (1 << 27);
5315 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5316
5317 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5318 tmp &= ~(0xFUL << 28);
5319 tmp |= (4 << 28);
5320 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5321
5322 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5323 tmp &= ~(0xFUL << 28);
5324 tmp |= (4 << 28);
5325 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5326 }
5327
5328 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5329 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5330 tmp |= SBI_DBUFF0_ENABLE;
5331 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
5332
5333 mutex_unlock(&dev_priv->dpio_lock);
5334 }
5335
5336 /*
5337 * Initialize reference clocks when the driver loads
5338 */
intel_init_pch_refclk(struct drm_device * dev)5339 void intel_init_pch_refclk(struct drm_device *dev)
5340 {
5341 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5342 ironlake_init_pch_refclk(dev);
5343 else if (HAS_PCH_LPT(dev))
5344 lpt_init_pch_refclk(dev);
5345 }
5346
ironlake_get_refclk(struct drm_crtc * crtc)5347 static int ironlake_get_refclk(struct drm_crtc *crtc)
5348 {
5349 struct drm_device *dev = crtc->dev;
5350 struct drm_i915_private *dev_priv = dev->dev_private;
5351 struct intel_encoder *encoder;
5352 int num_connectors = 0;
5353 bool is_lvds = false;
5354
5355 for_each_encoder_on_crtc(dev, crtc, encoder) {
5356 switch (encoder->type) {
5357 case INTEL_OUTPUT_LVDS:
5358 is_lvds = true;
5359 break;
5360 }
5361 num_connectors++;
5362 }
5363
5364 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5365 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5366 dev_priv->vbt.lvds_ssc_freq);
5367 return dev_priv->vbt.lvds_ssc_freq * 1000;
5368 }
5369
5370 return 120000;
5371 }
5372
ironlake_set_pipeconf(struct drm_crtc * crtc)5373 static void ironlake_set_pipeconf(struct drm_crtc *crtc)
5374 {
5375 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5377 int pipe = intel_crtc->pipe;
5378 uint32_t val;
5379
5380 val = 0;
5381
5382 switch (intel_crtc->config.pipe_bpp) {
5383 case 18:
5384 val |= PIPECONF_6BPC;
5385 break;
5386 case 24:
5387 val |= PIPECONF_8BPC;
5388 break;
5389 case 30:
5390 val |= PIPECONF_10BPC;
5391 break;
5392 case 36:
5393 val |= PIPECONF_12BPC;
5394 break;
5395 default:
5396 /* Case prevented by intel_choose_pipe_bpp_dither. */
5397 BUG();
5398 }
5399
5400 if (intel_crtc->config.dither)
5401 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5402
5403 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5404 val |= PIPECONF_INTERLACED_ILK;
5405 else
5406 val |= PIPECONF_PROGRESSIVE;
5407
5408 if (intel_crtc->config.limited_color_range)
5409 val |= PIPECONF_COLOR_RANGE_SELECT;
5410
5411 I915_WRITE(PIPECONF(pipe), val);
5412 POSTING_READ(PIPECONF(pipe));
5413 }
5414
5415 /*
5416 * Set up the pipe CSC unit.
5417 *
5418 * Currently only full range RGB to limited range RGB conversion
5419 * is supported, but eventually this should handle various
5420 * RGB<->YCbCr scenarios as well.
5421 */
intel_set_pipe_csc(struct drm_crtc * crtc)5422 static void intel_set_pipe_csc(struct drm_crtc *crtc)
5423 {
5424 struct drm_device *dev = crtc->dev;
5425 struct drm_i915_private *dev_priv = dev->dev_private;
5426 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5427 int pipe = intel_crtc->pipe;
5428 uint16_t coeff = 0x7800; /* 1.0 */
5429
5430 /*
5431 * TODO: Check what kind of values actually come out of the pipe
5432 * with these coeff/postoff values and adjust to get the best
5433 * accuracy. Perhaps we even need to take the bpc value into
5434 * consideration.
5435 */
5436
5437 if (intel_crtc->config.limited_color_range)
5438 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5439
5440 /*
5441 * GY/GU and RY/RU should be the other way around according
5442 * to BSpec, but reality doesn't agree. Just set them up in
5443 * a way that results in the correct picture.
5444 */
5445 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5446 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5447
5448 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5449 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5450
5451 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5452 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5453
5454 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5455 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5456 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5457
5458 if (INTEL_INFO(dev)->gen > 6) {
5459 uint16_t postoff = 0;
5460
5461 if (intel_crtc->config.limited_color_range)
5462 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5463
5464 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5465 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5466 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5467
5468 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5469 } else {
5470 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5471
5472 if (intel_crtc->config.limited_color_range)
5473 mode |= CSC_BLACK_SCREEN_OFFSET;
5474
5475 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5476 }
5477 }
5478
haswell_set_pipeconf(struct drm_crtc * crtc)5479 static void haswell_set_pipeconf(struct drm_crtc *crtc)
5480 {
5481 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5482 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5483 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
5484 uint32_t val;
5485
5486 val = 0;
5487
5488 if (intel_crtc->config.dither)
5489 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5490
5491 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5492 val |= PIPECONF_INTERLACED_ILK;
5493 else
5494 val |= PIPECONF_PROGRESSIVE;
5495
5496 I915_WRITE(PIPECONF(cpu_transcoder), val);
5497 POSTING_READ(PIPECONF(cpu_transcoder));
5498
5499 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5500 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
5501 }
5502
ironlake_compute_clocks(struct drm_crtc * crtc,intel_clock_t * clock,bool * has_reduced_clock,intel_clock_t * reduced_clock)5503 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5504 intel_clock_t *clock,
5505 bool *has_reduced_clock,
5506 intel_clock_t *reduced_clock)
5507 {
5508 struct drm_device *dev = crtc->dev;
5509 struct drm_i915_private *dev_priv = dev->dev_private;
5510 struct intel_encoder *intel_encoder;
5511 int refclk;
5512 const intel_limit_t *limit;
5513 bool ret, is_lvds = false;
5514
5515 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5516 switch (intel_encoder->type) {
5517 case INTEL_OUTPUT_LVDS:
5518 is_lvds = true;
5519 break;
5520 }
5521 }
5522
5523 refclk = ironlake_get_refclk(crtc);
5524
5525 /*
5526 * Returns a set of divisors for the desired target clock with the given
5527 * refclk, or FALSE. The returned values represent the clock equation:
5528 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5529 */
5530 limit = intel_limit(crtc, refclk);
5531 ret = dev_priv->display.find_dpll(limit, crtc,
5532 to_intel_crtc(crtc)->config.port_clock,
5533 refclk, NULL, clock);
5534 if (!ret)
5535 return false;
5536
5537 if (is_lvds && dev_priv->lvds_downclock_avail) {
5538 /*
5539 * Ensure we match the reduced clock's P to the target clock.
5540 * If the clocks don't match, we can't switch the display clock
5541 * by using the FP0/FP1. In such case we will disable the LVDS
5542 * downclock feature.
5543 */
5544 *has_reduced_clock =
5545 dev_priv->display.find_dpll(limit, crtc,
5546 dev_priv->lvds_downclock,
5547 refclk, clock,
5548 reduced_clock);
5549 }
5550
5551 return true;
5552 }
5553
cpt_enable_fdi_bc_bifurcation(struct drm_device * dev)5554 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5555 {
5556 struct drm_i915_private *dev_priv = dev->dev_private;
5557 uint32_t temp;
5558
5559 temp = I915_READ(SOUTH_CHICKEN1);
5560 if (temp & FDI_BC_BIFURCATION_SELECT)
5561 return;
5562
5563 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5564 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5565
5566 temp |= FDI_BC_BIFURCATION_SELECT;
5567 DRM_DEBUG_KMS("enabling fdi C rx\n");
5568 I915_WRITE(SOUTH_CHICKEN1, temp);
5569 POSTING_READ(SOUTH_CHICKEN1);
5570 }
5571
ivybridge_update_fdi_bc_bifurcation(struct intel_crtc * intel_crtc)5572 static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5573 {
5574 struct drm_device *dev = intel_crtc->base.dev;
5575 struct drm_i915_private *dev_priv = dev->dev_private;
5576
5577 switch (intel_crtc->pipe) {
5578 case PIPE_A:
5579 break;
5580 case PIPE_B:
5581 if (intel_crtc->config.fdi_lanes > 2) {
5582 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5583 DRM_DEBUG_KMS("bc_bifurcation select 0x%x", I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5584 } else
5585 cpt_enable_fdi_bc_bifurcation(dev);
5586
5587 break;
5588 case PIPE_C:
5589 cpt_enable_fdi_bc_bifurcation(dev);
5590
5591 break;
5592 default:
5593 BUG();
5594 }
5595 }
5596
ironlake_get_lanes_required(int target_clock,int link_bw,int bpp)5597 int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5598 {
5599 /*
5600 * Account for spread spectrum to avoid
5601 * oversubscribing the link. Max center spread
5602 * is 2.5%; use 5% for safety's sake.
5603 */
5604 u32 bps = target_clock * bpp * 21 / 20;
5605 return bps / (link_bw * 8) + 1;
5606 }
5607
ironlake_needs_fb_cb_tune(struct dpll * dpll,int factor)5608 static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5609 {
5610 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5611 }
5612
ironlake_compute_dpll(struct intel_crtc * intel_crtc,u32 * fp,intel_clock_t * reduced_clock,u32 * fp2)5613 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5614 u32 *fp,
5615 intel_clock_t *reduced_clock, u32 *fp2)
5616 {
5617 struct drm_crtc *crtc = &intel_crtc->base;
5618 struct drm_device *dev = crtc->dev;
5619 struct drm_i915_private *dev_priv = dev->dev_private;
5620 struct intel_encoder *intel_encoder;
5621 uint32_t dpll;
5622 int factor, num_connectors = 0;
5623 bool is_lvds = false, is_sdvo = false;
5624
5625 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5626 switch (intel_encoder->type) {
5627 case INTEL_OUTPUT_LVDS:
5628 is_lvds = true;
5629 break;
5630 case INTEL_OUTPUT_SDVO:
5631 case INTEL_OUTPUT_HDMI:
5632 is_sdvo = true;
5633 break;
5634 }
5635
5636 num_connectors++;
5637 }
5638
5639 /* Enable autotuning of the PLL clock (if permissible) */
5640 factor = 21;
5641 if (is_lvds) {
5642 if ((intel_panel_use_ssc(dev_priv) &&
5643 dev_priv->vbt.lvds_ssc_freq == 100) ||
5644 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
5645 factor = 25;
5646 } else if (intel_crtc->config.sdvo_tv_clock)
5647 factor = 20;
5648
5649 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
5650 *fp |= FP_CB_TUNE;
5651
5652 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5653 *fp2 |= FP_CB_TUNE;
5654
5655 dpll = 0;
5656
5657 if (is_lvds)
5658 dpll |= DPLLB_MODE_LVDS;
5659 else
5660 dpll |= DPLLB_MODE_DAC_SERIAL;
5661
5662 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5663 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5664
5665 if (is_sdvo)
5666 dpll |= DPLL_DVO_HIGH_SPEED;
5667 if (intel_crtc->config.has_dp_encoder)
5668 dpll |= DPLL_DVO_HIGH_SPEED;
5669
5670 /* compute bitmask from p1 value */
5671 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5672 /* also FPA1 */
5673 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5674
5675 switch (intel_crtc->config.dpll.p2) {
5676 case 5:
5677 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5678 break;
5679 case 7:
5680 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5681 break;
5682 case 10:
5683 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5684 break;
5685 case 14:
5686 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5687 break;
5688 }
5689
5690 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5691 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5692 else
5693 dpll |= PLL_REF_INPUT_DREFCLK;
5694
5695 return dpll | DPLL_VCO_ENABLE;
5696 }
5697
ironlake_crtc_mode_set(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * fb)5698 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5699 int x, int y,
5700 struct drm_framebuffer *fb)
5701 {
5702 struct drm_device *dev = crtc->dev;
5703 struct drm_i915_private *dev_priv = dev->dev_private;
5704 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5705 int pipe = intel_crtc->pipe;
5706 int plane = intel_crtc->plane;
5707 int num_connectors = 0;
5708 intel_clock_t clock, reduced_clock;
5709 u32 dpll = 0, fp = 0, fp2 = 0;
5710 bool ok, has_reduced_clock = false;
5711 bool is_lvds = false;
5712 struct intel_encoder *encoder;
5713 struct intel_shared_dpll *pll;
5714 int ret;
5715
5716 for_each_encoder_on_crtc(dev, crtc, encoder) {
5717 switch (encoder->type) {
5718 case INTEL_OUTPUT_LVDS:
5719 is_lvds = true;
5720 break;
5721 }
5722
5723 num_connectors++;
5724 }
5725
5726 if(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)))
5727 DRM_ERROR("Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5728
5729 ok = ironlake_compute_clocks(crtc, &clock,
5730 &has_reduced_clock, &reduced_clock);
5731 if (!ok && !intel_crtc->config.clock_set) {
5732 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5733 return -EINVAL;
5734 }
5735 /* Compat-code for transition, will disappear. */
5736 if (!intel_crtc->config.clock_set) {
5737 intel_crtc->config.dpll.n = clock.n;
5738 intel_crtc->config.dpll.m1 = clock.m1;
5739 intel_crtc->config.dpll.m2 = clock.m2;
5740 intel_crtc->config.dpll.p1 = clock.p1;
5741 intel_crtc->config.dpll.p2 = clock.p2;
5742 }
5743
5744 /* Ensure that the cursor is valid for the new mode before changing... */
5745 intel_crtc_update_cursor(crtc, true);
5746
5747 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5748 if (intel_crtc->config.has_pch_encoder) {
5749 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
5750 if (has_reduced_clock)
5751 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
5752
5753 dpll = ironlake_compute_dpll(intel_crtc,
5754 &fp, &reduced_clock,
5755 has_reduced_clock ? &fp2 : NULL);
5756
5757 intel_crtc->config.dpll_hw_state.dpll = dpll;
5758 intel_crtc->config.dpll_hw_state.fp0 = fp;
5759 if (has_reduced_clock)
5760 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5761 else
5762 intel_crtc->config.dpll_hw_state.fp1 = fp;
5763
5764 pll = intel_get_shared_dpll(intel_crtc, dpll, fp);
5765 if (pll == NULL) {
5766 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5767 pipe_name(pipe));
5768 return -EINVAL;
5769 }
5770 } else
5771 intel_put_shared_dpll(intel_crtc);
5772
5773 if (intel_crtc->config.has_dp_encoder)
5774 intel_dp_set_m_n(intel_crtc);
5775
5776 for_each_encoder_on_crtc(dev, crtc, encoder)
5777 if (encoder->pre_pll_enable)
5778 encoder->pre_pll_enable(encoder);
5779
5780 if (is_lvds && has_reduced_clock && i915_powersave)
5781 intel_crtc->lowfreq_avail = true;
5782 else
5783 intel_crtc->lowfreq_avail = false;
5784
5785 if (intel_crtc->config.has_pch_encoder) {
5786 pll = intel_crtc_to_shared_dpll(intel_crtc);
5787 /*
5788 * We previously verified the shared_dpll in the eDP case,
5789 * so pll should not be NULL from above call.
5790 */
5791 BUG_ON(pll == NULL);
5792 if (pll == NULL)
5793 return -EINVAL;
5794
5795 I915_WRITE(PCH_DPLL(pll->id), dpll);
5796
5797 /* Wait for the clocks to stabilize. */
5798 POSTING_READ(PCH_DPLL(pll->id));
5799 udelay(150);
5800
5801 /* The pixel multiplier can only be updated once the
5802 * DPLL is enabled and the clocks are stable.
5803 *
5804 * So write it again.
5805 */
5806 I915_WRITE(PCH_DPLL(pll->id), dpll);
5807
5808 if (has_reduced_clock)
5809 I915_WRITE(PCH_FP1(pll->id), fp2);
5810 else
5811 I915_WRITE(PCH_FP1(pll->id), fp);
5812 }
5813
5814 intel_set_pipe_timings(intel_crtc);
5815
5816 if (intel_crtc->config.has_pch_encoder) {
5817 intel_cpu_transcoder_set_m_n(intel_crtc,
5818 &intel_crtc->config.fdi_m_n);
5819 }
5820
5821 if (IS_IVYBRIDGE(dev))
5822 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
5823
5824 ironlake_set_pipeconf(crtc);
5825
5826 /* Set up the display plane register */
5827 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5828 POSTING_READ(DSPCNTR(plane));
5829
5830 ret = intel_pipe_set_base(crtc, x, y, fb);
5831
5832 intel_update_watermarks(dev);
5833
5834 return ret;
5835 }
5836
ironlake_get_fdi_m_n_config(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config)5837 static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5838 struct intel_crtc_config *pipe_config)
5839 {
5840 struct drm_device *dev = crtc->base.dev;
5841 struct drm_i915_private *dev_priv = dev->dev_private;
5842 enum transcoder transcoder = pipe_config->cpu_transcoder;
5843
5844 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5845 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5846 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5847 & ~TU_SIZE_MASK;
5848 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5849 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5850 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5851 }
5852
ironlake_get_pfit_config(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config)5853 static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5854 struct intel_crtc_config *pipe_config)
5855 {
5856 struct drm_device *dev = crtc->base.dev;
5857 struct drm_i915_private *dev_priv = dev->dev_private;
5858 uint32_t tmp;
5859
5860 tmp = I915_READ(PF_CTL(crtc->pipe));
5861
5862 if (tmp & PF_ENABLE) {
5863 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5864 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5865
5866 /* We currently do not free assignements of panel fitters on
5867 * ivb/hsw (since we don't use the higher upscaling modes which
5868 * differentiates them) so just WARN about this case for now. */
5869 if (IS_GEN7(dev)) {
5870 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5871 PF_PIPE_SEL_IVB(crtc->pipe));
5872 DRM_DEBUG("PF_CTL(crtc->pipe) 0x%x", tmp);
5873 }
5874 }
5875 }
5876
ironlake_get_pipe_config(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config)5877 static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5878 struct intel_crtc_config *pipe_config)
5879 {
5880 struct drm_device *dev = crtc->base.dev;
5881 struct drm_i915_private *dev_priv = dev->dev_private;
5882 uint32_t tmp;
5883
5884 pipe_config->cpu_transcoder = (enum transcoder)crtc->pipe;
5885 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5886
5887 tmp = I915_READ(PIPECONF(crtc->pipe));
5888 if (!(tmp & PIPECONF_ENABLE))
5889 return false;
5890
5891 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
5892 /* LINTED */
5893 struct intel_shared_dpll *pll;
5894
5895 pipe_config->has_pch_encoder = true;
5896
5897 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5898 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5899 FDI_DP_PORT_WIDTH_SHIFT) + 1;
5900
5901 ironlake_get_fdi_m_n_config(crtc, pipe_config);
5902
5903 /* XXX: Can't properly read out the pch dpll pixel multiplier
5904 * since we don't have state tracking for pch clocks yet. */
5905 pipe_config->pixel_multiplier = 1;
5906
5907 if (HAS_PCH_IBX(dev_priv->dev)) {
5908 pipe_config->shared_dpll = (enum intel_dpll_id)crtc->pipe;
5909 } else {
5910 tmp = I915_READ(PCH_DPLL_SEL);
5911 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5912 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5913 else
5914 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5915 }
5916
5917 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5918
5919 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5920 &pipe_config->dpll_hw_state));
5921 } else {
5922 pipe_config->pixel_multiplier = 1;
5923 }
5924
5925 intel_get_pipe_timings(crtc, pipe_config);
5926
5927 ironlake_get_pfit_config(crtc, pipe_config);
5928
5929 return true;
5930 }
5931
haswell_modeset_global_resources(struct drm_device * dev)5932 static void haswell_modeset_global_resources(struct drm_device *dev)
5933 {
5934 bool enable = false;
5935 struct intel_crtc *crtc;
5936
5937 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list, base.head) {
5938 if (!crtc->base.enabled)
5939 continue;
5940
5941 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5942 crtc->config.cpu_transcoder != TRANSCODER_EDP)
5943 enable = true;
5944 }
5945
5946 intel_set_power_well(dev, enable);
5947 }
5948
haswell_crtc_mode_set(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * fb)5949 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5950 int x, int y,
5951 struct drm_framebuffer *fb)
5952 {
5953 struct drm_device *dev = crtc->dev;
5954 struct drm_i915_private *dev_priv = dev->dev_private;
5955 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5956 int plane = intel_crtc->plane;
5957 int ret;
5958
5959 if (!intel_ddi_pll_mode_set(crtc))
5960 return -EINVAL;
5961
5962 /* Ensure that the cursor is valid for the new mode before changing... */
5963 intel_crtc_update_cursor(crtc, true);
5964
5965 if (intel_crtc->config.has_dp_encoder)
5966 intel_dp_set_m_n(intel_crtc);
5967
5968 intel_crtc->lowfreq_avail = false;
5969
5970 intel_set_pipe_timings(intel_crtc);
5971
5972 if (intel_crtc->config.has_pch_encoder) {
5973 intel_cpu_transcoder_set_m_n(intel_crtc,
5974 &intel_crtc->config.fdi_m_n);
5975 }
5976
5977 haswell_set_pipeconf(crtc);
5978
5979 intel_set_pipe_csc(crtc);
5980
5981 /* Set up the display plane register */
5982 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
5983 POSTING_READ(DSPCNTR(plane));
5984
5985 ret = intel_pipe_set_base(crtc, x, y, fb);
5986
5987 intel_update_watermarks(dev);
5988
5989 return ret;
5990 }
5991
haswell_get_pipe_config(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config)5992 static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5993 struct intel_crtc_config *pipe_config)
5994 {
5995 struct drm_device *dev = crtc->base.dev;
5996 struct drm_i915_private *dev_priv = dev->dev_private;
5997 enum intel_display_power_domain pfit_domain;
5998 uint32_t tmp;
5999
6000 pipe_config->cpu_transcoder = (enum transcoder)crtc->pipe;
6001 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6002
6003 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6004 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6005 enum pipe trans_edp_pipe;
6006 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6007 default:
6008 DRM_ERROR("unknown pipe linked to edp transcoder\n");
6009 /* FALLTHROUGH */
6010 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6011 case TRANS_DDI_EDP_INPUT_A_ON:
6012 trans_edp_pipe = PIPE_A;
6013 break;
6014 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6015 trans_edp_pipe = PIPE_B;
6016 break;
6017 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6018 trans_edp_pipe = PIPE_C;
6019 break;
6020 }
6021
6022 if (trans_edp_pipe == crtc->pipe)
6023 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6024 }
6025
6026 if (!intel_display_power_enabled(dev,
6027 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
6028 return false;
6029
6030 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
6031 if (!(tmp & PIPECONF_ENABLE))
6032 return false;
6033
6034 /*
6035 * Haswell has only FDI/PCH transcoder A. It is which is connected to
6036 * DDI E. So just check whether this pipe is wired to DDI E and whether
6037 * the PCH transcoder is on.
6038 */
6039 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
6040 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
6041 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
6042 pipe_config->has_pch_encoder = true;
6043
6044 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6045 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6046 FDI_DP_PORT_WIDTH_SHIFT) + 1;
6047
6048 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6049 }
6050
6051 intel_get_pipe_timings(crtc, pipe_config);
6052
6053 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6054 if (intel_display_power_enabled(dev, pfit_domain))
6055 ironlake_get_pfit_config(crtc, pipe_config);
6056
6057 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6058 (I915_READ(IPS_CTL) & IPS_ENABLE);
6059
6060 pipe_config->pixel_multiplier = 1;
6061
6062 return true;
6063 }
6064
intel_crtc_mode_set(struct drm_crtc * crtc,int x,int y,struct drm_framebuffer * fb)6065 static int intel_crtc_mode_set(struct drm_crtc *crtc,
6066 int x, int y,
6067 struct drm_framebuffer *fb)
6068 {
6069 struct drm_device *dev = crtc->dev;
6070 struct drm_i915_private *dev_priv = dev->dev_private;
6071 struct drm_encoder_helper_funcs *encoder_funcs;
6072 struct intel_encoder *encoder;
6073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6074 struct drm_display_mode *adjusted_mode =
6075 &intel_crtc->config.adjusted_mode;
6076 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
6077 int pipe = intel_crtc->pipe;
6078 int ret;
6079
6080 drm_vblank_pre_modeset(dev, pipe);
6081
6082 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6083
6084 drm_vblank_post_modeset(dev, pipe);
6085
6086 if (ret != 0)
6087 return ret;
6088
6089 for_each_encoder_on_crtc(dev, crtc, encoder) {
6090 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6091 encoder->base.base.id,
6092 drm_get_encoder_name(&encoder->base),
6093 mode->base.id, mode->name);
6094 if (encoder->mode_set) {
6095 encoder->mode_set(encoder);
6096 } else {
6097 encoder_funcs = encoder->base.helper_private;
6098 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6099 }
6100 }
6101
6102 return 0;
6103 }
6104
intel_eld_uptodate(struct drm_connector * connector,int reg_eldv,uint32_t bits_eldv,int reg_elda,uint32_t bits_elda,int reg_edid)6105 static bool intel_eld_uptodate(struct drm_connector *connector,
6106 int reg_eldv, uint32_t bits_eldv,
6107 int reg_elda, uint32_t bits_elda,
6108 int reg_edid)
6109 {
6110 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6111 uint8_t *eld = connector->eld;
6112 uint32_t i;
6113
6114 i = I915_READ(reg_eldv);
6115 i &= bits_eldv;
6116
6117 if (!eld[0])
6118 return !i;
6119
6120 if (!i)
6121 return false;
6122
6123 i = I915_READ(reg_elda);
6124 i &= ~bits_elda;
6125 I915_WRITE(reg_elda, i);
6126
6127 for (i = 0; i < eld[2]; i++)
6128 if (I915_READ(reg_edid) != *((uint32_t *)(uintptr_t)eld + i))
6129 return false;
6130
6131 return true;
6132 }
6133
g4x_write_eld(struct drm_connector * connector,struct drm_crtc * crtc)6134 static void g4x_write_eld(struct drm_connector *connector,
6135 struct drm_crtc *crtc)
6136 {
6137 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6138 uint8_t *eld = connector->eld;
6139 uint32_t eldv;
6140 uint32_t len;
6141 uint32_t i;
6142
6143 i = I915_READ(G4X_AUD_VID_DID);
6144
6145 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6146 eldv = G4X_ELDV_DEVCL_DEVBLC;
6147 else
6148 eldv = G4X_ELDV_DEVCTG;
6149
6150 if (intel_eld_uptodate(connector,
6151 G4X_AUD_CNTL_ST, eldv,
6152 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6153 G4X_HDMIW_HDMIEDID))
6154 return;
6155
6156 i = I915_READ(G4X_AUD_CNTL_ST);
6157 i &= ~(eldv | G4X_ELD_ADDR);
6158 len = (i >> 9) & 0x1f; /* ELD buffer size */
6159 I915_WRITE(G4X_AUD_CNTL_ST, i);
6160
6161 if (!eld[0])
6162 return;
6163
6164 len = min(eld[2], len);
6165 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6166 for (i = 0; i < len; i++)
6167 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)(uintptr_t)eld + i));
6168
6169 i = I915_READ(G4X_AUD_CNTL_ST);
6170 i |= eldv;
6171 I915_WRITE(G4X_AUD_CNTL_ST, i);
6172 }
6173
haswell_write_eld(struct drm_connector * connector,struct drm_crtc * crtc)6174 static void haswell_write_eld(struct drm_connector *connector,
6175 struct drm_crtc *crtc)
6176 {
6177 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6178 uint8_t *eld = connector->eld;
6179 struct drm_device *dev = crtc->dev;
6180 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6181 uint32_t eldv;
6182 uint32_t i;
6183 int len;
6184 int pipe = to_intel_crtc(crtc)->pipe;
6185 int tmp;
6186
6187 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6188 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6189 int aud_config = HSW_AUD_CFG(pipe);
6190 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6191
6192
6193 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6194
6195 /* Audio output enable */
6196 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6197 tmp = I915_READ(aud_cntrl_st2);
6198 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6199 I915_WRITE(aud_cntrl_st2, tmp);
6200
6201 /* Wait for 1 vertical blank */
6202 intel_wait_for_vblank(dev, pipe);
6203
6204 /* Set ELD valid state */
6205 tmp = I915_READ(aud_cntrl_st2);
6206 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6207 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6208 I915_WRITE(aud_cntrl_st2, tmp);
6209 tmp = I915_READ(aud_cntrl_st2);
6210 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6211
6212 /* Enable HDMI mode */
6213 tmp = I915_READ(aud_config);
6214 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6215 /* clear N_programing_enable and N_value_index */
6216 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6217 I915_WRITE(aud_config, tmp);
6218
6219 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6220
6221 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
6222 intel_crtc->eld_vld = true;
6223
6224 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6225 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6226 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6227 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6228 } else
6229 I915_WRITE(aud_config, 0);
6230
6231 if (intel_eld_uptodate(connector,
6232 aud_cntrl_st2, eldv,
6233 aud_cntl_st, IBX_ELD_ADDRESS,
6234 hdmiw_hdmiedid))
6235 return;
6236
6237 i = I915_READ(aud_cntrl_st2);
6238 i &= ~eldv;
6239 I915_WRITE(aud_cntrl_st2, i);
6240
6241 if (!eld[0])
6242 return;
6243
6244 i = I915_READ(aud_cntl_st);
6245 i &= ~IBX_ELD_ADDRESS;
6246 I915_WRITE(aud_cntl_st, i);
6247 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6248 DRM_DEBUG_DRIVER("port num:%d\n", i);
6249
6250 len = min(eld[2], 21); /* 84 bytes of hw ELD buffer */
6251 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6252 for (i = 0; i < len; i++)
6253 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)(uintptr_t)(eld + i)));
6254
6255 i = I915_READ(aud_cntrl_st2);
6256 i |= eldv;
6257 I915_WRITE(aud_cntrl_st2, i);
6258
6259 }
6260
ironlake_write_eld(struct drm_connector * connector,struct drm_crtc * crtc)6261 static void ironlake_write_eld(struct drm_connector *connector,
6262 struct drm_crtc *crtc)
6263 {
6264 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6265 uint8_t *eld = connector->eld;
6266 uint32_t eldv;
6267 uint32_t i;
6268 int len;
6269 int hdmiw_hdmiedid;
6270 int aud_config;
6271 int aud_cntl_st;
6272 int aud_cntrl_st2;
6273 int pipe = to_intel_crtc(crtc)->pipe;
6274
6275 if (HAS_PCH_IBX(connector->dev)) {
6276 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6277 aud_config = IBX_AUD_CFG(pipe);
6278 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
6279 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
6280 } else {
6281 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6282 aud_config = CPT_AUD_CFG(pipe);
6283 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
6284 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
6285 }
6286
6287 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6288
6289 i = I915_READ(aud_cntl_st);
6290 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6291 if (!i) {
6292 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6293 /* operate blindly on all ports */
6294 eldv = IBX_ELD_VALIDB;
6295 eldv |= IBX_ELD_VALIDB << 4;
6296 eldv |= IBX_ELD_VALIDB << 8;
6297 } else {
6298 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
6299 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
6300 }
6301
6302 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6303 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6304 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6305 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6306 } else
6307 I915_WRITE(aud_config, 0);
6308
6309 if (intel_eld_uptodate(connector,
6310 aud_cntrl_st2, eldv,
6311 aud_cntl_st, IBX_ELD_ADDRESS,
6312 hdmiw_hdmiedid))
6313 return;
6314
6315 i = I915_READ(aud_cntrl_st2);
6316 i &= ~eldv;
6317 I915_WRITE(aud_cntrl_st2, i);
6318
6319 if (!eld[0])
6320 return;
6321
6322 i = I915_READ(aud_cntl_st);
6323 i &= ~IBX_ELD_ADDRESS;
6324 I915_WRITE(aud_cntl_st, i);
6325
6326 len = min(eld[2], 21); /* 84 bytes of hw ELD buffer */
6327 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6328 for (i = 0; i < len; i++)
6329 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)(uintptr_t)eld + i));
6330
6331 i = I915_READ(aud_cntrl_st2);
6332 i |= eldv;
6333 I915_WRITE(aud_cntrl_st2, i);
6334 }
6335
intel_write_eld(struct drm_encoder * encoder,struct drm_display_mode * mode)6336 void intel_write_eld(struct drm_encoder *encoder,
6337 struct drm_display_mode *mode)
6338 {
6339 struct drm_crtc *crtc = encoder->crtc;
6340 struct drm_connector *connector;
6341 struct drm_device *dev = encoder->dev;
6342 struct drm_i915_private *dev_priv = dev->dev_private;
6343
6344 connector = drm_select_eld(encoder, mode);
6345 if (!connector)
6346 return;
6347
6348 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6349 connector->base.id,
6350 drm_get_connector_name(connector),
6351 connector->encoder->base.id,
6352 drm_get_encoder_name(connector->encoder));
6353
6354 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6355
6356 if (dev_priv->display.write_eld)
6357 dev_priv->display.write_eld(connector, crtc);
6358 }
6359
6360 /** Loads the palette/gamma unit for the CRTC with the prepared values */
intel_crtc_load_lut(struct drm_crtc * crtc)6361 void intel_crtc_load_lut(struct drm_crtc *crtc)
6362 {
6363 struct drm_device *dev = crtc->dev;
6364 struct drm_i915_private *dev_priv = dev->dev_private;
6365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6366 enum pipe pipe = intel_crtc->pipe;
6367 int palreg = PALETTE(pipe);
6368 int i;
6369 bool reenable_ips = false;
6370
6371 /* The clocks have to be on to load the palette. */
6372 if (!crtc->enabled || !intel_crtc->active)
6373 return;
6374
6375 if (!HAS_PCH_SPLIT(dev_priv->dev))
6376 assert_pll_enabled(dev_priv, pipe);
6377
6378 /* use legacy palette for Ironlake */
6379 if (HAS_PCH_SPLIT(dev))
6380 palreg = LGC_PALETTE(pipe);
6381
6382 /* Workaround : Do not read or write the pipe palette/gamma data while
6383 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6384 */
6385 if (intel_crtc->config.ips_enabled &&
6386 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6387 GAMMA_MODE_MODE_SPLIT)) {
6388 hsw_disable_ips(intel_crtc);
6389 reenable_ips = true;
6390 }
6391
6392 for (i = 0; i < 256; i++) {
6393 I915_WRITE(palreg + 4 * i,
6394 (intel_crtc->lut_r[i] << 16) |
6395 (intel_crtc->lut_g[i] << 8) |
6396 intel_crtc->lut_b[i]);
6397 }
6398
6399 if (reenable_ips)
6400 hsw_enable_ips(intel_crtc);
6401 }
6402
i845_update_cursor(struct drm_crtc * crtc,u32 base)6403 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6404 {
6405 struct drm_device *dev = crtc->dev;
6406 struct drm_i915_private *dev_priv = dev->dev_private;
6407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6408 bool visible = base != 0;
6409 u32 cntl;
6410
6411 if (intel_crtc->cursor_visible == visible)
6412 return;
6413
6414 cntl = I915_READ(_CURACNTR);
6415 if (visible) {
6416 /* On these chipsets we can only modify the base whilst
6417 * the cursor is disabled.
6418 */
6419 I915_WRITE(_CURABASE, base);
6420
6421 cntl &= ~(CURSOR_FORMAT_MASK);
6422 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6423 cntl |= CURSOR_ENABLE |
6424 CURSOR_GAMMA_ENABLE |
6425 CURSOR_FORMAT_ARGB;
6426 } else
6427 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6428 I915_WRITE(_CURACNTR, cntl);
6429
6430 intel_crtc->cursor_visible = visible;
6431 }
6432
i9xx_update_cursor(struct drm_crtc * crtc,u32 base)6433 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6434 {
6435 struct drm_device *dev = crtc->dev;
6436 struct drm_i915_private *dev_priv = dev->dev_private;
6437 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6438 int pipe = intel_crtc->pipe;
6439 bool visible = base != 0;
6440
6441 if (intel_crtc->cursor_visible != visible) {
6442 uint32_t cntl = I915_READ(CURCNTR(pipe));
6443 if (base) {
6444 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6445 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6446 cntl |= pipe << 28; /* Connect to correct pipe */
6447 } else {
6448 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6449 cntl |= CURSOR_MODE_DISABLE;
6450 }
6451 I915_WRITE(CURCNTR(pipe), cntl);
6452
6453 intel_crtc->cursor_visible = visible;
6454 }
6455 /* and commit changes on next vblank */
6456 I915_WRITE(CURBASE(pipe), base);
6457 }
6458
ivb_update_cursor(struct drm_crtc * crtc,u32 base)6459 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6460 {
6461 struct drm_device *dev = crtc->dev;
6462 struct drm_i915_private *dev_priv = dev->dev_private;
6463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6464 int pipe = intel_crtc->pipe;
6465 bool visible = base != 0;
6466
6467 if (intel_crtc->cursor_visible != visible) {
6468 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6469 if (base) {
6470 cntl &= ~CURSOR_MODE;
6471 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6472 } else {
6473 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6474 cntl |= CURSOR_MODE_DISABLE;
6475 }
6476 if (IS_HASWELL(dev))
6477 cntl |= CURSOR_PIPE_CSC_ENABLE;
6478 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6479
6480 intel_crtc->cursor_visible = visible;
6481 }
6482 /* and commit changes on next vblank */
6483 I915_WRITE(CURBASE_IVB(pipe), base);
6484 }
6485
6486 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
intel_crtc_update_cursor(struct drm_crtc * crtc,bool on)6487 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6488 bool on)
6489 {
6490 struct drm_device *dev = crtc->dev;
6491 struct drm_i915_private *dev_priv = dev->dev_private;
6492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6493 int pipe = intel_crtc->pipe;
6494 int x = intel_crtc->cursor_x;
6495 int y = intel_crtc->cursor_y;
6496 u32 base, pos;
6497 bool visible;
6498
6499 pos = 0;
6500
6501 if (on && crtc->enabled && crtc->fb) {
6502 base = intel_crtc->cursor_addr;
6503 if (x > (int) crtc->fb->width)
6504 base = 0;
6505
6506 if (y > (int) crtc->fb->height)
6507 base = 0;
6508 } else
6509 base = 0;
6510
6511 if (x < 0) {
6512 if (x + intel_crtc->cursor_width < 0)
6513 base = 0;
6514
6515 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6516 x = -x;
6517 }
6518 pos |= x << CURSOR_X_SHIFT;
6519
6520 if (y < 0) {
6521 if (y + intel_crtc->cursor_height < 0)
6522 base = 0;
6523
6524 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6525 y = -y;
6526 }
6527 pos |= y << CURSOR_Y_SHIFT;
6528
6529 visible = base != 0;
6530 if (!visible && !intel_crtc->cursor_visible)
6531 return;
6532
6533 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6534 I915_WRITE(CURPOS_IVB(pipe), pos);
6535 ivb_update_cursor(crtc, base);
6536 } else {
6537 I915_WRITE(CURPOS(pipe), pos);
6538 if (IS_845G(dev) || IS_I865G(dev))
6539 i845_update_cursor(crtc, base);
6540 else
6541 i9xx_update_cursor(crtc, base);
6542 }
6543 }
6544
intel_crtc_cursor_set(struct drm_crtc * crtc,struct drm_file * file,uint32_t handle,uint32_t width,uint32_t height)6545 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6546 struct drm_file *file,
6547 uint32_t handle,
6548 uint32_t width, uint32_t height)
6549 {
6550 struct drm_device *dev = crtc->dev;
6551 struct drm_i915_private *dev_priv = dev->dev_private;
6552 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6553 struct drm_i915_gem_object *obj;
6554 uint32_t addr;
6555 int ret;
6556
6557 /* if we want to turn off the cursor ignore width and height */
6558 if (!handle) {
6559 DRM_DEBUG_KMS("cursor off\n");
6560 addr = 0;
6561 obj = NULL;
6562 mutex_lock(&dev->struct_mutex);
6563 goto finish;
6564 }
6565
6566 /* Currently we only support 64x64 cursors */
6567 if (width != 64 || height != 64) {
6568 DRM_ERROR("we currently only support 64x64 cursors\n");
6569 return -EINVAL;
6570 }
6571
6572 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6573 if (&obj->base == NULL)
6574 return -ENOENT;
6575
6576 if (obj->base.size < width * height * 4) {
6577 DRM_ERROR("buffer is to small\n");
6578 ret = -ENOMEM;
6579 goto fail;
6580 }
6581
6582 /* we only need to pin inside GTT if cursor is non-phy */
6583 mutex_lock(&dev->struct_mutex);
6584 if (!dev_priv->info->cursor_needs_physical) {
6585 unsigned alignment;
6586
6587 if (obj->tiling_mode) {
6588 DRM_ERROR("cursor cannot be tiled\n");
6589 ret = -EINVAL;
6590 goto fail_locked;
6591 }
6592
6593 /* Note that the w/a also requires 2 PTE of padding following
6594 * the bo. We currently fill all unused PTE with the shadow
6595 * page and so we should always have valid PTE following the
6596 * cursor preventing the VT-d warning.
6597 */
6598 alignment = 0;
6599 if (need_vtd_wa(dev))
6600 alignment = 64*1024;
6601
6602 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
6603 if (ret) {
6604 DRM_ERROR("failed to move cursor bo into the GTT\n");
6605 goto fail_locked;
6606 }
6607
6608 ret = i915_gem_object_put_fence(obj);
6609 if (ret) {
6610 DRM_ERROR("failed to release fence for cursor");
6611 goto fail_unpin;
6612 }
6613
6614 addr = obj->gtt_offset;
6615 obj->is_cursor = 1;
6616 } else {
6617 int align = IS_I830(dev) ? 16 * 1024 : 256;
6618 ret = i915_gem_attach_phys_object(dev, obj,
6619 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6620 align);
6621 if (ret) {
6622 DRM_ERROR("failed to attach phys object\n");
6623 goto fail_locked;
6624 }
6625 addr = obj->phys_obj->handle->paddr;
6626 }
6627
6628 if (IS_GEN2(dev))
6629 I915_WRITE(CURSIZE, (height << 12) | width);
6630
6631 finish:
6632 if (intel_crtc->cursor_bo) {
6633 if (dev_priv->info->cursor_needs_physical) {
6634 if (intel_crtc->cursor_bo != obj)
6635 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6636 } else
6637 i915_gem_object_unpin(intel_crtc->cursor_bo);
6638 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6639 }
6640
6641 mutex_unlock(&dev->struct_mutex);
6642
6643 intel_crtc->cursor_addr = addr;
6644 intel_crtc->cursor_bo = obj;
6645 intel_crtc->cursor_width = (int16_t)width;
6646 intel_crtc->cursor_height = (int16_t)height;
6647
6648 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6649
6650 return 0;
6651 fail_unpin:
6652 i915_gem_object_unpin(obj);
6653 fail_locked:
6654 mutex_unlock(&dev->struct_mutex);
6655 fail:
6656 drm_gem_object_unreference_unlocked(&obj->base);
6657 return ret;
6658 }
6659
intel_crtc_cursor_move(struct drm_crtc * crtc,int x,int y)6660 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6661 {
6662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6663
6664 intel_crtc->cursor_x = (int16_t)x;
6665 intel_crtc->cursor_y = (int16_t)y;
6666
6667 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
6668
6669 return 0;
6670 }
6671
6672 /** Sets the color ramps on behalf of RandR */
intel_crtc_fb_gamma_set(struct drm_crtc * crtc,u16 red,u16 green,u16 blue,int regno)6673 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6674 u16 blue, int regno)
6675 {
6676 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6677
6678 intel_crtc->lut_r[regno] = red >> 8;
6679 intel_crtc->lut_g[regno] = green >> 8;
6680 intel_crtc->lut_b[regno] = blue >> 8;
6681 }
6682
intel_crtc_fb_gamma_get(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,int regno)6683 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6684 u16 *blue, int regno)
6685 {
6686 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6687
6688 *red = intel_crtc->lut_r[regno] << 8;
6689 *green = intel_crtc->lut_g[regno] << 8;
6690 *blue = intel_crtc->lut_b[regno] << 8;
6691 }
6692
intel_crtc_gamma_set(struct drm_crtc * crtc,u16 * red,u16 * green,u16 * blue,uint32_t start,uint32_t size)6693 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6694 u16 *blue, uint32_t start, uint32_t size)
6695 {
6696 int end = (start + size > 256) ? 256 : start + size, i;
6697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6698
6699 for (i = start; i < end; i++) {
6700 intel_crtc->lut_r[i] = red[i] >> 8;
6701 intel_crtc->lut_g[i] = green[i] >> 8;
6702 intel_crtc->lut_b[i] = blue[i] >> 8;
6703 }
6704
6705 intel_crtc_load_lut(crtc);
6706 }
6707
6708 /* VESA 640x480x72Hz mode to set on the pipe */
6709 static struct drm_display_mode load_detect_mode = {
6710 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6711 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6712 };
6713
6714 static struct drm_framebuffer *
intel_framebuffer_create(struct drm_device * dev,struct drm_mode_fb_cmd2 * mode_cmd,struct drm_i915_gem_object * obj)6715 intel_framebuffer_create(struct drm_device *dev,
6716 struct drm_mode_fb_cmd2 *mode_cmd,
6717 struct drm_i915_gem_object *obj)
6718 {
6719 struct intel_framebuffer *intel_fb;
6720 int ret;
6721
6722 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6723 if (!intel_fb) {
6724 drm_gem_object_unreference_unlocked(&obj->base);
6725 return (NULL);
6726 }
6727
6728 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6729 if (ret) {
6730 drm_gem_object_unreference_unlocked(&obj->base);
6731 kfree(intel_fb, sizeof(struct intel_framebuffer));
6732 return (NULL);
6733 }
6734
6735 return &intel_fb->base;
6736 }
6737
6738 static u32
intel_framebuffer_pitch_for_width(int width,int bpp)6739 intel_framebuffer_pitch_for_width(int width, int bpp)
6740 {
6741 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6742 return ALIGN(pitch, 64);
6743 }
6744
6745 static u32
intel_framebuffer_size_for_mode(struct drm_display_mode * mode,int bpp)6746 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6747 {
6748 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6749 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6750 }
6751
6752 static struct drm_framebuffer *
intel_framebuffer_create_for_mode(struct drm_device * dev,struct drm_display_mode * mode,int depth,int bpp)6753 intel_framebuffer_create_for_mode(struct drm_device *dev,
6754 struct drm_display_mode *mode,
6755 int depth, int bpp)
6756 {
6757 struct drm_i915_gem_object *obj;
6758 struct drm_mode_fb_cmd2 mode_cmd;
6759
6760 obj = i915_gem_alloc_object(dev,
6761 intel_framebuffer_size_for_mode(mode, bpp));
6762 if (obj == NULL)
6763 return (NULL);
6764
6765 (void) memset(&mode_cmd, 0, sizeof(struct drm_mode_fb_cmd2));
6766
6767 mode_cmd.width = mode->hdisplay;
6768 mode_cmd.height = mode->vdisplay;
6769 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6770 bpp);
6771 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6772
6773 return intel_framebuffer_create(dev, &mode_cmd, obj);
6774 }
6775
6776 static struct drm_framebuffer *
mode_fits_in_fbdev(struct drm_device * dev,struct drm_display_mode * mode)6777 mode_fits_in_fbdev(struct drm_device *dev,
6778 struct drm_display_mode *mode)
6779 {
6780 struct drm_i915_private *dev_priv = dev->dev_private;
6781 struct drm_i915_gem_object *obj;
6782 struct drm_framebuffer *fb;
6783
6784 if (dev_priv->fbdev == NULL)
6785 return NULL;
6786
6787 obj = dev_priv->fbdev->ifb.obj;
6788 if (obj == NULL)
6789 return NULL;
6790
6791 fb = &dev_priv->fbdev->ifb.base;
6792 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6793 fb->bits_per_pixel))
6794 return NULL;
6795
6796 if (obj->base.size < mode->vdisplay * fb->pitches[0])
6797 return NULL;
6798
6799 return fb;
6800 }
6801
intel_get_load_detect_pipe(struct drm_connector * connector,struct drm_display_mode * mode,struct intel_load_detect_pipe * old)6802 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6803 struct drm_display_mode *mode,
6804 struct intel_load_detect_pipe *old)
6805 {
6806 struct intel_crtc *intel_crtc;
6807 struct intel_encoder *intel_encoder =
6808 intel_attached_encoder(connector);
6809 struct drm_crtc *possible_crtc;
6810 struct drm_encoder *encoder = &intel_encoder->base;
6811 struct drm_crtc *crtc = NULL;
6812 struct drm_device *dev = encoder->dev;
6813 struct drm_framebuffer *fb;
6814 int i = -1;
6815
6816 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6817 connector->base.id, drm_get_connector_name(connector),
6818 encoder->base.id, drm_get_encoder_name(encoder));
6819
6820 /*
6821 * Algorithm gets a little messy:
6822 *
6823 * - if the connector already has an assigned crtc, use it (but make
6824 * sure it's on first)
6825 *
6826 * - try to find the first unused crtc that can drive this connector,
6827 * and use that if we find one
6828 */
6829
6830 /* See if we already have a CRTC for this connector */
6831 if (encoder->crtc) {
6832 crtc = encoder->crtc;
6833
6834 mutex_lock(&crtc->mutex);
6835
6836 /* Make sure the crtc and connector are running */
6837 old->dpms_mode = connector->dpms;
6838 old->load_detect_temp = false;
6839
6840 /* Make sure the crtc and connector are running */
6841 if (connector->dpms != DRM_MODE_DPMS_ON)
6842 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6843
6844 return true;
6845 }
6846
6847 /* Find an unused one (if possible) */
6848 list_for_each_entry(possible_crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
6849 i++;
6850 if (!(encoder->possible_crtcs & (1 << i)))
6851 continue;
6852 if (!possible_crtc->enabled) {
6853 crtc = possible_crtc;
6854 break;
6855 }
6856 }
6857
6858 /*
6859 * If we didn't find an unused CRTC, don't use any.
6860 */
6861 if (!crtc) {
6862 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6863 return false;
6864 }
6865
6866 mutex_lock(&crtc->mutex);
6867 intel_encoder->new_crtc = to_intel_crtc(crtc);
6868 to_intel_connector(connector)->new_encoder = intel_encoder;
6869
6870 intel_crtc = to_intel_crtc(crtc);
6871 old->dpms_mode = connector->dpms;
6872 old->load_detect_temp = true;
6873 old->release_fb = NULL;
6874
6875 if (!mode)
6876 mode = &load_detect_mode;
6877
6878 /* We need a framebuffer large enough to accommodate all accesses
6879 * that the plane may generate whilst we perform load detection.
6880 * We can not rely on the fbcon either being present (we get called
6881 * during its initialisation to detect all boot displays, or it may
6882 * not even exist) or that it is large enough to satisfy the
6883 * requested mode.
6884 */
6885 fb = mode_fits_in_fbdev(dev, mode);
6886 if (fb == NULL) {
6887 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6888 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6889 old->release_fb = fb;
6890 } else
6891 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6892 if (IS_ERR(fb)) {
6893 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6894 mutex_unlock(&crtc->mutex);
6895 return false;
6896 }
6897
6898 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6899 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6900 if (old->release_fb)
6901 old->release_fb->funcs->destroy(old->release_fb);
6902 mutex_unlock(&crtc->mutex);
6903 return false;
6904 }
6905
6906 /* let the connector get through one full cycle before testing */
6907 intel_wait_for_vblank(dev, intel_crtc->pipe);
6908 return true;
6909 }
6910
intel_release_load_detect_pipe(struct drm_connector * connector,struct intel_load_detect_pipe * old)6911 void intel_release_load_detect_pipe(struct drm_connector *connector,
6912 struct intel_load_detect_pipe *old)
6913 {
6914 struct intel_encoder *intel_encoder =
6915 intel_attached_encoder(connector);
6916 struct drm_encoder *encoder = &intel_encoder->base;
6917 struct drm_crtc *crtc = encoder->crtc;
6918
6919 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6920 connector->base.id, drm_get_connector_name(connector),
6921 encoder->base.id, drm_get_encoder_name(encoder));
6922
6923 if (old->load_detect_temp) {
6924 to_intel_connector(connector)->new_encoder = NULL;
6925 intel_encoder->new_crtc = NULL;
6926 intel_set_mode(crtc, NULL, 0, 0, NULL);
6927
6928 if (old->release_fb) {
6929 drm_framebuffer_unregister_private(old->release_fb);
6930 drm_framebuffer_unreference(old->release_fb);
6931 }
6932
6933 mutex_unlock(&crtc->mutex);
6934 return;
6935 }
6936
6937 /* Switch crtc and encoder back off if necessary */
6938 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6939 connector->funcs->dpms(connector, old->dpms_mode);
6940
6941 mutex_unlock(&crtc->mutex);
6942 }
6943
6944 /* Returns the clock of the currently programmed mode of the given pipe. */
intel_crtc_clock_get(struct drm_device * dev,struct drm_crtc * crtc)6945 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6946 {
6947 struct drm_i915_private *dev_priv = dev->dev_private;
6948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6949 int pipe = intel_crtc->pipe;
6950 u32 dpll = I915_READ(DPLL(pipe));
6951 u32 fp;
6952 intel_clock_t clock;
6953
6954 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6955 fp = I915_READ(FP0(pipe));
6956 else
6957 fp = I915_READ(FP1(pipe));
6958
6959 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6960 if (IS_PINEVIEW(dev)) {
6961 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6962 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6963 } else {
6964 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6965 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6966 }
6967
6968 if (!IS_GEN2(dev)) {
6969 if (IS_PINEVIEW(dev))
6970 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6971 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6972 else
6973 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6974 DPLL_FPA01_P1_POST_DIV_SHIFT);
6975
6976 switch (dpll & DPLL_MODE_MASK) {
6977 case DPLLB_MODE_DAC_SERIAL:
6978 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6979 5 : 10;
6980 break;
6981 case DPLLB_MODE_LVDS:
6982 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6983 7 : 14;
6984 break;
6985 default:
6986 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6987 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6988 return 0;
6989 }
6990
6991 if (IS_PINEVIEW(dev))
6992 pineview_clock(96000, &clock);
6993 else
6994 i9xx_clock(96000, &clock);
6995 } else {
6996 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6997
6998 if (is_lvds) {
6999 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7000 DPLL_FPA01_P1_POST_DIV_SHIFT);
7001 clock.p2 = 14;
7002
7003 if ((dpll & PLL_REF_INPUT_MASK) ==
7004 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
7005 /* XXX: might not be 66MHz */
7006 i9xx_clock(66000, &clock);
7007 } else
7008 i9xx_clock(48000, &clock);
7009 } else {
7010 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7011 clock.p1 = 2;
7012 else {
7013 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7014 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7015 }
7016 if (dpll & PLL_P2_DIVIDE_BY_4)
7017 clock.p2 = 4;
7018 else
7019 clock.p2 = 2;
7020
7021 i9xx_clock(48000, &clock);
7022 }
7023 }
7024
7025 /* XXX: It would be nice to validate the clocks, but we can't reuse
7026 * i830PllIsValid() because it relies on the xf86_config connector
7027 * configuration being accurate, which it isn't necessarily.
7028 */
7029
7030 return clock.dot;
7031 }
7032
7033 /** Returns the currently programmed mode of the given pipe. */
intel_crtc_mode_get(struct drm_device * dev,struct drm_crtc * crtc)7034 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7035 struct drm_crtc *crtc)
7036 {
7037 struct drm_i915_private *dev_priv = dev->dev_private;
7038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7039 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
7040 struct drm_display_mode *mode;
7041 int htot = I915_READ(HTOTAL(cpu_transcoder));
7042 int hsync = I915_READ(HSYNC(cpu_transcoder));
7043 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7044 int vsync = I915_READ(VSYNC(cpu_transcoder));
7045
7046 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7047 if (!mode)
7048 return NULL;
7049
7050 mode->clock = intel_crtc_clock_get(dev, crtc);
7051 mode->hdisplay = (htot & 0xffff) + 1;
7052 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7053 mode->hsync_start = (hsync & 0xffff) + 1;
7054 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7055 mode->vdisplay = (vtot & 0xffff) + 1;
7056 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7057 mode->vsync_start = (vsync & 0xffff) + 1;
7058 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7059
7060 drm_mode_set_name(mode);
7061
7062 return mode;
7063 }
7064
intel_increase_pllclock(struct drm_crtc * crtc)7065 void intel_increase_pllclock(struct drm_crtc *crtc)
7066 {
7067 struct drm_device *dev = crtc->dev;
7068 drm_i915_private_t *dev_priv = dev->dev_private;
7069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7070 int pipe = intel_crtc->pipe;
7071 int dpll_reg = DPLL(pipe);
7072 int dpll;
7073
7074 if (HAS_PCH_SPLIT(dev))
7075 return;
7076
7077 if (!dev_priv->lvds_downclock_avail)
7078 return;
7079
7080 dpll = I915_READ(dpll_reg);
7081 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
7082 DRM_DEBUG_DRIVER("upclocking LVDS\n");
7083
7084 assert_panel_unlocked(dev_priv, pipe);
7085
7086 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7087 I915_WRITE(dpll_reg, dpll);
7088 intel_wait_for_vblank(dev, pipe);
7089
7090 dpll = I915_READ(dpll_reg);
7091 if (dpll & DISPLAY_RATE_SELECT_FPA1)
7092 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
7093 }
7094 }
7095
intel_decrease_pllclock(struct drm_crtc * crtc)7096 static void intel_decrease_pllclock(struct drm_crtc *crtc)
7097 {
7098 struct drm_device *dev = crtc->dev;
7099 drm_i915_private_t *dev_priv = dev->dev_private;
7100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7101
7102 if (HAS_PCH_SPLIT(dev))
7103 return;
7104
7105 if (!dev_priv->lvds_downclock_avail)
7106 return;
7107
7108 /*
7109 * Since this is called by a timer, we should never get here in
7110 * the manual case.
7111 */
7112 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
7113 int pipe = intel_crtc->pipe;
7114 int dpll_reg = DPLL(pipe);
7115 int dpll;
7116
7117 DRM_DEBUG_DRIVER("downclocking LVDS\n");
7118
7119 assert_panel_unlocked(dev_priv, pipe);
7120
7121 dpll = I915_READ(dpll_reg);
7122 dpll |= DISPLAY_RATE_SELECT_FPA1;
7123 I915_WRITE(dpll_reg, dpll);
7124 intel_wait_for_vblank(dev, pipe);
7125 dpll = I915_READ(dpll_reg);
7126 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
7127 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
7128 }
7129
7130 }
7131
intel_mark_busy(struct drm_device * dev)7132 void intel_mark_busy(struct drm_device *dev)
7133 {
7134 }
7135
intel_mark_idle(struct drm_device * dev)7136 void intel_mark_idle(struct drm_device *dev)
7137 {
7138 struct drm_crtc *crtc;
7139
7140 if (!i915_powersave)
7141 return;
7142
7143 list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
7144 if (!crtc->fb)
7145 continue;
7146
7147 intel_decrease_pllclock(crtc);
7148 }
7149 }
7150
intel_mark_fb_busy(struct drm_i915_gem_object * obj,struct intel_ring_buffer * ring)7151 void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7152 struct intel_ring_buffer *ring)
7153 {
7154 struct drm_device *dev = obj->base.dev;
7155 struct drm_crtc *crtc;
7156
7157 if (!i915_powersave)
7158 return;
7159
7160 list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
7161 if (!crtc->fb)
7162 continue;
7163
7164 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7165 continue;
7166
7167 intel_increase_pllclock(crtc);
7168 if (ring && intel_fbc_enabled(dev))
7169 ring->fbc_dirty = true;
7170 }
7171 }
7172
intel_crtc_destroy(struct drm_crtc * crtc)7173 static void intel_crtc_destroy(struct drm_crtc *crtc)
7174 {
7175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7176 struct drm_device *dev = crtc->dev;
7177 drm_i915_private_t *dev_priv = dev->dev_private;
7178 struct intel_unpin_work *work;
7179 unsigned long flags;
7180
7181 spin_lock_irqsave(&dev->event_lock, flags);
7182 work = intel_crtc->unpin_work;
7183 intel_crtc->unpin_work = NULL;
7184 spin_unlock_irqrestore(&dev->event_lock, flags);
7185
7186 if (work) {
7187 cancel_delayed_work(dev_priv->other_wq);
7188 kfree(work, sizeof(*work));
7189 }
7190
7191 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7192
7193 drm_crtc_cleanup(crtc);
7194
7195 kfree(intel_crtc, sizeof (struct intel_crtc) +
7196 (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)));
7197 }
7198
intel_unpin_work_fn(struct work_struct * __work)7199 static void intel_unpin_work_fn(struct work_struct *__work)
7200 {
7201 struct intel_unpin_work *work =
7202 container_of(__work, struct intel_unpin_work, work);
7203 struct drm_device *dev = work->crtc->dev;
7204
7205 mutex_lock(&dev->struct_mutex);
7206 intel_unpin_fb_obj(work->old_fb_obj);
7207 drm_gem_object_unreference(&work->pending_flip_obj->base);
7208 drm_gem_object_unreference(&work->old_fb_obj->base);
7209
7210 intel_update_fbc(dev);
7211 mutex_unlock(&dev->struct_mutex);
7212
7213 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7214 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7215 kfree(work, sizeof(struct intel_unpin_work));
7216 }
7217
do_intel_finish_page_flip(struct drm_device * dev,struct drm_crtc * crtc)7218 static void do_intel_finish_page_flip(struct drm_device *dev,
7219 struct drm_crtc *crtc)
7220 {
7221 drm_i915_private_t *dev_priv = dev->dev_private;
7222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7223 struct intel_unpin_work *work;
7224 unsigned long flags;
7225
7226 /* Ignore early vblank irqs */
7227 if (intel_crtc == NULL)
7228 return;
7229
7230 spin_lock_irqsave(&dev->event_lock, flags);
7231 work = intel_crtc->unpin_work;
7232 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
7233 spin_unlock_irqrestore(&dev->event_lock, flags);
7234 return;
7235 }
7236
7237 intel_crtc->unpin_work = NULL;
7238
7239 if (work->event) {
7240 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
7241
7242 pollwakeup(&work->event->base.file_priv->drm_pollhead, POLLIN | POLLRDNORM);
7243 }
7244 drm_vblank_put(dev, intel_crtc->pipe);
7245
7246 spin_unlock_irqrestore(&dev->event_lock, flags);
7247
7248 DRM_WAKEUP(&dev_priv->pending_flip_queue);
7249
7250 (void) queue_work(dev_priv->wq, &work->work);
7251
7252 }
7253
intel_finish_page_flip(struct drm_device * dev,int pipe)7254 void intel_finish_page_flip(struct drm_device *dev, int pipe)
7255 {
7256 drm_i915_private_t *dev_priv = dev->dev_private;
7257 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7258
7259 do_intel_finish_page_flip(dev, crtc);
7260 }
7261
intel_finish_page_flip_plane(struct drm_device * dev,int plane)7262 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7263 {
7264 drm_i915_private_t *dev_priv = dev->dev_private;
7265 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7266
7267 do_intel_finish_page_flip(dev, crtc);
7268 }
7269
intel_prepare_page_flip(struct drm_device * dev,int plane)7270 void intel_prepare_page_flip(struct drm_device *dev, int plane)
7271 {
7272 drm_i915_private_t *dev_priv = dev->dev_private;
7273 struct intel_crtc *intel_crtc =
7274 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7275 unsigned long flags;
7276
7277 /* NB: An MMIO update of the plane base pointer will also
7278 * generate a page-flip completion irq, i.e. every modeset
7279 * is also accompanied by a spurious intel_prepare_page_flip().
7280 */
7281 spin_lock_irqsave(&dev->event_lock, flags);
7282 if (intel_crtc->unpin_work)
7283 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
7284 spin_unlock_irqrestore(&dev->event_lock, flags);
7285 }
7286
intel_mark_page_flip_active(struct intel_crtc * intel_crtc)7287 inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7288 {
7289 /* Ensure that the work item is consistent when activating it ... */
7290 membar_producer();
7291 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7292 /* and that it is marked active as soon as the irq could fire. */
7293 membar_producer();
7294 }
7295
intel_gen2_queue_flip(struct drm_device * dev,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj)7296 static int intel_gen2_queue_flip(struct drm_device *dev,
7297 struct drm_crtc *crtc,
7298 struct drm_framebuffer *fb,
7299 struct drm_i915_gem_object *obj)
7300 {
7301 struct drm_i915_private *dev_priv = dev->dev_private;
7302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7303 u32 flip_mask;
7304 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7305 int ret;
7306
7307 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7308 if (ret)
7309 goto err;
7310
7311 ret = intel_ring_begin(ring, 6);
7312 if (ret)
7313 goto err_unpin;
7314
7315 /* Can't queue multiple flips, so wait for the previous
7316 * one to finish before executing the next.
7317 */
7318 if (intel_crtc->plane)
7319 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7320 else
7321 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7322 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7323 intel_ring_emit(ring, MI_NOOP);
7324 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7325 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7326 intel_ring_emit(ring, fb->pitches[0]);
7327 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7328 intel_ring_emit(ring, 0); /* aux display base address, unused */
7329
7330 intel_mark_page_flip_active(intel_crtc);
7331 intel_ring_advance(ring);
7332 return 0;
7333
7334 err_unpin:
7335 intel_unpin_fb_obj(obj);
7336 err:
7337 return ret;
7338 }
7339
intel_gen3_queue_flip(struct drm_device * dev,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj)7340 static int intel_gen3_queue_flip(struct drm_device *dev,
7341 struct drm_crtc *crtc,
7342 struct drm_framebuffer *fb,
7343 struct drm_i915_gem_object *obj)
7344 {
7345 struct drm_i915_private *dev_priv = dev->dev_private;
7346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7347 u32 flip_mask;
7348 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7349 int ret;
7350
7351 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7352 if (ret)
7353 goto err;
7354
7355 ret = intel_ring_begin(ring, 6);
7356 if (ret)
7357 goto err_unpin;
7358
7359 if (intel_crtc->plane)
7360 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7361 else
7362 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7363 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7364 intel_ring_emit(ring, MI_NOOP);
7365 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7366 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7367 intel_ring_emit(ring, fb->pitches[0]);
7368 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7369 intel_ring_emit(ring, MI_NOOP);
7370
7371 intel_mark_page_flip_active(intel_crtc);
7372 intel_ring_advance(ring);
7373 return 0;
7374
7375 err_unpin:
7376 intel_unpin_fb_obj(obj);
7377 err:
7378 return ret;
7379 }
7380
intel_gen4_queue_flip(struct drm_device * dev,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj)7381 static int intel_gen4_queue_flip(struct drm_device *dev,
7382 struct drm_crtc *crtc,
7383 struct drm_framebuffer *fb,
7384 struct drm_i915_gem_object *obj)
7385 {
7386 struct drm_i915_private *dev_priv = dev->dev_private;
7387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7388 uint32_t pf, pipesrc;
7389 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7390 int ret;
7391
7392 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7393 if (ret)
7394 goto err;
7395
7396 ret = intel_ring_begin(ring, 4);
7397 if (ret)
7398 goto err_unpin;
7399
7400 /* i965+ uses the linear or tiled offsets from the
7401 * Display Registers (which do not change across a page-flip)
7402 * so we need only reprogram the base address.
7403 */
7404 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7405 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7406 intel_ring_emit(ring, fb->pitches[0]);
7407 intel_ring_emit(ring,
7408 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7409 obj->tiling_mode);
7410
7411 /* XXX Enabling the panel-fitter across page-flip is so far
7412 * untested on non-native modes, so ignore it for now.
7413 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7414 */
7415 pf = 0;
7416 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7417 intel_ring_emit(ring, pf | pipesrc);
7418
7419 intel_mark_page_flip_active(intel_crtc);
7420 intel_ring_advance(ring);
7421 return 0;
7422
7423 err_unpin:
7424 intel_unpin_fb_obj(obj);
7425 err:
7426 return ret;
7427 }
7428
intel_gen6_queue_flip(struct drm_device * dev,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj)7429 static int intel_gen6_queue_flip(struct drm_device *dev,
7430 struct drm_crtc *crtc,
7431 struct drm_framebuffer *fb,
7432 struct drm_i915_gem_object *obj)
7433 {
7434 struct drm_i915_private *dev_priv = dev->dev_private;
7435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7436 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
7437 uint32_t pf, pipesrc;
7438 int ret;
7439
7440 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7441 if (ret)
7442 goto err;
7443
7444 ret = intel_ring_begin(ring, 4);
7445 if (ret)
7446 goto err_unpin;
7447
7448 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7449 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7450 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7451 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7452
7453 /* Contrary to the suggestions in the documentation,
7454 * "Enable Panel Fitter" does not seem to be required when page
7455 * flipping with a non-native mode, and worse causes a normal
7456 * modeset to fail.
7457 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7458 */
7459 pf = 0;
7460 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7461 intel_ring_emit(ring, pf | pipesrc);
7462
7463 intel_mark_page_flip_active(intel_crtc);
7464 intel_ring_advance(ring);
7465 return 0;
7466
7467 err_unpin:
7468 intel_unpin_fb_obj(obj);
7469 err:
7470 return ret;
7471 }
7472
7473 /*
7474 * On gen7 we currently use the blit ring because (in early silicon at least)
7475 * the render ring doesn't give us interrpts for page flip completion, which
7476 * means clients will hang after the first flip is queued. Fortunately the
7477 * blit ring generates interrupts properly, so use it instead.
7478 */
intel_gen7_queue_flip(struct drm_device * dev,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj)7479 static int intel_gen7_queue_flip(struct drm_device *dev,
7480 struct drm_crtc *crtc,
7481 struct drm_framebuffer *fb,
7482 struct drm_i915_gem_object *obj)
7483 {
7484 struct drm_i915_private *dev_priv = dev->dev_private;
7485 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7486 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7487 uint32_t plane_bit = 0;
7488 int ret;
7489
7490 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7491 if (ret)
7492 goto err;
7493
7494 switch(intel_crtc->plane) {
7495 case PLANE_A:
7496 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7497 break;
7498 case PLANE_B:
7499 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7500 break;
7501 case PLANE_C:
7502 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7503 break;
7504 default:
7505 DRM_ERROR("unknown plane in flip command\n");
7506 ret = -ENODEV;
7507 goto err_unpin;
7508 }
7509
7510 ret = intel_ring_begin(ring, 4);
7511 if (ret)
7512 goto err_unpin;
7513
7514 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7515 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7516 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7517 intel_ring_emit(ring, (MI_NOOP));
7518
7519 intel_mark_page_flip_active(intel_crtc);
7520 intel_ring_advance(ring);
7521 return 0;
7522
7523 err_unpin:
7524 intel_unpin_fb_obj(obj);
7525 err:
7526 return ret;
7527 }
7528
intel_default_queue_flip(struct drm_device * dev,struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_i915_gem_object * obj)7529 static int intel_default_queue_flip(struct drm_device *dev,
7530 struct drm_crtc *crtc,
7531 struct drm_framebuffer *fb,
7532 struct drm_i915_gem_object *obj)
7533 {
7534 return -ENODEV;
7535 }
7536
intel_crtc_page_flip(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_pending_vblank_event * event)7537 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7538 struct drm_framebuffer *fb,
7539 struct drm_pending_vblank_event *event)
7540 {
7541 struct drm_device *dev = crtc->dev;
7542 struct drm_i915_private *dev_priv = dev->dev_private;
7543 struct drm_framebuffer *old_fb = crtc->fb;
7544 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
7545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7546 struct intel_unpin_work *work;
7547 unsigned long flags;
7548 int ret;
7549
7550 /* Can't change pixel format via MI display flips. */
7551 if (fb->pixel_format != crtc->fb->pixel_format)
7552 return -EINVAL;
7553
7554 /*
7555 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7556 * Note that pitch changes could also affect these register.
7557 */
7558 if (INTEL_INFO(dev)->gen > 3 &&
7559 (fb->offsets[0] != crtc->fb->offsets[0] ||
7560 fb->pitches[0] != crtc->fb->pitches[0]))
7561 return -EINVAL;
7562
7563 work = kzalloc(sizeof *work, GFP_KERNEL);
7564 if (work == NULL)
7565 return -ENOMEM;
7566
7567 work->event = event;
7568 work->crtc = crtc;
7569 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
7570 INIT_WORK(&work->work, intel_unpin_work_fn);
7571
7572 ret = drm_vblank_get(dev, intel_crtc->pipe);
7573 if (ret)
7574 goto free_work;
7575
7576 /* We borrow the event spin lock for protecting unpin_work */
7577 spin_lock_irqsave(&dev->event_lock, flags);
7578 if (intel_crtc->unpin_work) {
7579 spin_unlock_irqrestore(&dev->event_lock, flags);
7580 kfree(work, sizeof(struct intel_unpin_work));
7581 drm_vblank_put(dev, intel_crtc->pipe);
7582
7583 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7584 return -EBUSY;
7585 }
7586 intel_crtc->unpin_work = work;
7587 spin_unlock_irqrestore(&dev->event_lock, flags);
7588
7589 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7590 flush_workqueue(dev_priv->wq);
7591
7592 mutex_lock(&dev->struct_mutex);
7593
7594 /* Reference the objects for the scheduled work. */
7595 drm_gem_object_reference(&work->old_fb_obj->base);
7596 drm_gem_object_reference(&obj->base);
7597
7598 crtc->fb = fb;
7599
7600 work->pending_flip_obj = obj;
7601 work->enable_stall_check = true;
7602
7603 atomic_inc(&intel_crtc->unpin_work_count);
7604 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
7605
7606 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7607 if (ret)
7608 goto cleanup_pending;
7609
7610 intel_disable_fbc(dev);
7611 intel_mark_fb_busy(obj, NULL);
7612 mutex_unlock(&dev->struct_mutex);
7613
7614 return 0;
7615
7616 cleanup_pending:
7617 atomic_dec(&intel_crtc->unpin_work_count);
7618 crtc->fb = old_fb;
7619 drm_gem_object_unreference(&work->old_fb_obj->base);
7620 drm_gem_object_unreference(&obj->base);
7621 mutex_unlock(&dev->struct_mutex);
7622
7623 spin_lock_irqsave(&dev->event_lock, flags);
7624 intel_crtc->unpin_work = NULL;
7625 spin_unlock_irqrestore(&dev->event_lock, flags);
7626
7627 drm_vblank_put(dev, intel_crtc->pipe);
7628 free_work:
7629 kfree(work, sizeof(struct intel_unpin_work));
7630
7631 return ret;
7632 }
7633
7634 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7635 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7636 .load_lut = intel_crtc_load_lut,
7637 };
7638
intel_encoder_crtc_ok(struct drm_encoder * encoder,struct drm_crtc * crtc)7639 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7640 struct drm_crtc *crtc)
7641 {
7642 struct drm_device *dev;
7643 struct drm_crtc *tmp;
7644 int crtc_mask = 1;
7645
7646 ASSERT(crtc);
7647
7648 dev = crtc->dev;
7649
7650 list_for_each_entry(tmp, struct drm_crtc, &dev->mode_config.crtc_list, head) {
7651 if (tmp == crtc)
7652 break;
7653 crtc_mask <<= 1;
7654 }
7655
7656 if (encoder->possible_crtcs & crtc_mask)
7657 return true;
7658 return false;
7659 }
7660
7661 /**
7662 * intel_modeset_update_staged_output_state
7663 *
7664 * Updates the staged output configuration state, e.g. after we've read out the
7665 * current hw state.
7666 */
intel_modeset_update_staged_output_state(struct drm_device * dev)7667 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7668 {
7669 struct intel_encoder *encoder;
7670 struct intel_connector *connector;
7671
7672 list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
7673 base.head) {
7674 connector->new_encoder =
7675 to_intel_encoder(connector->base.encoder);
7676 }
7677
7678 list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
7679 base.head) {
7680 encoder->new_crtc =
7681 to_intel_crtc(encoder->base.crtc);
7682 }
7683 }
7684
7685 /**
7686 * intel_modeset_commit_output_state
7687 *
7688 * This function copies the stage display pipe configuration to the real one.
7689 */
intel_modeset_commit_output_state(struct drm_device * dev)7690 static void intel_modeset_commit_output_state(struct drm_device *dev)
7691 {
7692 struct intel_encoder *encoder;
7693 struct intel_connector *connector;
7694
7695 list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
7696 base.head) {
7697 connector->base.encoder = &connector->new_encoder->base;
7698 }
7699
7700 list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
7701 base.head) {
7702 encoder->base.crtc = &encoder->new_crtc->base;
7703 }
7704 }
7705
7706 static void
connected_sink_compute_bpp(struct intel_connector * connector,struct intel_crtc_config * pipe_config)7707 connected_sink_compute_bpp(struct intel_connector * connector,
7708 struct intel_crtc_config *pipe_config)
7709 {
7710 int bpp = pipe_config->pipe_bpp;
7711
7712 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7713 connector->base.base.id,
7714 drm_get_connector_name(&connector->base));
7715
7716 /* Don't use an invalid EDID bpc value */
7717 if (connector->base.display_info.bpc &&
7718 connector->base.display_info.bpc * 3 < bpp) {
7719 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7720 bpp, connector->base.display_info.bpc*3);
7721 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7722 }
7723
7724 /* Clamp bpp to 8 on screens without EDID 1.4 */
7725 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7726 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7727 bpp);
7728 pipe_config->pipe_bpp = 24;
7729 }
7730 }
7731
7732 static int
compute_baseline_pipe_bpp(struct intel_crtc * crtc,struct drm_framebuffer * fb,struct intel_crtc_config * pipe_config)7733 compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7734 struct drm_framebuffer *fb,
7735 struct intel_crtc_config *pipe_config)
7736 {
7737 struct drm_device *dev = crtc->base.dev;
7738 struct intel_connector *connector;
7739 int bpp;
7740
7741 switch (fb->pixel_format) {
7742 case DRM_FORMAT_C8:
7743 bpp = 8*3; /* since we go through a colormap */
7744 break;
7745 case DRM_FORMAT_XRGB1555:
7746 case DRM_FORMAT_ARGB1555:
7747 /* checked in intel_framebuffer_init already */
7748 if (INTEL_INFO(dev)->gen > 3)
7749 return -EINVAL;
7750 /* FALLTHROUGH */
7751 case DRM_FORMAT_RGB565:
7752 bpp = 6*3; /* min is 18bpp */
7753 break;
7754 case DRM_FORMAT_XBGR8888:
7755 case DRM_FORMAT_ABGR8888:
7756 /* checked in intel_framebuffer_init already */
7757 if (INTEL_INFO(dev)->gen < 4)
7758 return -EINVAL;
7759 /* FALLTHROUGH */
7760 case DRM_FORMAT_XRGB8888:
7761 case DRM_FORMAT_ARGB8888:
7762 bpp = 8*3;
7763 break;
7764 case DRM_FORMAT_XRGB2101010:
7765 case DRM_FORMAT_ARGB2101010:
7766 case DRM_FORMAT_XBGR2101010:
7767 case DRM_FORMAT_ABGR2101010:
7768 /* checked in intel_framebuffer_init already */
7769 if (INTEL_INFO(dev)->gen < 4)
7770 return -EINVAL;
7771 bpp = 10*3;
7772 break;
7773 /* TODO: gen4+ supports 16 bpc floating point, too. */
7774 default:
7775 DRM_DEBUG_KMS("unsupported depth\n");
7776 return -EINVAL;
7777 }
7778
7779 pipe_config->pipe_bpp = bpp;
7780
7781 /* Clamp display bpp to EDID value */
7782 list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
7783 base.head) {
7784 if (!connector->new_encoder ||
7785 connector->new_encoder->new_crtc != crtc)
7786 continue;
7787
7788 connected_sink_compute_bpp(connector, pipe_config);
7789 }
7790
7791 return bpp;
7792 }
7793
intel_dump_pipe_config(struct intel_crtc * crtc,struct intel_crtc_config * pipe_config,const char * context)7794 static void intel_dump_pipe_config(struct intel_crtc *crtc,
7795 struct intel_crtc_config *pipe_config,
7796 const char *context)
7797 {
7798 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7799 context, pipe_name(crtc->pipe));
7800
7801 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7802 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7803 pipe_config->pipe_bpp, pipe_config->dither);
7804 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7805 pipe_config->has_pch_encoder,
7806 pipe_config->fdi_lanes,
7807 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7808 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7809 pipe_config->fdi_m_n.tu);
7810 DRM_DEBUG_KMS("requested mode:\n");
7811 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7812 DRM_DEBUG_KMS("adjusted mode:\n");
7813 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7814 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7815 pipe_config->gmch_pfit.control,
7816 pipe_config->gmch_pfit.pgm_ratios,
7817 pipe_config->gmch_pfit.lvds_border_bits);
7818 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7819 pipe_config->pch_pfit.pos,
7820 pipe_config->pch_pfit.size);
7821 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
7822 }
7823
check_encoder_cloning(struct drm_crtc * crtc)7824 static bool check_encoder_cloning(struct drm_crtc *crtc)
7825 {
7826 int num_encoders = 0;
7827 bool uncloneable_encoders = false;
7828 struct intel_encoder *encoder;
7829
7830 list_for_each_entry(encoder, struct intel_encoder, &crtc->dev->mode_config.encoder_list,
7831 base.head) {
7832 if (&encoder->new_crtc->base != crtc)
7833 continue;
7834
7835 num_encoders++;
7836 if (!encoder->cloneable)
7837 uncloneable_encoders = true;
7838 }
7839
7840 return !(num_encoders > 1 && uncloneable_encoders);
7841 }
7842
7843 static struct intel_crtc_config *
intel_modeset_pipe_config(struct drm_crtc * crtc,struct drm_framebuffer * fb,struct drm_display_mode * mode)7844 intel_modeset_pipe_config(struct drm_crtc *crtc,
7845 struct drm_framebuffer *fb,
7846 struct drm_display_mode *mode)
7847 {
7848 struct drm_device *dev = crtc->dev;
7849 struct drm_encoder_helper_funcs *encoder_funcs;
7850 struct intel_encoder *encoder;
7851 struct intel_crtc_config *pipe_config;
7852 int plane_bpp, ret = -EINVAL;
7853 bool retry = true;
7854
7855 if (!check_encoder_cloning(crtc)) {
7856 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7857 return NULL;
7858 }
7859
7860 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7861 if (!pipe_config)
7862 return NULL;
7863
7864 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7865 drm_mode_copy(&pipe_config->requested_mode, mode);
7866 pipe_config->cpu_transcoder = (enum transcoder)to_intel_crtc(crtc)->pipe;
7867 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
7868
7869 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7870 * plane pixel format and any sink constraints into account. Returns the
7871 * source plane bpp so that dithering can be selected on mismatches
7872 * after encoders and crtc also have had their say. */
7873 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7874 fb, pipe_config);
7875 if (plane_bpp < 0)
7876 goto fail;
7877
7878 encoder_retry:
7879 /* Ensure the port clock defaults are reset when retrying. */
7880 pipe_config->port_clock = 0;
7881 pipe_config->pixel_multiplier = 1;
7882
7883 /* Pass our mode to the connectors and the CRTC to give them a chance to
7884 * adjust it according to limitations or connector properties, and also
7885 * a chance to reject the mode entirely.
7886 */
7887 list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
7888 base.head) {
7889
7890 if (&encoder->new_crtc->base != crtc)
7891 continue;
7892
7893 if (encoder->compute_config) {
7894 if (!(encoder->compute_config(encoder, pipe_config))) {
7895 DRM_DEBUG_KMS("Encoder config failure\n");
7896 goto fail;
7897 }
7898
7899 continue;
7900 }
7901
7902 encoder_funcs = encoder->base.helper_private;
7903 if (!(encoder_funcs->mode_fixup(&encoder->base,
7904 &pipe_config->requested_mode,
7905 &pipe_config->adjusted_mode))) {
7906 DRM_DEBUG_KMS("Encoder fixup failed\n");
7907 goto fail;
7908 }
7909 }
7910
7911 /* Set default port clock if not overwritten by the encoder. Needs to be
7912 * done afterwards in case the encoder adjusts the mode. */
7913 if (!pipe_config->port_clock)
7914 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7915
7916 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
7917 if (ret < 0) {
7918 DRM_DEBUG_KMS("CRTC fixup failed\n");
7919 goto fail;
7920 }
7921
7922 if (ret == RETRY) {
7923 if (!retry) {
7924 DRM_ERROR("loop in pipe configuration computation");
7925 ret = -EINVAL;
7926 goto fail;
7927 }
7928
7929 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7930 retry = false;
7931 goto encoder_retry;
7932 }
7933
7934 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7935 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7936 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7937
7938 return pipe_config;
7939 fail:
7940 kfree(pipe_config, sizeof(*pipe_config));
7941 return NULL;
7942 }
7943
7944 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7945 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7946 static void
intel_modeset_affected_pipes(struct drm_crtc * crtc,unsigned * modeset_pipes,unsigned * prepare_pipes,unsigned * disable_pipes)7947 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7948 unsigned *prepare_pipes, unsigned *disable_pipes)
7949 {
7950 struct intel_crtc *intel_crtc;
7951 struct drm_device *dev = crtc->dev;
7952 struct intel_encoder *encoder;
7953 struct intel_connector *connector;
7954 struct drm_crtc *tmp_crtc;
7955
7956 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7957
7958 /* Check which crtcs have changed outputs connected to them, these need
7959 * to be part of the prepare_pipes mask. We don't (yet) support global
7960 * modeset across multiple crtcs, so modeset_pipes will only have one
7961 * bit set at most. */
7962 list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
7963 base.head) {
7964 if (connector->base.encoder == &connector->new_encoder->base)
7965 continue;
7966
7967 if (connector->base.encoder) {
7968 tmp_crtc = connector->base.encoder->crtc;
7969
7970 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7971 }
7972
7973 if (connector->new_encoder)
7974 *prepare_pipes |=
7975 1 << connector->new_encoder->new_crtc->pipe;
7976 }
7977
7978 list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
7979 base.head) {
7980 if (encoder->base.crtc == &encoder->new_crtc->base)
7981 continue;
7982
7983 if (encoder->base.crtc) {
7984 tmp_crtc = encoder->base.crtc;
7985
7986 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7987 }
7988
7989 if (encoder->new_crtc)
7990 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7991 }
7992
7993 /* Check for any pipes that will be fully disabled ... */
7994 list_for_each_entry(intel_crtc, struct intel_crtc, &dev->mode_config.crtc_list,
7995 base.head) {
7996 bool used = false;
7997
7998 /* Don't try to disable disabled crtcs. */
7999 if (!intel_crtc->base.enabled)
8000 continue;
8001
8002 list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
8003 base.head) {
8004 if (encoder->new_crtc == intel_crtc)
8005 used = true;
8006 }
8007
8008 if (!used)
8009 *disable_pipes |= 1 << intel_crtc->pipe;
8010 }
8011
8012
8013 /* set_mode is also used to update properties on life display pipes. */
8014 intel_crtc = to_intel_crtc(crtc);
8015 if (crtc->enabled)
8016 *prepare_pipes |= 1 << intel_crtc->pipe;
8017
8018 /*
8019 * For simplicity do a full modeset on any pipe where the output routing
8020 * changed. We could be more clever, but that would require us to be
8021 * more careful with calling the relevant encoder->mode_set functions.
8022 */
8023 if (*prepare_pipes)
8024 *modeset_pipes = *prepare_pipes;
8025
8026 /* ... and mask these out. */
8027 *modeset_pipes &= ~(*disable_pipes);
8028 *prepare_pipes &= ~(*disable_pipes);
8029
8030 /*
8031 * HACK: We don't (yet) fully support global modesets. intel_set_config
8032 * obies this rule, but the modeset restore mode of
8033 * intel_modeset_setup_hw_state does not.
8034 */
8035 *modeset_pipes &= 1 << intel_crtc->pipe;
8036 *prepare_pipes &= 1 << intel_crtc->pipe;
8037
8038 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8039 *modeset_pipes, *prepare_pipes, *disable_pipes);
8040 }
8041
intel_crtc_in_use(struct drm_crtc * crtc)8042 static bool intel_crtc_in_use(struct drm_crtc *crtc)
8043 {
8044 struct drm_encoder *encoder;
8045 struct drm_device *dev = crtc->dev;
8046
8047 list_for_each_entry(encoder, struct drm_encoder, &dev->mode_config.encoder_list, head)
8048 if (encoder->crtc == crtc)
8049 return true;
8050
8051 return false;
8052 }
8053
8054 static void
intel_modeset_update_state(struct drm_device * dev,unsigned prepare_pipes)8055 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8056 {
8057 struct intel_encoder *intel_encoder;
8058 struct intel_crtc *intel_crtc;
8059 struct drm_connector *connector;
8060
8061 list_for_each_entry(intel_encoder, struct intel_encoder, &dev->mode_config.encoder_list,
8062 base.head) {
8063 if (!intel_encoder->base.crtc)
8064 continue;
8065
8066 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8067
8068 if (prepare_pipes & (1 << intel_crtc->pipe))
8069 intel_encoder->connectors_active = false;
8070 }
8071
8072 intel_modeset_commit_output_state(dev);
8073
8074 /* Update computed state. */
8075 list_for_each_entry(intel_crtc, struct intel_crtc, &dev->mode_config.crtc_list,
8076 base.head) {
8077 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8078 }
8079
8080 list_for_each_entry(connector, struct drm_connector, &dev->mode_config.connector_list, head) {
8081 if (!connector->encoder || !connector->encoder->crtc)
8082 continue;
8083
8084 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8085
8086 if (prepare_pipes & (1 << intel_crtc->pipe)) {
8087 struct drm_property *dpms_property =
8088 dev->mode_config.dpms_property;
8089
8090 connector->dpms = DRM_MODE_DPMS_ON;
8091 drm_object_property_set_value(&connector->base,
8092 dpms_property,
8093 DRM_MODE_DPMS_ON);
8094
8095 intel_encoder = to_intel_encoder(connector->encoder);
8096 intel_encoder->connectors_active = true;
8097 }
8098 }
8099
8100 }
8101
8102 #define for_each_intel_crtc_masked(dev, mask, _intel_crtc) \
8103 list_for_each_entry((_intel_crtc), struct intel_crtc, \
8104 &(dev)->mode_config.crtc_list, \
8105 base.head) \
8106 if (mask & (1 <<(_intel_crtc)->pipe)) \
8107
8108 static bool
intel_pipe_config_compare(struct drm_device * dev,struct intel_crtc_config * current_config,struct intel_crtc_config * pipe_config)8109 intel_pipe_config_compare(struct drm_device *dev,
8110 struct intel_crtc_config *current_config,
8111 struct intel_crtc_config *pipe_config)
8112 {
8113 #define PIPE_CONF_CHECK_X(name) \
8114 if (current_config->name != pipe_config->name) { \
8115 DRM_DEBUG_KMS("mismatch in " #name " " \
8116 "(expected 0x%08x, found 0x%08x)\n", \
8117 current_config->name, \
8118 pipe_config->name); \
8119 return false; \
8120 }
8121
8122 #define PIPE_CONF_CHECK_I(name) \
8123 if (current_config->name != pipe_config->name) { \
8124 DRM_DEBUG_KMS("mismatch in " #name " " \
8125 "(expected %i, found %i)\n", \
8126 current_config->name, \
8127 pipe_config->name); \
8128 return false; \
8129 }
8130
8131 #define PIPE_CONF_CHECK_FLAGS(name, mask) \
8132 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8133 DRM_DEBUG_KMS("mismatch in " #name " " \
8134 "(expected %i, found %i)\n", \
8135 current_config->name & (mask), \
8136 pipe_config->name & (mask)); \
8137 return false; \
8138 }
8139
8140 #define PIPE_CONF_QUIRK(quirk) \
8141 ((current_config->quirks | pipe_config->quirks) & (quirk))
8142
8143 PIPE_CONF_CHECK_I(cpu_transcoder);
8144
8145 PIPE_CONF_CHECK_I(has_pch_encoder);
8146 PIPE_CONF_CHECK_I(fdi_lanes);
8147 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8148 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8149 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8150 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8151 PIPE_CONF_CHECK_I(fdi_m_n.tu);
8152
8153 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8154 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8155 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8156 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8157 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8158 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8159
8160 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8161 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8162 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8163 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8164 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8165 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8166
8167 if (!HAS_PCH_SPLIT(dev))
8168 PIPE_CONF_CHECK_I(pixel_multiplier);
8169
8170 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8171 DRM_MODE_FLAG_INTERLACE);
8172
8173 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8174 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8175 DRM_MODE_FLAG_PHSYNC);
8176 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8177 DRM_MODE_FLAG_NHSYNC);
8178 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8179 DRM_MODE_FLAG_PVSYNC);
8180 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8181 DRM_MODE_FLAG_NVSYNC);
8182 }
8183
8184 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8185 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8186
8187 PIPE_CONF_CHECK_I(gmch_pfit.control);
8188 /* pfit ratios are autocomputed by the hw on gen4+ */
8189 if (INTEL_INFO(dev)->gen < 4)
8190 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8191 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8192 PIPE_CONF_CHECK_I(pch_pfit.pos);
8193 PIPE_CONF_CHECK_I(pch_pfit.size);
8194
8195 PIPE_CONF_CHECK_I(ips_enabled);
8196
8197 PIPE_CONF_CHECK_I(shared_dpll);
8198 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8199 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8200 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
8201
8202 #undef PIPE_CONF_CHECK_X
8203 #undef PIPE_CONF_CHECK_I
8204 #undef PIPE_CONF_CHECK_FLAGS
8205 #undef PIPE_CONF_QUIRK
8206
8207 return true;
8208 }
8209
8210 static void
check_connector_state(struct drm_device * dev)8211 check_connector_state(struct drm_device *dev)
8212 {
8213 struct intel_connector *connector;
8214
8215 list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
8216 base.head) {
8217 /* This also checks the encoder/connector hw state with the
8218 * ->get_hw_state callbacks. */
8219 intel_connector_check_state(connector);
8220
8221 if (&connector->new_encoder->base != connector->base.encoder)
8222 DRM_ERROR("connector's staged encoder doesn't match current encoder\n");
8223 }
8224 }
8225
8226 static void
check_encoder_state(struct drm_device * dev)8227 check_encoder_state(struct drm_device *dev)
8228 {
8229 struct intel_encoder *encoder;
8230 struct intel_connector *connector;
8231
8232 list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
8233 base.head) {
8234 bool enabled = false;
8235 bool active = false;
8236 enum pipe pipe, tracked_pipe;
8237
8238 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8239 encoder->base.base.id,
8240 drm_get_encoder_name(&encoder->base));
8241
8242 if (&encoder->new_crtc->base != encoder->base.crtc)
8243 DRM_ERROR("encoder's stage crtc doesn't match current crtc\n");
8244 if (encoder->connectors_active && !encoder->base.crtc)
8245 DRM_ERROR("encoder's active_connectors set, but no crtc\n");
8246
8247 list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
8248 base.head) {
8249 if (connector->base.encoder != &encoder->base)
8250 continue;
8251 enabled = true;
8252 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8253 active = true;
8254 }
8255 if (!!encoder->base.crtc != enabled)
8256 DRM_ERROR("encoder's enabled state mismatch "
8257 "(expected %i, found %i)\n",
8258 !!encoder->base.crtc, enabled);
8259 if (active && !encoder->base.crtc)
8260 DRM_ERROR("active encoder with no crtc\n");
8261
8262 if (encoder->connectors_active != active)
8263 DRM_ERROR("encoder's computed active state doesn't match tracked active state "
8264 "(expected %i, found %i)\n", active, encoder->connectors_active);
8265
8266 active = encoder->get_hw_state(encoder, &pipe);
8267 if (active != encoder->connectors_active)
8268 DRM_ERROR("encoder's hw state doesn't match sw tracking "
8269 "(expected %i, found %i)\n",
8270 encoder->connectors_active, active);
8271
8272 if (!encoder->base.crtc)
8273 continue;
8274
8275 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8276 if (active && pipe != tracked_pipe)
8277 DRM_ERROR("active encoder's pipe doesn't match"
8278 "(expected %i, found %i)\n",
8279 tracked_pipe, pipe);
8280
8281 }
8282 }
8283
8284 static void
check_crtc_state(struct drm_device * dev)8285 check_crtc_state(struct drm_device *dev)
8286 {
8287 drm_i915_private_t *dev_priv = dev->dev_private;
8288 struct intel_crtc *crtc;
8289 struct intel_encoder *encoder;
8290 struct intel_crtc_config pipe_config;
8291
8292 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list,
8293 base.head) {
8294 bool enabled = false;
8295 bool active = false;
8296
8297 (void) memset(&pipe_config, 0, sizeof(pipe_config));
8298
8299 DRM_DEBUG_KMS("[CRTC:%d]\n",
8300 crtc->base.base.id);
8301
8302 if (crtc->active && !crtc->base.enabled)
8303 DRM_ERROR("active crtc, but not enabled in sw tracking\n");
8304
8305 list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
8306 base.head) {
8307 if (encoder->base.crtc != &crtc->base)
8308 continue;
8309 enabled = true;
8310 if (encoder->connectors_active)
8311 active = true;
8312 }
8313
8314 if (active != crtc->active)
8315 DRM_ERROR("crtc's computed active state doesn't match tracked active state "
8316 "(expected %i, found %i)\n", active, crtc->active);
8317 if (enabled != crtc->base.enabled)
8318 DRM_ERROR("crtc's computed enabled state doesn't match tracked enabled state "
8319 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8320
8321 active = dev_priv->display.get_pipe_config(crtc,
8322 &pipe_config);
8323
8324 /* hw state is inconsistent with the pipe A quirk */
8325 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8326 active = crtc->active;
8327
8328 list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
8329 base.head) {
8330 enum pipe pipe;
8331 if (encoder->base.crtc != &crtc->base)
8332 continue;
8333 if (encoder->get_config &&
8334 encoder->get_hw_state(encoder, &pipe))
8335 encoder->get_config(encoder, &pipe_config);
8336 }
8337
8338 if(crtc->active != active)
8339 DRM_ERROR("crtc active state doesn't match with hw state "
8340 "(expected %i, found %i)\n", crtc->active, active);
8341
8342 if (active &&
8343 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8344 DRM_DEBUG_KMS("pipe state doesn't match!\n");
8345 intel_dump_pipe_config(crtc, &pipe_config,
8346 "[hw state]");
8347 intel_dump_pipe_config(crtc, &crtc->config,
8348 "[sw state]");
8349 }
8350 }
8351 }
8352
8353 static void
check_shared_dpll_state(struct drm_device * dev)8354 check_shared_dpll_state(struct drm_device *dev)
8355 {
8356 drm_i915_private_t *dev_priv = dev->dev_private;
8357 struct intel_crtc *crtc;
8358 struct intel_dpll_hw_state dpll_hw_state;
8359 int i;
8360
8361 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8362 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8363 int enabled_crtcs = 0, active_crtcs = 0;
8364 bool active;
8365
8366 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8367
8368 DRM_DEBUG_KMS("%s\n", pll->name);
8369
8370 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8371
8372 if(pll->active > pll->refcount)
8373 DRM_DEBUG_KMS("more active pll users than references: %i vs %i\n",
8374 pll->active, pll->refcount);
8375 if(pll->active && !pll->on)
8376 DRM_DEBUG_KMS("pll in active use but not on in sw tracking\n");
8377 if(pll->on && !pll->active)
8378 DRM_DEBUG_KMS("pll in on but not on in use in sw tracking\n");
8379 if(pll->on != active)
8380 DRM_DEBUG_KMS("pll on state mismatch (expected %i, found %i)\n",
8381 pll->on, active);
8382
8383 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list,
8384 base.head) {
8385 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8386 enabled_crtcs++;
8387 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8388 active_crtcs++;
8389 }
8390 if(pll->active != active_crtcs)
8391 DRM_DEBUG_KMS("pll active crtcs mismatch (expected %i, found %i)\n",
8392 pll->active, active_crtcs);
8393 if(pll->refcount != enabled_crtcs)
8394 DRM_DEBUG_KMS("pll enabled crtcs mismatch (expected %i, found %i)\n",
8395 pll->refcount, enabled_crtcs);
8396
8397 if(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8398 sizeof(dpll_hw_state)))
8399 DRM_ERROR("pll hw state mismatch\n");
8400 }
8401 }
8402
8403 void
intel_modeset_check_state(struct drm_device * dev)8404 intel_modeset_check_state(struct drm_device *dev)
8405 {
8406 check_connector_state(dev);
8407 check_encoder_state(dev);
8408 check_crtc_state(dev);
8409 check_shared_dpll_state(dev);
8410 }
8411
__intel_set_mode(struct drm_crtc * crtc,struct drm_display_mode * mode,int x,int y,struct drm_framebuffer * fb)8412 static int __intel_set_mode(struct drm_crtc *crtc,
8413 struct drm_display_mode *mode,
8414 int x, int y, struct drm_framebuffer *fb)
8415 {
8416 struct drm_device *dev = crtc->dev;
8417 drm_i915_private_t *dev_priv = dev->dev_private;
8418 struct drm_display_mode *saved_mode, *saved_hwmode;
8419 struct intel_crtc_config *pipe_config = NULL;
8420 struct intel_crtc *intel_crtc;
8421 unsigned disable_pipes, prepare_pipes, modeset_pipes;
8422 int ret = 0;
8423
8424 saved_mode = kzalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
8425 if (!saved_mode)
8426 return -ENOMEM;
8427 saved_hwmode = saved_mode + 1;
8428
8429 intel_modeset_affected_pipes(crtc, &modeset_pipes,
8430 &prepare_pipes, &disable_pipes);
8431
8432 *saved_hwmode = crtc->hwmode;
8433 *saved_mode = crtc->mode;
8434
8435 /* Hack: Because we don't (yet) support global modeset on multiple
8436 * crtcs, we don't keep track of the new mode for more than one crtc.
8437 * Hence simply check whether any bit is set in modeset_pipes in all the
8438 * pieces of code that are not yet converted to deal with mutliple crtcs
8439 * changing their mode at the same time. */
8440 if (modeset_pipes) {
8441 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
8442 if (!(pipe_config)) {
8443 ret = -EINVAL;
8444 pipe_config = NULL;
8445
8446 goto out;
8447 }
8448 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8449 "[modeset]");
8450 }
8451
8452 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8453 intel_crtc_disable(&intel_crtc->base);
8454
8455 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8456 if (intel_crtc->base.enabled)
8457 dev_priv->display.crtc_disable(&intel_crtc->base);
8458 }
8459
8460 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8461 * to set it here already despite that we pass it down the callchain.
8462 */
8463 if (modeset_pipes) {
8464 crtc->mode = *mode;
8465 /* mode_set/enable/disable functions rely on a correct pipe
8466 * config. */
8467 to_intel_crtc(crtc)->config = *pipe_config;
8468 }
8469
8470 /* Only after disabling all output pipelines that will be changed can we
8471 * update the the output configuration. */
8472 intel_modeset_update_state(dev, prepare_pipes);
8473
8474 if (dev_priv->display.modeset_global_resources)
8475 dev_priv->display.modeset_global_resources(dev);
8476
8477 /* Set up the DPLL and any encoders state that needs to adjust or depend
8478 * on the DPLL.
8479 */
8480 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
8481 ret = intel_crtc_mode_set(&intel_crtc->base,
8482 x, y, fb);
8483 if (ret)
8484 goto done;
8485 }
8486
8487 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
8488 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8489 dev_priv->display.crtc_enable(&intel_crtc->base);
8490
8491 if (modeset_pipes) {
8492 /* Store real post-adjustment hardware mode. */
8493 crtc->hwmode = pipe_config->adjusted_mode;
8494
8495 /* Calculate and store various constants which
8496 * are later needed by vblank and swap-completion
8497 * timestamping. They are derived from true hwmode.
8498 */
8499 drm_calc_timestamping_constants(crtc);
8500 }
8501
8502 /* FIXME: add subpixel order */
8503 done:
8504 if (ret && crtc->enabled) {
8505 crtc->hwmode = *saved_hwmode;
8506 crtc->mode = *saved_mode;
8507 }
8508
8509 out:
8510 if (pipe_config)
8511 kfree(pipe_config, sizeof(*pipe_config));
8512 kfree(saved_mode, 2 * sizeof(*saved_mode));
8513 return ret;
8514 }
8515
intel_set_mode(struct drm_crtc * crtc,struct drm_display_mode * mode,int x,int y,struct drm_framebuffer * fb)8516 int intel_set_mode(struct drm_crtc *crtc,
8517 struct drm_display_mode *mode,
8518 int x, int y, struct drm_framebuffer *fb)
8519 {
8520 int ret;
8521
8522 ret = __intel_set_mode(crtc, mode, x, y, fb);
8523
8524 if (ret == 0)
8525 intel_modeset_check_state(crtc->dev);
8526
8527 return ret;
8528 }
8529
intel_crtc_restore_mode(struct drm_crtc * crtc)8530 void intel_crtc_restore_mode(struct drm_crtc *crtc)
8531 {
8532 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8533 }
8534
8535 #undef for_each_intel_crtc_masked
8536
intel_set_config_free(struct drm_device * dev,struct intel_set_config * config)8537 static void intel_set_config_free(struct drm_device *dev, struct intel_set_config *config)
8538 {
8539 if (!config)
8540 return;
8541
8542 kfree(config->save_connector_encoders, dev->mode_config.num_connector * sizeof(struct drm_encoder *));
8543 kfree(config->save_encoder_crtcs, dev->mode_config.num_encoder * sizeof(struct drm_crtc *));
8544 kfree(config, sizeof(*config));
8545 }
8546
intel_set_config_save_state(struct drm_device * dev,struct intel_set_config * config)8547 static int intel_set_config_save_state(struct drm_device *dev,
8548 struct intel_set_config *config)
8549 {
8550 struct drm_encoder *encoder;
8551 struct drm_connector *connector;
8552 int count;
8553
8554 config->save_encoder_crtcs =
8555 kcalloc(dev->mode_config.num_encoder,
8556 sizeof(struct drm_crtc *), GFP_KERNEL);
8557 if (!config->save_encoder_crtcs)
8558 return -ENOMEM;
8559
8560 config->save_connector_encoders =
8561 kcalloc(dev->mode_config.num_connector,
8562 sizeof(struct drm_encoder *), GFP_KERNEL);
8563 if (!config->save_connector_encoders)
8564 return -ENOMEM;
8565
8566 /* Copy data. Note that driver private data is not affected.
8567 * Should anything bad happen only the expected state is
8568 * restored, not the drivers personal bookkeeping.
8569 */
8570 count = 0;
8571 list_for_each_entry(encoder, struct drm_encoder, &dev->mode_config.encoder_list, head) {
8572 config->save_encoder_crtcs[count++] = encoder->crtc;
8573 }
8574
8575 count = 0;
8576 list_for_each_entry(connector, struct drm_connector, &dev->mode_config.connector_list, head) {
8577 config->save_connector_encoders[count++] = connector->encoder;
8578 }
8579
8580 return 0;
8581 }
8582
intel_set_config_restore_state(struct drm_device * dev,struct intel_set_config * config)8583 static void intel_set_config_restore_state(struct drm_device *dev,
8584 struct intel_set_config *config)
8585 {
8586 struct intel_encoder *encoder;
8587 struct intel_connector *connector;
8588 int count;
8589
8590 count = 0;
8591 list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list, base.head) {
8592 encoder->new_crtc =
8593 to_intel_crtc(config->save_encoder_crtcs[count++]);
8594 }
8595
8596 count = 0;
8597 list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list, base.head) {
8598 connector->new_encoder =
8599 to_intel_encoder(config->save_connector_encoders[count++]);
8600 }
8601 }
8602
8603 static bool
is_crtc_connector_off(struct drm_mode_set * set)8604 is_crtc_connector_off(struct drm_mode_set *set)
8605 {
8606 int i;
8607
8608 if (set->num_connectors == 0)
8609 return false;
8610
8611 if ((set->connectors == NULL))
8612 return false;
8613
8614 for (i = 0; i < set->num_connectors; i++)
8615 if (set->connectors[i]->encoder &&
8616 set->connectors[i]->encoder->crtc == set->crtc &&
8617 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
8618 return true;
8619
8620 return false;
8621 }
8622
8623 static void
intel_set_config_compute_mode_changes(struct drm_mode_set * set,struct intel_set_config * config)8624 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8625 struct intel_set_config *config)
8626 {
8627
8628 /* We should be able to check here if the fb has the same properties
8629 * and then just flip_or_move it */
8630 if (is_crtc_connector_off(set)) {
8631 config->mode_changed = true;
8632 } else if (set->crtc->fb != set->fb) {
8633 /* If we have no fb then treat it as a full mode set */
8634 if (set->crtc->fb == NULL) {
8635 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8636 config->mode_changed = true;
8637 } else if (set->fb == NULL) {
8638 config->mode_changed = true;
8639 } else if (set->fb->pixel_format !=
8640 set->crtc->fb->pixel_format) {
8641 config->mode_changed = true;
8642 } else {
8643 config->fb_changed = true;
8644 }
8645 }
8646
8647 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
8648 config->fb_changed = true;
8649
8650 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8651 DRM_DEBUG_KMS("modes are different, full mode set\n");
8652 drm_mode_debug_printmodeline(&set->crtc->mode);
8653 drm_mode_debug_printmodeline(set->mode);
8654 config->mode_changed = true;
8655 }
8656 }
8657
8658 static int
intel_modeset_stage_output_state(struct drm_device * dev,struct drm_mode_set * set,struct intel_set_config * config)8659 intel_modeset_stage_output_state(struct drm_device *dev,
8660 struct drm_mode_set *set,
8661 struct intel_set_config *config)
8662 {
8663 struct drm_crtc *new_crtc;
8664 struct intel_connector *connector;
8665 struct intel_encoder *encoder;
8666 /* LINTED */
8667 int count, ro;
8668
8669 /* The upper layers ensure that we either disabl a crtc or have a list
8670 * of connectors. For paranoia, double-check this. */
8671 WARN_ON(!set->fb && (set->num_connectors != 0));
8672 WARN_ON(set->fb && (set->num_connectors == 0));
8673
8674 count = 0;
8675 list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
8676 base.head) {
8677 /* Otherwise traverse passed in connector list and get encoders
8678 * for them. */
8679 for (ro = 0; ro < set->num_connectors; ro++) {
8680 if (set->connectors[ro] == &connector->base) {
8681 connector->new_encoder = connector->encoder;
8682 break;
8683 }
8684 }
8685
8686 /* If we disable the crtc, disable all its connectors. Also, if
8687 * the connector is on the changing crtc but not on the new
8688 * connector list, disable it. */
8689 if ((!set->fb || ro == set->num_connectors) &&
8690 connector->base.encoder &&
8691 connector->base.encoder->crtc == set->crtc) {
8692 connector->new_encoder = NULL;
8693
8694 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8695 connector->base.base.id,
8696 drm_get_connector_name(&connector->base));
8697 }
8698
8699
8700 if (&connector->new_encoder->base != connector->base.encoder) {
8701 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
8702 config->mode_changed = true;
8703 }
8704 }
8705 /* connector->new_encoder is now updated for all connectors. */
8706
8707 /* Update crtc of enabled connectors. */
8708 count = 0;
8709 list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
8710 base.head) {
8711 if (!connector->new_encoder)
8712 continue;
8713
8714 new_crtc = connector->new_encoder->base.crtc;
8715
8716 for (ro = 0; ro < set->num_connectors; ro++) {
8717 if (set->connectors[ro] == &connector->base)
8718 new_crtc = set->crtc;
8719 }
8720
8721 /* Make sure the new CRTC will work with the encoder */
8722 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8723 new_crtc)) {
8724 return -EINVAL;
8725 }
8726 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8727
8728 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8729 connector->base.base.id,
8730 drm_get_connector_name(&connector->base),
8731 new_crtc->base.id);
8732 }
8733
8734 /* Check for any encoders that needs to be disabled. */
8735 list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
8736 base.head) {
8737 list_for_each_entry(connector, struct intel_connector,
8738 &dev->mode_config.connector_list,
8739 base.head) {
8740 if (connector->new_encoder == encoder) {
8741 WARN_ON(!connector->new_encoder->new_crtc);
8742
8743 goto next_encoder;
8744 }
8745 }
8746 encoder->new_crtc = NULL;
8747 next_encoder:
8748 /* Only now check for crtc changes so we don't miss encoders
8749 * that will be disabled. */
8750 if (&encoder->new_crtc->base != encoder->base.crtc) {
8751 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
8752 config->mode_changed = true;
8753 }
8754 }
8755 /* Now we've also updated encoder->new_crtc for all encoders. */
8756
8757 return 0;
8758 }
8759
intel_crtc_set_config(struct drm_mode_set * set)8760 static int intel_crtc_set_config(struct drm_mode_set *set)
8761 {
8762 struct drm_device *dev;
8763 struct drm_mode_set save_set;
8764 struct intel_set_config *config;
8765 int ret;
8766
8767 BUG_ON(!set);
8768 BUG_ON(!set->crtc);
8769 BUG_ON(!set->crtc->helper_private);
8770
8771 /* Enforce sane interface api - has been abused by the fb helper. */
8772 BUG_ON(!set->mode && set->fb);
8773 BUG_ON(set->fb && set->num_connectors == 0);
8774
8775 if (set->fb) {
8776 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8777 set->crtc->base.id, set->fb->base.id,
8778 (int)set->num_connectors, set->x, set->y);
8779 } else {
8780 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
8781 }
8782
8783 dev = set->crtc->dev;
8784
8785 ret = -ENOMEM;
8786 config = kzalloc(sizeof(*config), GFP_KERNEL);
8787 if (!config)
8788 goto out_config;
8789
8790 ret = intel_set_config_save_state(dev, config);
8791 if (ret)
8792 goto out_config;
8793
8794 save_set.crtc = set->crtc;
8795 save_set.mode = &set->crtc->mode;
8796 save_set.x = set->crtc->x;
8797 save_set.y = set->crtc->y;
8798 save_set.fb = set->crtc->fb;
8799
8800 /* Compute whether we need a full modeset, only an fb base update or no
8801 * change at all. In the future we might also check whether only the
8802 * mode changed, e.g. for LVDS where we only change the panel fitter in
8803 * such cases. */
8804 intel_set_config_compute_mode_changes(set, config);
8805
8806 ret = intel_modeset_stage_output_state(dev, set, config);
8807 if (ret)
8808 goto fail;
8809
8810 if (config->mode_changed) {
8811 if ((set->mode == NULL) && set->fb) {
8812 DRM_DEBUG_KMS("fb changed without set->mode");
8813 ret = -EINVAL;
8814 goto fail;
8815 }
8816
8817 ret = intel_set_mode(set->crtc, set->mode,
8818 set->x, set->y, set->fb);
8819 } else if (config->fb_changed) {
8820 intel_crtc_wait_for_pending_flips(set->crtc);
8821
8822 ret = intel_pipe_set_base(set->crtc,
8823 set->x, set->y, set->fb);
8824 }
8825
8826 if (ret) {
8827 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8828 set->crtc->base.id, ret);
8829 fail:
8830 intel_set_config_restore_state(dev, config);
8831
8832 /* Try to restore the config */
8833 if (config->mode_changed &&
8834 intel_set_mode(save_set.crtc, save_set.mode,
8835 save_set.x, save_set.y, save_set.fb))
8836 DRM_ERROR("failed to restore config after modeset failure\n");
8837 }
8838
8839 out_config:
8840 intel_set_config_free(dev, config);
8841 return ret;
8842 }
8843
8844 static const struct drm_crtc_funcs intel_crtc_funcs = {
8845 .cursor_set = intel_crtc_cursor_set,
8846 .cursor_move = intel_crtc_cursor_move,
8847 .gamma_set = intel_crtc_gamma_set,
8848 .set_config = intel_crtc_set_config,
8849 .destroy = intel_crtc_destroy,
8850 .page_flip = intel_crtc_page_flip,
8851 };
8852
intel_cpu_pll_init(struct drm_device * dev)8853 static void intel_cpu_pll_init(struct drm_device *dev)
8854 {
8855 if (HAS_DDI(dev))
8856 intel_ddi_pll_init(dev);
8857 }
8858
ibx_pch_dpll_get_hw_state(struct drm_i915_private * dev_priv,struct intel_shared_dpll * pll,struct intel_dpll_hw_state * hw_state)8859 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8860 struct intel_shared_dpll *pll,
8861 struct intel_dpll_hw_state *hw_state)
8862 {
8863 uint32_t val;
8864
8865 val = I915_READ(PCH_DPLL(pll->id));
8866 hw_state->dpll = val;
8867 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8868 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
8869
8870 return val & DPLL_VCO_ENABLE;
8871 }
8872
ibx_pch_dpll_enable(struct drm_i915_private * dev_priv,struct intel_shared_dpll * pll)8873 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8874 struct intel_shared_dpll *pll)
8875 {
8876 uint32_t reg, val;
8877
8878 /* PCH refclock must be enabled first */
8879 assert_pch_refclk_enabled(dev_priv);
8880
8881 reg = PCH_DPLL(pll->id);
8882 val = I915_READ(reg);
8883 val |= DPLL_VCO_ENABLE;
8884 I915_WRITE(reg, val);
8885 POSTING_READ(reg);
8886 udelay(200);
8887 }
8888
ibx_pch_dpll_disable(struct drm_i915_private * dev_priv,struct intel_shared_dpll * pll)8889 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8890 struct intel_shared_dpll *pll)
8891 {
8892 struct drm_device *dev = dev_priv->dev;
8893 struct intel_crtc *crtc;
8894 uint32_t reg, val;
8895
8896 /* Make sure no transcoder isn't still depending on us. */
8897 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list, base.head) {
8898 if (intel_crtc_to_shared_dpll(crtc) == pll)
8899 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
8900 }
8901
8902 reg = PCH_DPLL(pll->id);
8903 val = I915_READ(reg);
8904 val &= ~DPLL_VCO_ENABLE;
8905 I915_WRITE(reg, val);
8906 POSTING_READ(reg);
8907 udelay(200);
8908 }
8909
8910 static char *ibx_pch_dpll_names[] = {
8911 "PCH DPLL A",
8912 "PCH DPLL B",
8913 };
8914
ibx_pch_dpll_init(struct drm_device * dev)8915 static void ibx_pch_dpll_init(struct drm_device *dev)
8916 {
8917 struct drm_i915_private *dev_priv = dev->dev_private;
8918 int i;
8919
8920 dev_priv->num_shared_dpll = 2;
8921
8922 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8923 dev_priv->shared_dplls[i].id = i;
8924 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
8925 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8926 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
8927 dev_priv->shared_dplls[i].get_hw_state =
8928 ibx_pch_dpll_get_hw_state;
8929 }
8930 }
8931
intel_shared_dpll_init(struct drm_device * dev)8932 static void intel_shared_dpll_init(struct drm_device *dev)
8933 {
8934 struct drm_i915_private *dev_priv = dev->dev_private;
8935
8936 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8937 ibx_pch_dpll_init(dev);
8938 else
8939 dev_priv->num_shared_dpll = 0;
8940
8941 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8942 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8943 dev_priv->num_shared_dpll);
8944 }
8945
intel_crtc_init(struct drm_device * dev,int pipe)8946 static void intel_crtc_init(struct drm_device *dev, int pipe)
8947 {
8948 drm_i915_private_t *dev_priv = dev->dev_private;
8949 struct intel_crtc *intel_crtc;
8950 int i;
8951
8952 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8953 if (intel_crtc == NULL)
8954 return;
8955
8956 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8957
8958 (void) drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8959 for (i = 0; i < 256; i++) {
8960 intel_crtc->lut_r[i] = (u8) i;
8961 intel_crtc->lut_g[i] = (u8) i;
8962 intel_crtc->lut_b[i] = (u8) i;
8963 }
8964
8965 /* Swap pipes & planes for FBC on pre-965 */
8966 intel_crtc->pipe = pipe;
8967 intel_crtc->plane = pipe;
8968 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8969 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8970 intel_crtc->plane = !pipe;
8971 }
8972
8973 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8974 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8975 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8976 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8977
8978 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8979 }
8980
8981 /* LINTED */
intel_get_pipe_from_crtc_id(DRM_IOCTL_ARGS)8982 int intel_get_pipe_from_crtc_id(DRM_IOCTL_ARGS)
8983 {
8984 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8985 struct drm_mode_object *drmmode_obj;
8986 struct intel_crtc *crtc;
8987
8988 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8989 return -ENODEV;
8990
8991 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8992 DRM_MODE_OBJECT_CRTC);
8993
8994 if (!drmmode_obj) {
8995 DRM_ERROR("no such CRTC id\n");
8996 return -EINVAL;
8997 }
8998
8999 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9000 pipe_from_crtc_id->pipe = crtc->pipe;
9001
9002 return 0;
9003 }
9004
intel_encoder_clones(struct intel_encoder * encoder)9005 static int intel_encoder_clones(struct intel_encoder *encoder)
9006 {
9007 struct drm_device *dev = encoder->base.dev;
9008 struct intel_encoder *source_encoder;
9009 int index_mask = 0;
9010 int entry = 0;
9011
9012 list_for_each_entry(source_encoder, struct intel_encoder,
9013 &dev->mode_config.encoder_list, base.head) {
9014
9015 if (encoder == source_encoder)
9016 index_mask |= (1 << entry);
9017
9018 /* Intel hw has only one MUX where enocoders could be cloned. */
9019 if (encoder->cloneable && source_encoder->cloneable)
9020 index_mask |= (1 << entry);
9021
9022 entry++;
9023 }
9024
9025 return index_mask;
9026 }
9027
has_edp_a(struct drm_device * dev)9028 static bool has_edp_a(struct drm_device *dev)
9029 {
9030 struct drm_i915_private *dev_priv = dev->dev_private;
9031
9032 if (!IS_MOBILE(dev))
9033 return false;
9034
9035 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9036 return false;
9037
9038 if (IS_GEN5(dev) &&
9039 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9040 return false;
9041
9042 return true;
9043 }
9044
intel_setup_outputs(struct drm_device * dev)9045 static void intel_setup_outputs(struct drm_device *dev)
9046 {
9047 struct drm_i915_private *dev_priv = dev->dev_private;
9048 struct intel_encoder *encoder;
9049 bool dpd_is_edp = false;
9050
9051 intel_lvds_init(dev);
9052
9053 if (!IS_ULT(dev))
9054 intel_crt_init(dev);
9055
9056 if (HAS_DDI(dev)) {
9057 int found;
9058
9059 /* Haswell uses DDI functions to detect digital outputs */
9060 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9061 /* DDI A only supports eDP */
9062 if (found)
9063 intel_ddi_init(dev, PORT_A);
9064
9065 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9066 * register */
9067 found = I915_READ(SFUSE_STRAP);
9068
9069 if (found & SFUSE_STRAP_DDIB_DETECTED)
9070 intel_ddi_init(dev, PORT_B);
9071 if (found & SFUSE_STRAP_DDIC_DETECTED)
9072 intel_ddi_init(dev, PORT_C);
9073 if (found & SFUSE_STRAP_DDID_DETECTED)
9074 intel_ddi_init(dev, PORT_D);
9075 } else if (HAS_PCH_SPLIT(dev)) {
9076 int found;
9077 dpd_is_edp = intel_dpd_is_edp(dev);
9078
9079 if (has_edp_a(dev))
9080 intel_dp_init(dev, DP_A, PORT_A);
9081
9082 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
9083 /* PCH SDVOB multiplex with HDMIB */
9084 found = intel_sdvo_init(dev, PCH_SDVOB, true);
9085 if (!found)
9086 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
9087 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
9088 intel_dp_init(dev, PCH_DP_B, PORT_B);
9089 }
9090
9091 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
9092 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
9093
9094 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
9095 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
9096
9097 if (I915_READ(PCH_DP_C) & DP_DETECTED)
9098 intel_dp_init(dev, PCH_DP_C, PORT_C);
9099
9100 if (I915_READ(PCH_DP_D) & DP_DETECTED)
9101 intel_dp_init(dev, PCH_DP_D, PORT_D);
9102 } else if (IS_VALLEYVIEW(dev)) {
9103 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
9104 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9105 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
9106
9107 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9108 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9109 PORT_B);
9110 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9111 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9112 }
9113 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
9114 bool found = false;
9115
9116 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9117 DRM_DEBUG_KMS("probing SDVOB\n");
9118 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
9119 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9120 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
9121 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
9122 }
9123
9124 if (!found && SUPPORTS_INTEGRATED_DP(dev))
9125 intel_dp_init(dev, DP_B, PORT_B);
9126 }
9127
9128 /* Before G4X SDVOC doesn't have its own detect register */
9129
9130 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
9131 DRM_DEBUG_KMS("probing SDVOC\n");
9132 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
9133 }
9134
9135 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
9136
9137 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9138 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
9139 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
9140 }
9141 if (SUPPORTS_INTEGRATED_DP(dev))
9142 intel_dp_init(dev, DP_C, PORT_C);
9143 }
9144
9145 if (SUPPORTS_INTEGRATED_DP(dev) &&
9146 (I915_READ(DP_D) & DP_DETECTED))
9147 intel_dp_init(dev, DP_D, PORT_D);
9148 } else if (IS_GEN2(dev))
9149 intel_dvo_init(dev);
9150
9151 if (SUPPORTS_TV(dev))
9152 intel_tv_init(dev);
9153
9154 list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list, base.head) {
9155 encoder->base.possible_crtcs = encoder->crtc_mask;
9156 encoder->base.possible_clones =
9157 intel_encoder_clones(encoder);
9158 }
9159
9160 intel_init_pch_refclk(dev);
9161
9162 drm_helper_move_panel_connectors_to_head(dev);
9163 }
9164
intel_user_framebuffer_destroy(struct drm_framebuffer * fb)9165 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9166 {
9167 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9168
9169 drm_framebuffer_cleanup(fb);
9170 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
9171
9172 kfree(intel_fb, sizeof (struct intel_framebuffer));
9173 }
9174
intel_user_framebuffer_create_handle(struct drm_framebuffer * fb,struct drm_file * file,unsigned int * handle)9175 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
9176 struct drm_file *file,
9177 unsigned int *handle)
9178 {
9179 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9180 struct drm_i915_gem_object *obj = intel_fb->obj;
9181
9182 return drm_gem_handle_create(file, &obj->base, handle);
9183 }
9184
9185 static const struct drm_framebuffer_funcs intel_fb_funcs = {
9186 .destroy = intel_user_framebuffer_destroy,
9187 .create_handle = intel_user_framebuffer_create_handle,
9188 };
9189
intel_framebuffer_init(struct drm_device * dev,struct intel_framebuffer * intel_fb,struct drm_mode_fb_cmd2 * mode_cmd,struct drm_i915_gem_object * obj)9190 int intel_framebuffer_init(struct drm_device *dev,
9191 struct intel_framebuffer *intel_fb,
9192 struct drm_mode_fb_cmd2 *mode_cmd,
9193 struct drm_i915_gem_object *obj)
9194 {
9195 int pitch_limit;
9196 int ret;
9197
9198 if (obj->tiling_mode == I915_TILING_Y) {
9199 DRM_DEBUG("hardware does not support tiling Y\n");
9200 return -EINVAL;
9201 }
9202
9203 if (mode_cmd->pitches[0] & 63) {
9204 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9205 mode_cmd->pitches[0]);
9206 return -EINVAL;
9207 }
9208
9209 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9210 pitch_limit = 32*1024;
9211 } else if (INTEL_INFO(dev)->gen >= 4) {
9212 if (obj->tiling_mode)
9213 pitch_limit = 16*1024;
9214 else
9215 pitch_limit = 32*1024;
9216 } else if (INTEL_INFO(dev)->gen >= 3) {
9217 if (obj->tiling_mode)
9218 pitch_limit = 8*1024;
9219 else
9220 pitch_limit = 16*1024;
9221 } else
9222 /* XXX DSPC is limited to 4k tiled */
9223 pitch_limit = 8*1024;
9224
9225 if (mode_cmd->pitches[0] > pitch_limit) {
9226 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9227 obj->tiling_mode ? "tiled" : "linear",
9228 mode_cmd->pitches[0], pitch_limit);
9229 return -EINVAL;
9230 }
9231
9232 if (obj->tiling_mode != I915_TILING_NONE &&
9233 mode_cmd->pitches[0] != obj->stride) {
9234 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9235 mode_cmd->pitches[0], obj->stride);
9236 return -EINVAL;
9237 }
9238
9239 /* Reject formats not supported by any plane early. */
9240 switch (mode_cmd->pixel_format) {
9241 case DRM_FORMAT_C8:
9242 case DRM_FORMAT_RGB565:
9243 case DRM_FORMAT_XRGB8888:
9244 case DRM_FORMAT_ARGB8888:
9245 break;
9246 case DRM_FORMAT_XRGB1555:
9247 case DRM_FORMAT_ARGB1555:
9248 if (INTEL_INFO(dev)->gen > 3) {
9249 DRM_DEBUG("unsupported pixel format: %s\n",
9250 drm_get_format_name(mode_cmd->pixel_format));
9251 return -EINVAL;
9252 }
9253 break;
9254 case DRM_FORMAT_XBGR8888:
9255 case DRM_FORMAT_ABGR8888:
9256 case DRM_FORMAT_XRGB2101010:
9257 case DRM_FORMAT_ARGB2101010:
9258 case DRM_FORMAT_XBGR2101010:
9259 case DRM_FORMAT_ABGR2101010:
9260 if (INTEL_INFO(dev)->gen < 4) {
9261 DRM_DEBUG("unsupported pixel format: %s\n",
9262 drm_get_format_name(mode_cmd->pixel_format));
9263 return -EINVAL;
9264 }
9265 break;
9266 case DRM_FORMAT_YUYV:
9267 case DRM_FORMAT_UYVY:
9268 case DRM_FORMAT_YVYU:
9269 case DRM_FORMAT_VYUY:
9270 if (INTEL_INFO(dev)->gen < 5) {
9271 DRM_DEBUG("unsupported pixel format: %s\n",
9272 drm_get_format_name(mode_cmd->pixel_format));
9273 return -EINVAL;
9274 }
9275 break;
9276 default:
9277 DRM_DEBUG("unsupported pixel format: %s\n",
9278 drm_get_format_name(mode_cmd->pixel_format));
9279 return -EINVAL;
9280 }
9281
9282 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9283 if (mode_cmd->offsets[0] != 0)
9284 return -EINVAL;
9285
9286 (void) drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9287 intel_fb->obj = obj;
9288
9289 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9290 if (ret) {
9291 DRM_ERROR("framebuffer init failed %d\n", ret);
9292 return ret;
9293 }
9294
9295 return 0;
9296 }
9297
9298 static struct drm_framebuffer *
intel_user_framebuffer_create(struct drm_device * dev,struct drm_file * filp,struct drm_mode_fb_cmd2 * mode_cmd)9299 intel_user_framebuffer_create(struct drm_device *dev,
9300 struct drm_file *filp,
9301 struct drm_mode_fb_cmd2 *mode_cmd)
9302 {
9303 struct drm_i915_gem_object *obj;
9304
9305 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9306 mode_cmd->handles[0]));
9307 if (&obj->base == NULL)
9308 return (NULL);
9309
9310 return intel_framebuffer_create(dev, mode_cmd, obj);
9311 }
9312
9313 static const struct drm_mode_config_funcs intel_mode_funcs = {
9314 .fb_create = intel_user_framebuffer_create,
9315 .output_poll_changed = intel_fb_output_poll_changed,
9316 };
9317
9318 /* Set up chip specific display functions */
intel_init_display(struct drm_device * dev)9319 static void intel_init_display(struct drm_device *dev)
9320 {
9321 struct drm_i915_private *dev_priv = dev->dev_private;
9322
9323 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9324 dev_priv->display.find_dpll = g4x_find_best_dpll;
9325 else if (IS_VALLEYVIEW(dev))
9326 dev_priv->display.find_dpll = vlv_find_best_dpll;
9327 else if (IS_PINEVIEW(dev))
9328 dev_priv->display.find_dpll = pnv_find_best_dpll;
9329 else
9330 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9331
9332 if (HAS_DDI(dev)) {
9333 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
9334 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
9335 dev_priv->display.crtc_enable = haswell_crtc_enable;
9336 dev_priv->display.crtc_disable = haswell_crtc_disable;
9337 dev_priv->display.off = haswell_crtc_off;
9338 dev_priv->display.update_plane = ironlake_update_plane;
9339 } else if (HAS_PCH_SPLIT(dev)) {
9340 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
9341 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
9342 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9343 dev_priv->display.crtc_disable = ironlake_crtc_disable;
9344 dev_priv->display.off = ironlake_crtc_off;
9345 dev_priv->display.update_plane = ironlake_update_plane;
9346 } else if (IS_VALLEYVIEW(dev)) {
9347 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9348 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9349 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9350 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9351 dev_priv->display.off = i9xx_crtc_off;
9352 dev_priv->display.update_plane = i9xx_update_plane;
9353 } else {
9354 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9355 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9356 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9357 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9358 dev_priv->display.off = i9xx_crtc_off;
9359 dev_priv->display.update_plane = i9xx_update_plane;
9360 }
9361
9362 /* Returns the core display clock speed */
9363 if (IS_VALLEYVIEW(dev))
9364 dev_priv->display.get_display_clock_speed =
9365 valleyview_get_display_clock_speed;
9366 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
9367 dev_priv->display.get_display_clock_speed =
9368 i945_get_display_clock_speed;
9369 else if (IS_I915G(dev))
9370 dev_priv->display.get_display_clock_speed =
9371 i915_get_display_clock_speed;
9372 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
9373 dev_priv->display.get_display_clock_speed =
9374 i9xx_misc_get_display_clock_speed;
9375 else if (IS_I915GM(dev))
9376 dev_priv->display.get_display_clock_speed =
9377 i915gm_get_display_clock_speed;
9378 else if (IS_I865G(dev))
9379 dev_priv->display.get_display_clock_speed =
9380 i865_get_display_clock_speed;
9381 else if (IS_I85X(dev))
9382 dev_priv->display.get_display_clock_speed =
9383 i855_get_display_clock_speed;
9384 else /* 852, 830 */
9385 dev_priv->display.get_display_clock_speed =
9386 i830_get_display_clock_speed;
9387
9388 if (HAS_PCH_SPLIT(dev)) {
9389 if (IS_GEN5(dev)) {
9390 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
9391 dev_priv->display.write_eld = ironlake_write_eld;
9392 } else if (IS_GEN6(dev)) {
9393 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
9394 dev_priv->display.write_eld = ironlake_write_eld;
9395 } else if (IS_IVYBRIDGE(dev)) {
9396 /* FIXME: detect B0+ stepping and use auto training */
9397 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
9398 dev_priv->display.write_eld = ironlake_write_eld;
9399 dev_priv->display.modeset_global_resources =
9400 ivb_modeset_global_resources;
9401 } else if (IS_HASWELL(dev)) {
9402 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
9403 dev_priv->display.write_eld = haswell_write_eld;
9404 dev_priv->display.modeset_global_resources =
9405 haswell_modeset_global_resources;
9406 }
9407 } else if (IS_G4X(dev)) {
9408 dev_priv->display.write_eld = g4x_write_eld;
9409 }
9410
9411 /* Default just returns -ENODEV to indicate unsupported */
9412 dev_priv->display.queue_flip = intel_default_queue_flip;
9413
9414 switch (INTEL_INFO(dev)->gen) {
9415 case 2:
9416 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9417 break;
9418
9419 case 3:
9420 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9421 break;
9422
9423 case 4:
9424 case 5:
9425 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9426 break;
9427
9428 case 6:
9429 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9430 break;
9431 case 7:
9432 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9433 break;
9434 }
9435 }
9436
9437 /*
9438 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9439 * resume, or other times. This quirk makes sure that's the case for
9440 * affected systems.
9441 */
quirk_pipea_force(struct drm_device * dev)9442 static void quirk_pipea_force (struct drm_device *dev)
9443 {
9444 struct drm_i915_private *dev_priv = dev->dev_private;
9445
9446 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
9447 DRM_INFO("applying pipe a force quirk\n");
9448 }
9449
9450 /*
9451 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9452 */
quirk_ssc_force_disable(struct drm_device * dev)9453 static void quirk_ssc_force_disable(struct drm_device *dev)
9454 {
9455 struct drm_i915_private *dev_priv = dev->dev_private;
9456 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
9457 DRM_INFO("applying lvds SSC disable quirk\n");
9458 }
9459
9460 /*
9461 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9462 * brightness value
9463 */
quirk_invert_brightness(struct drm_device * dev)9464 static void quirk_invert_brightness(struct drm_device *dev)
9465 {
9466 struct drm_i915_private *dev_priv = dev->dev_private;
9467 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
9468 DRM_INFO("applying inverted panel brightness quirk\n");
9469 }
9470
9471 #if 0
9472 /*
9473 * Some machines (Dell XPS13) suffer broken backlight controls if
9474 * BLM_PCH_PWM_ENABLE is set.
9475 */
9476 static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
9477 {
9478 struct drm_i915_private *dev_priv = dev->dev_private;
9479 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
9480 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
9481 }
9482
9483 struct intel_quirk {
9484 int device;
9485 int subsystem_vendor;
9486 int subsystem_device;
9487 void (*hook)(struct drm_device *dev);
9488 };
9489
9490 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9491 struct intel_dmi_quirk {
9492 void (*hook)(struct drm_device *dev);
9493 const struct dmi_system_id (*dmi_id_list)[];
9494 };
9495
9496 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9497 {
9498 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9499 return 1;
9500 }
9501
9502 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9503 {
9504 .dmi_id_list = &(const struct dmi_system_id[]) {
9505 {
9506 .callback = intel_dmi_reverse_brightness,
9507 .ident = "NCR Corporation",
9508 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9509 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9510 },
9511 },
9512 { } /* terminating entry */
9513 },
9514 .hook = quirk_invert_brightness,
9515 },
9516 };
9517
9518 static struct intel_quirk intel_quirks[] = {
9519 /* HP Mini needs pipe A force quirk (LP: #322104) */
9520 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
9521
9522 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9523 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9524
9525 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9526 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9527
9528 /* 830/845 need to leave pipe A & dpll A up */
9529 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9530 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9531
9532 /* Lenovo U160 cannot use SSC on LVDS */
9533 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
9534
9535 /* Sony Vaio Y cannot use SSC on LVDS */
9536 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
9537
9538 /* Acer Aspire 5734Z must invert backlight brightness */
9539 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
9540
9541 /* Acer/eMachines G725 */
9542 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
9543
9544 /* Acer/eMachines e725 */
9545 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
9546
9547 /* Acer/Packard Bell NCL20 */
9548 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
9549
9550 /* Acer Aspire 4736Z */
9551 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
9552
9553 /* Dell XPS13 HD Sandy Bridge */
9554 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
9555 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
9556 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
9557 };
9558
9559 static void intel_init_quirks(struct drm_device *dev)
9560 {
9561 struct pci_dev *d = dev->pdev;
9562 int i;
9563
9564 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9565 struct intel_quirk *q = &intel_quirks[i];
9566
9567 if (d->device == q->device &&
9568 (d->subsystem_vendor == q->subsystem_vendor ||
9569 q->subsystem_vendor == PCI_ANY_ID) &&
9570 (d->subsystem_device == q->subsystem_device ||
9571 q->subsystem_device == PCI_ANY_ID))
9572 q->hook(dev);
9573 }
9574 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9575 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9576 intel_dmi_quirks[i].hook(dev);
9577 }
9578 }
9579 #endif
9580 /* Disable the VGA plane that we never use */
i915_disable_vga(struct drm_device * dev)9581 static void i915_disable_vga(struct drm_device *dev)
9582 {
9583 struct drm_i915_private *dev_priv = dev->dev_private;
9584 u8 sr1;
9585 u32 vga_reg = i915_vgacntrl_reg(dev);
9586
9587 I915_WRITE8(VGA_SR_INDEX, SR01);
9588 sr1 = I915_READ8(VGA_SR_DATA);
9589 I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
9590 udelay(300);
9591
9592 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9593 POSTING_READ(vga_reg);
9594 }
9595
intel_modeset_init_hw(struct drm_device * dev)9596 void intel_modeset_init_hw(struct drm_device *dev)
9597 {
9598 intel_init_power_well(dev);
9599
9600 intel_prepare_ddi(dev);
9601
9602 intel_init_clock_gating(dev);
9603
9604 mutex_lock(&dev->struct_mutex);
9605 intel_enable_gt_powersave(dev);
9606 mutex_unlock(&dev->struct_mutex);
9607 }
9608
intel_modeset_suspend_hw(struct drm_device * dev)9609 void intel_modeset_suspend_hw(struct drm_device *dev)
9610 {
9611 intel_suspend_hw(dev);
9612 }
9613
intel_modeset_init(struct drm_device * dev)9614 void intel_modeset_init(struct drm_device *dev)
9615 {
9616 struct drm_i915_private *dev_priv = dev->dev_private;
9617 int i, j, ret;
9618
9619 drm_mode_config_init(dev);
9620
9621 dev->mode_config.min_width = 0;
9622 dev->mode_config.min_height = 0;
9623
9624 dev->mode_config.preferred_depth = 24;
9625 dev->mode_config.prefer_shadow = 1;
9626
9627 dev->mode_config.funcs = (void *)&intel_mode_funcs;
9628
9629 /* OSOL_I915 intel_init_quirks(dev); */
9630
9631 intel_init_pm(dev);
9632
9633 if (INTEL_INFO(dev)->num_pipes == 0)
9634 return;
9635
9636 intel_init_display(dev);
9637
9638 if (IS_GEN2(dev)) {
9639 dev->mode_config.max_width = 2048;
9640 dev->mode_config.max_height = 2048;
9641 } else if (IS_GEN3(dev)) {
9642 dev->mode_config.max_width = 4096;
9643 dev->mode_config.max_height = 4096;
9644 } else {
9645 dev->mode_config.max_width = 8192;
9646 dev->mode_config.max_height = 8192;
9647 }
9648 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
9649
9650 DRM_DEBUG_KMS("%d display pipe%s available.\n",
9651 INTEL_INFO(dev)->num_pipes,
9652 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
9653
9654 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
9655 intel_crtc_init(dev, i);
9656 for (j = 0; j < dev_priv->num_plane; j++) {
9657 ret = intel_plane_init(dev, i, j);
9658 if (ret)
9659 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9660 pipe_name(i), sprite_name(i, j), ret);
9661 }
9662 }
9663
9664 intel_cpu_pll_init(dev);
9665 intel_shared_dpll_init(dev);
9666
9667 /* Just disable it once at startup */
9668 i915_disable_vga(dev);
9669 intel_setup_outputs(dev);
9670
9671 /* Just in case the BIOS is doing something questionable. */
9672 intel_disable_fbc(dev);
9673 }
9674
9675 static void
intel_connector_break_all_links(struct intel_connector * connector)9676 intel_connector_break_all_links(struct intel_connector *connector)
9677 {
9678 connector->base.dpms = DRM_MODE_DPMS_OFF;
9679 connector->base.encoder = NULL;
9680 connector->encoder->connectors_active = false;
9681 connector->encoder->base.crtc = NULL;
9682 }
9683
intel_enable_pipe_a(struct drm_device * dev)9684 static void intel_enable_pipe_a(struct drm_device *dev)
9685 {
9686 struct intel_connector *connector;
9687 struct drm_connector *crt = NULL;
9688 struct intel_load_detect_pipe load_detect_temp;
9689
9690 /* We can't just switch on the pipe A, we need to set things up with a
9691 * proper mode and output configuration. As a gross hack, enable pipe A
9692 * by enabling the load detect pipe once. */
9693 list_for_each_entry(connector, struct intel_connector,
9694 &dev->mode_config.connector_list,
9695 base.head) {
9696 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9697 crt = &connector->base;
9698 break;
9699 }
9700 }
9701
9702 if (!crt)
9703 return;
9704
9705 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9706 intel_release_load_detect_pipe(crt, &load_detect_temp);
9707
9708
9709 }
9710
9711 static bool
intel_check_plane_mapping(struct intel_crtc * crtc)9712 intel_check_plane_mapping(struct intel_crtc *crtc)
9713 {
9714 struct drm_device *dev = crtc->base.dev;
9715 struct drm_i915_private *dev_priv = dev->dev_private;
9716 u32 reg, val;
9717
9718 if (INTEL_INFO(dev)->num_pipes == 1)
9719 return true;
9720
9721 reg = DSPCNTR(!crtc->plane);
9722 val = I915_READ(reg);
9723
9724 if ((val & DISPLAY_PLANE_ENABLE) &&
9725 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9726 return false;
9727
9728 return true;
9729 }
9730
intel_sanitize_crtc(struct intel_crtc * crtc)9731 static void intel_sanitize_crtc(struct intel_crtc *crtc)
9732 {
9733 struct drm_device *dev = crtc->base.dev;
9734 struct drm_i915_private *dev_priv = dev->dev_private;
9735 u32 reg;
9736
9737 /* Clear any frame start delays used for debugging left by the BIOS */
9738 reg = PIPECONF(crtc->config.cpu_transcoder);
9739 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9740
9741 /* We need to sanitize the plane -> pipe mapping first because this will
9742 * disable the crtc (and hence change the state) if it is wrong. Note
9743 * that gen4+ has a fixed plane -> pipe mapping. */
9744 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
9745 struct intel_connector *connector;
9746 bool plane;
9747
9748 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9749 crtc->base.base.id);
9750
9751 /* Pipe has the wrong plane attached and the plane is active.
9752 * Temporarily change the plane mapping and disable everything
9753 * ... */
9754 plane = crtc->plane;
9755 crtc->plane = !plane;
9756 dev_priv->display.crtc_disable(&crtc->base);
9757 crtc->plane = plane;
9758
9759 /* ... and break all links. */
9760 list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
9761 base.head) {
9762 if (connector->encoder->base.crtc != &crtc->base)
9763 continue;
9764
9765 intel_connector_break_all_links(connector);
9766 }
9767
9768 WARN_ON(crtc->active);
9769 crtc->base.enabled = false;
9770 }
9771
9772 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9773 crtc->pipe == PIPE_A && !crtc->active) {
9774 /* BIOS forgot to enable pipe A, this mostly happens after
9775 * resume. Force-enable the pipe to fix this, the update_dpms
9776 * call below we restore the pipe to the right state, but leave
9777 * the required bits on. */
9778 intel_enable_pipe_a(dev);
9779 }
9780
9781 /* Adjust the state of the output pipe according to whether we
9782 * have active connectors/encoders. */
9783 intel_crtc_update_dpms(&crtc->base);
9784
9785 if (crtc->active != crtc->base.enabled) {
9786 struct intel_encoder *encoder;
9787
9788 /* This can happen either due to bugs in the get_hw_state
9789 * functions or because the pipe is force-enabled due to the
9790 * pipe A quirk. */
9791 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9792 crtc->base.base.id,
9793 crtc->base.enabled ? "enabled" : "disabled",
9794 crtc->active ? "enabled" : "disabled");
9795
9796 crtc->base.enabled = crtc->active;
9797
9798 /* Because we only establish the connector -> encoder ->
9799 * crtc links if something is active, this means the
9800 * crtc is now deactivated. Break the links. connector
9801 * -> encoder links are only establish when things are
9802 * actually up, hence no need to break them. */
9803 WARN_ON(crtc->active);
9804
9805 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9806 WARN_ON(encoder->connectors_active);
9807 encoder->base.crtc = NULL;
9808 }
9809 }
9810 }
9811
intel_sanitize_encoder(struct intel_encoder * encoder)9812 static void intel_sanitize_encoder(struct intel_encoder *encoder)
9813 {
9814 struct intel_connector *connector;
9815 struct drm_device *dev = encoder->base.dev;
9816
9817 /* We need to check both for a crtc link (meaning that the
9818 * encoder is active and trying to read from a pipe) and the
9819 * pipe itself being active. */
9820 bool has_active_crtc = encoder->base.crtc &&
9821 to_intel_crtc(encoder->base.crtc)->active;
9822
9823 if (encoder->connectors_active && !has_active_crtc) {
9824 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9825 encoder->base.base.id,
9826 drm_get_encoder_name(&encoder->base));
9827
9828 /* Connector is active, but has no active pipe. This is
9829 * fallout from our resume register restoring. Disable
9830 * the encoder manually again. */
9831 if (encoder->base.crtc) {
9832 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9833 encoder->base.base.id,
9834 drm_get_encoder_name(&encoder->base));
9835 encoder->disable(encoder);
9836 }
9837
9838 /* Inconsistent output/port/pipe state happens presumably due to
9839 * a bug in one of the get_hw_state functions. Or someplace else
9840 * in our code, like the register restore mess on resume. Clamp
9841 * things to off as a safer default. */
9842 list_for_each_entry(connector, struct intel_connector,
9843 &dev->mode_config.connector_list,
9844 base.head) {
9845 if (connector->encoder != encoder)
9846 continue;
9847
9848 intel_connector_break_all_links(connector);
9849 }
9850 }
9851 /* Enabled encoders without active connectors will be fixed in
9852 * the crtc fixup. */
9853 }
9854
i915_redisable_vga(struct drm_device * dev)9855 void i915_redisable_vga(struct drm_device *dev)
9856 {
9857 struct drm_i915_private *dev_priv = dev->dev_private;
9858 u32 vga_reg = i915_vgacntrl_reg(dev);
9859
9860 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9861 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
9862 i915_disable_vga(dev);
9863 }
9864 }
9865
intel_modeset_readout_hw_state(struct drm_device * dev)9866 static void intel_modeset_readout_hw_state(struct drm_device *dev)
9867 {
9868 struct drm_i915_private *dev_priv = dev->dev_private;
9869 enum pipe pipe;
9870 struct intel_crtc *crtc;
9871 struct intel_encoder *encoder;
9872 struct intel_connector *connector;
9873 int i;
9874
9875 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list,
9876 base.head) {
9877 (void) memset(&crtc->config, 0, sizeof(crtc->config));
9878
9879 crtc->active = dev_priv->display.get_pipe_config(crtc,
9880 &crtc->config);
9881
9882 crtc->base.enabled = crtc->active;
9883
9884 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9885 crtc->base.base.id,
9886 crtc->active ? "enabled" : "disabled");
9887 }
9888
9889 /* FIXME: Smash this into the new shared dpll infrastructure. */
9890 if (HAS_DDI(dev))
9891 intel_ddi_setup_hw_pll_state(dev);
9892
9893 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9894 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9895
9896 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9897 pll->active = 0;
9898 list_for_each_entry(crtc, struct intel_crtc, &dev->mode_config.crtc_list,
9899 base.head) {
9900 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9901 pll->active++;
9902 }
9903 pll->refcount = pll->active;
9904
9905 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
9906 pll->name, pll->refcount, pll->on);
9907 }
9908
9909 list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
9910 base.head) {
9911 pipe = 0;
9912
9913 if (encoder->get_hw_state(encoder, &pipe)) {
9914 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9915 encoder->base.crtc = &crtc->base;
9916 if (encoder->get_config)
9917 encoder->get_config(encoder, &crtc->config);
9918 } else {
9919 encoder->base.crtc = NULL;
9920 }
9921
9922 encoder->connectors_active = false;
9923 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9924 encoder->base.base.id,
9925 drm_get_encoder_name(&encoder->base),
9926 encoder->base.crtc ? "enabled" : "disabled",
9927 pipe);
9928 }
9929
9930 list_for_each_entry(connector, struct intel_connector, &dev->mode_config.connector_list,
9931 base.head) {
9932 if (connector->get_hw_state(connector)) {
9933 connector->base.dpms = DRM_MODE_DPMS_ON;
9934 connector->encoder->connectors_active = true;
9935 connector->base.encoder = &connector->encoder->base;
9936 } else {
9937 connector->base.dpms = DRM_MODE_DPMS_OFF;
9938 connector->base.encoder = NULL;
9939 }
9940 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9941 connector->base.base.id,
9942 drm_get_connector_name(&connector->base),
9943 connector->base.encoder ? "enabled" : "disabled");
9944 }
9945 }
9946
9947 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9948 * and i915 state tracking structures. */
intel_modeset_setup_hw_state(struct drm_device * dev,bool force_restore)9949 void intel_modeset_setup_hw_state(struct drm_device *dev,
9950 bool force_restore)
9951 {
9952 struct drm_i915_private *dev_priv = dev->dev_private;
9953 enum pipe pipe;
9954 struct drm_plane *plane;
9955 struct intel_crtc *crtc;
9956 struct intel_encoder *encoder;
9957 int i;
9958
9959 intel_modeset_readout_hw_state(dev);
9960
9961 /* HW state is read out, now we need to sanitize this mess. */
9962 list_for_each_entry(encoder, struct intel_encoder, &dev->mode_config.encoder_list,
9963 base.head) {
9964 intel_sanitize_encoder(encoder);
9965 }
9966
9967 for_each_pipe(pipe) {
9968 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9969 intel_sanitize_crtc(crtc);
9970 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
9971 }
9972
9973 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9974 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9975
9976 if (!pll->on || pll->active)
9977 continue;
9978
9979 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
9980
9981 pll->disable(dev_priv, pll);
9982 pll->on = false;
9983 }
9984
9985 if (force_restore) {
9986 /*
9987 * We need to use raw interfaces for restoring state to avoid
9988 * checking (bogus) intermediate states.
9989 */
9990 for_each_pipe(pipe) {
9991 struct drm_crtc *crtc =
9992 dev_priv->pipe_to_crtc_mapping[pipe];
9993
9994 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9995 crtc->fb);
9996 }
9997 list_for_each_entry(plane, struct drm_plane, &dev->mode_config.plane_list, head)
9998 intel_plane_restore(plane);
9999
10000 i915_redisable_vga(dev);
10001 } else {
10002 intel_modeset_update_staged_output_state(dev);
10003 }
10004
10005 intel_modeset_check_state(dev);
10006
10007 drm_mode_config_reset(dev);
10008 }
10009
intel_modeset_gem_init(struct drm_device * dev)10010 void intel_modeset_gem_init(struct drm_device *dev)
10011 {
10012 intel_modeset_init_hw(dev);
10013
10014 intel_setup_overlay(dev);
10015
10016 intel_modeset_setup_hw_state(dev, false);
10017 }
10018
intel_modeset_cleanup(struct drm_device * dev)10019 void intel_modeset_cleanup(struct drm_device *dev)
10020 {
10021 struct drm_i915_private *dev_priv = dev->dev_private;
10022 struct drm_crtc *crtc;
10023 /* LINTED */
10024 struct intel_crtc *intel_crtc;
10025
10026 /*
10027 * Interrupts and polling as the first thing to avoid creating havoc.
10028 * Too much stuff here (turning of rps, connectors, ...) would
10029 * experience fancy races otherwise.
10030 */
10031 drm_irq_uninstall(dev);
10032 /* OSOL_I915 cancel_work_sync(&dev_priv->hotplug_work); */
10033 cancel_delayed_work(dev_priv->wq);
10034 /*
10035 * Due to the hpd irq storm handling the hotplug work can re-arm the
10036 * poll handlers. Hence disable polling after hpd handling is shut down.
10037 */
10038 drm_kms_helper_poll_fini(dev);
10039 mutex_lock(&dev->struct_mutex);
10040
10041 list_for_each_entry(crtc, struct drm_crtc, &dev->mode_config.crtc_list, head) {
10042 /* Skip inactive CRTCs */
10043 if (!crtc->fb)
10044 continue;
10045
10046 intel_crtc = to_intel_crtc(crtc);
10047 intel_increase_pllclock(crtc);
10048 }
10049
10050 intel_disable_fbc(dev);
10051
10052 intel_disable_gt_powersave(dev);
10053
10054 ironlake_teardown_rc6(dev);
10055
10056 mutex_unlock(&dev->struct_mutex);
10057
10058 /* flush any delayed tasks or pending work */
10059 /* OSOL_I915 flush_scheduled_work(); */
10060
10061 /* destroy backlight, if any, before the connectors */
10062 intel_panel_destroy_backlight(dev);
10063
10064 drm_mode_config_cleanup(dev);
10065
10066 intel_cleanup_overlay(dev);
10067 }
10068
10069
10070 /* current intel driver doesn't take advantage of encoders
10071 always give back the encoder for the connector
10072 */
intel_best_encoder(struct drm_connector * connector)10073 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
10074 {
10075 return &intel_attached_encoder(connector)->base;
10076 }
10077
intel_connector_attach_encoder(struct intel_connector * connector,struct intel_encoder * encoder)10078 void intel_connector_attach_encoder(struct intel_connector *connector,
10079 struct intel_encoder *encoder)
10080 {
10081 connector->encoder = encoder;
10082 (void) drm_mode_connector_attach_encoder(&connector->base,
10083 &encoder->base);
10084 }
10085
10086 /*
10087 * set vga decode state - true == enable VGA decode
10088 */
intel_modeset_vga_set_state(struct drm_device * dev,bool state)10089 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10090 {
10091 u16 gmch_ctrl;
10092
10093 pci_read_config_word(dev->pdev, INTEL_GMCH_CTRL, &gmch_ctrl);
10094 if (state)
10095 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10096 else
10097 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10098 pci_write_config_word(dev->pdev, INTEL_GMCH_CTRL, gmch_ctrl);
10099 return 0;
10100 }
10101
10102 #ifdef CONFIG_DEBUG_FS
10103 #include <linux/seq_file.h>
10104
10105 struct intel_display_error_state {
10106
10107 u32 power_well_driver;
10108
10109 int num_transcoders;
10110
10111 struct intel_cursor_error_state {
10112 u32 control;
10113 u32 position;
10114 u32 base;
10115 u32 size;
10116 } cursor[I915_MAX_PIPES];
10117
10118 struct intel_pipe_error_state {
10119 u32 source;
10120 } pipe[I915_MAX_PIPES];
10121
10122 struct intel_plane_error_state {
10123 u32 control;
10124 u32 stride;
10125 u32 size;
10126 u32 pos;
10127 u32 addr;
10128 u32 surface;
10129 u32 tile_offset;
10130 } plane[I915_MAX_PIPES];
10131
10132 struct intel_transcoder_error_state {
10133 enum transcoder cpu_transcoder;
10134
10135 u32 conf;
10136
10137 u32 htotal;
10138 u32 hblank;
10139 u32 hsync;
10140 u32 vtotal;
10141 u32 vblank;
10142 u32 vsync;
10143 } transcoder[4];
10144
10145 };
10146
10147 struct intel_display_error_state *
intel_display_capture_error_state(struct drm_device * dev)10148 intel_display_capture_error_state(struct drm_device *dev)
10149 {
10150 drm_i915_private_t *dev_priv = dev->dev_private;
10151 struct intel_display_error_state *error;
10152 int transcoders[4] = {
10153 TRANSCODER_A,
10154 TRANSCODER_B,
10155 TRANSCODER_C,
10156 TRANSCODER_EDP,
10157 };
10158 int i;
10159
10160 if (INTEL_INFO(dev)->num_pipes == 0)
10161 return NULL;
10162
10163 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10164 if (error == NULL)
10165 return NULL;
10166
10167 if (HAS_POWER_WELL(dev))
10168 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10169
10170 for_each_pipe(i) {
10171
10172 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10173 error->cursor[i].control = I915_READ(CURCNTR(i));
10174 error->cursor[i].position = I915_READ(CURPOS(i));
10175 error->cursor[i].base = I915_READ(CURBASE(i));
10176 } else {
10177 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10178 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10179 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10180 }
10181
10182 error->plane[i].control = I915_READ(DSPCNTR(i));
10183 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
10184 if (INTEL_INFO(dev)->gen <= 3) {
10185 error->plane[i].size = I915_READ(DSPSIZE(i));
10186 error->plane[i].pos = I915_READ(DSPPOS(i));
10187 }
10188 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10189 error->plane[i].addr = I915_READ(DSPADDR(i));
10190 if (INTEL_INFO(dev)->gen >= 4) {
10191 error->plane[i].surface = I915_READ(DSPSURF(i));
10192 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10193 }
10194
10195 error->pipe[i].source = I915_READ(PIPESRC(i));
10196 }
10197 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10198 if (HAS_DDI(dev_priv->dev))
10199 error->num_transcoders++; /* Account for eDP. */
10200
10201 for (i = 0; i < error->num_transcoders; i++) {
10202 enum transcoder cpu_transcoder = transcoders[i];
10203
10204 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10205
10206 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10207 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10208 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10209 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10210 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10211 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10212 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
10213 }
10214
10215 /* In the code above we read the registers without checking if the power
10216 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10217 * prevent the next I915_WRITE from detecting it and printing an error
10218 * message. */
10219 if (HAS_POWER_WELL(dev))
10220 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10221
10222 return error;
10223 }
10224
10225 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10226
10227 void
intel_display_print_error_state(struct drm_i915_error_state_buf * m,struct drm_device * dev,struct intel_display_error_state * error)10228 intel_display_print_error_state(struct drm_i915_error_state_buf *m,
10229 struct drm_device *dev,
10230 struct intel_display_error_state *error)
10231 {
10232 int i;
10233
10234 if (!error)
10235 return;
10236
10237 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
10238 if (HAS_POWER_WELL(dev))
10239 err_printf(m, "PWR_WELL_CTL2: %08x\n",
10240 error->power_well_driver);
10241 for_each_pipe(i) {
10242 err_printf(m, "Pipe [%d]:\n", i);
10243 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10244
10245 err_printf(m, "Plane [%d]:\n", i);
10246 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10247 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
10248 if (INTEL_INFO(dev)->gen <= 3) {
10249 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10250 err_printf(m, " POS: %08x\n", error->plane[i].pos);
10251 }
10252 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10253 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
10254 if (INTEL_INFO(dev)->gen >= 4) {
10255 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10256 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
10257 }
10258
10259 err_printf(m, "Cursor [%d]:\n", i);
10260 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10261 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10262 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
10263 }
10264
10265 for (i = 0; i < error->num_transcoders; i++) {
10266 err_printf(m, " CPU transcoder: %c\n",
10267 transcoder_name(error->transcoder[i].cpu_transcoder));
10268 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10269 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10270 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10271 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10272 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10273 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10274 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10275 + }
10276 }
10277 #endif
10278