xref: /gfx-drm/usr/src/uts/intel/io/i915/i915_drv.h (revision e49fc716)
1 /*
2  * Copyright (c) 2006, 2016, Oracle and/or its affiliates. All rights reserved.
3  */
4 
5 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
6  */
7 /*
8  *
9  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
10  * Copyright (c) 2009, 2013, Intel Corporation.
11  * All Rights Reserved.
12  *
13  * Permission is hereby granted, free of charge, to any person obtaining a
14  * copy of this software and associated documentation files (the
15  * "Software"), to deal in the Software without restriction, including
16  * without limitation the rights to use, copy, modify, merge, publish,
17  * distribute, sub license, and/or sell copies of the Software, and to
18  * permit persons to whom the Software is furnished to do so, subject to
19  * the following conditions:
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
26  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
28  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
29  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
30  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
31  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
32  *
33  */
34 
35 #ifndef _I915_DRV_H_
36 #define _I915_DRV_H_
37 
38 #include "i915_drm.h"
39 #include "i915_reg.h"
40 #include "intel_bios.h"
41 #include "intel_ringbuffer.h"
42 
43 #include <sys/systm.h> /* for __lintzero */
44 
45 /* General customization:
46  */
47 
48 #define DRIVER_AUTHOR		"Tungsten Graphics, Inc."
49 
50 #define DRIVER_NAME		"i915"
51 #define DRIVER_DESC		"Intel Graphics for Solaris"
52 #define DRIVER_DATE		"2013/06/19"
53 
54 enum pipe {
55 	PIPE_A = 0,
56 	PIPE_B,
57 	PIPE_C,
58 	I915_MAX_PIPES
59 };
60 #define pipe_name(p) ((p) + 'A')
61 
62 enum transcoder {
63 	TRANSCODER_A = 0,
64 	TRANSCODER_B,
65 	TRANSCODER_C,
66 	TRANSCODER_EDP = 0xF,
67 };
68 #define transcoder_name(t) ((t) + 'A')
69 
70 enum plane {
71 	PLANE_A = 0,
72 	PLANE_B,
73 	PLANE_C,
74 };
75 #define plane_name(p) ((p) + 'A')
76 
77 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
78 
79 enum port {
80 	PORT_A = 0,
81 	PORT_B,
82 	PORT_C,
83 	PORT_D,
84 	PORT_E,
85 	I915_MAX_PORTS
86 };
87 #define port_name(p) ((p) + 'A')
88 
89 enum intel_display_power_domain {
90 	POWER_DOMAIN_PIPE_A,
91 	POWER_DOMAIN_PIPE_B,
92 	POWER_DOMAIN_PIPE_C,
93 	POWER_DOMAIN_PIPE_A_PANEL_FITTER,
94 	POWER_DOMAIN_PIPE_B_PANEL_FITTER,
95 	POWER_DOMAIN_PIPE_C_PANEL_FITTER,
96 	POWER_DOMAIN_TRANSCODER_A,
97 	POWER_DOMAIN_TRANSCODER_B,
98 	POWER_DOMAIN_TRANSCODER_C,
99 	POWER_DOMAIN_TRANSCODER_EDP = POWER_DOMAIN_TRANSCODER_A + 0xF,
100 };
101 
102 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
103 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
104 		((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
105 #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)
106 
107 enum hpd_pin {
108 	HPD_NONE = 0,
109 	HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
110 	HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
111 	HPD_CRT,
112 	HPD_SDVO_B,
113 	HPD_SDVO_C,
114 	HPD_PORT_B,
115 	HPD_PORT_C,
116 	HPD_PORT_D,
117 	HPD_NUM_PINS
118 };
119 
120 #define I915_GEM_GPU_DOMAINS \
121 	(I915_GEM_DOMAIN_RENDER | \
122 	 I915_GEM_DOMAIN_SAMPLER | \
123 	 I915_GEM_DOMAIN_COMMAND | \
124 	 I915_GEM_DOMAIN_INSTRUCTION | \
125 	 I915_GEM_DOMAIN_VERTEX)
126 
127 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
128 
129 #define for_each_encoder_on_crtc(dev, __crtc, _intel_encoder) \
130 	list_for_each_entry((_intel_encoder), struct intel_encoder, &(dev)->mode_config.encoder_list, base.head) \
131 		if ((_intel_encoder)->base.crtc == (__crtc))
132 
133 struct drm_i915_private;
134 
135 enum intel_dpll_id {
136 	DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
137 	/* real shared dpll ids must be >= 0 */
138 	DPLL_ID_PCH_PLL_A,
139 	DPLL_ID_PCH_PLL_B,
140 };
141 #define I915_NUM_PLLS 2
142 
143 struct intel_dpll_hw_state {
144 	uint32_t dpll;
145 	uint32_t fp0;
146 	uint32_t fp1;
147 };
148 
149 struct intel_shared_dpll {
150 	int refcount; /* count of number of CRTCs sharing this PLL */
151 	int active; /* count of number of active CRTCs (i.e. DPMS on) */
152 	bool on; /* is the PLL actually active? Disabled during modeset */
153 	const char *name;
154 	/* should match the index in the dev_priv->shared_dplls array */
155 	enum intel_dpll_id id;
156 	struct intel_dpll_hw_state hw_state;
157 	void (*enable)(struct drm_i915_private *dev_priv,
158 		       struct intel_shared_dpll *pll);
159 	void (*disable)(struct drm_i915_private *dev_priv,
160 			struct intel_shared_dpll *pll);
161 	bool (*get_hw_state)(struct drm_i915_private *dev_priv,
162 			     struct intel_shared_dpll *pll,
163 			     struct intel_dpll_hw_state *hw_state);
164 };
165 
166 /* Used by dp and fdi links */
167 struct intel_link_m_n {
168 	uint32_t	tu;
169 	uint32_t	gmch_m;
170 	uint32_t	gmch_n;
171 	uint32_t	link_m;
172 	uint32_t	link_n;
173 };
174 
175 void intel_link_compute_m_n(int bpp, int nlanes,
176 			    int pixel_clock, int link_clock,
177 			    struct intel_link_m_n *m_n);
178 
179 extern int gpu_dump;
180 
181 struct intel_ddi_plls {
182 	int spll_refcount;
183 	int wrpll1_refcount;
184 	int wrpll2_refcount;
185 };
186 
187 /* Interface history:
188  *
189  * 1.1: Original.
190  * 1.2: Add Power Management
191  * 1.3: Add vblank support
192  * 1.4: Fix cmdbuffer path, add heap destroy
193  * 1.5: Add vblank pipe configuration
194  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
195  *      - Support vertical blank on secondary display pipe
196  */
197 #define DRIVER_MAJOR		1
198 #define DRIVER_MINOR		6
199 #define DRIVER_PATCHLEVEL	20130900
200 
201 #define WATCH_COHERENCY	0
202 #define WATCH_LISTS	0
203 #define WATCH_GTT	0
204 
205 #define I915_GEM_PHYS_CURSOR_0 1
206 #define I915_GEM_PHYS_CURSOR_1 2
207 #define I915_GEM_PHYS_OVERLAY_REGS 3
208 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
209 
210 struct drm_i915_gem_phys_object {
211 	int id;
212 	struct page **page_list;
213 	drm_dma_handle_t *handle;
214 	struct drm_i915_gem_object *cur_obj;
215 };
216 
217 struct mem_block {
218 	struct mem_block *next;
219 	struct mem_block *prev;
220 	int start;
221 	int size;
222 	struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
223 };
224 
225 struct opregion_header;
226 struct opregion_acpi;
227 struct opregion_swsci;
228 struct opregion_asle;
229 
230 struct intel_opregion {
231 	struct opregion_header *header;
232 	struct opregion_acpi *acpi;
233 	struct opregion_swsci *swsci;
234 	struct opregion_asle *asle;
235 	void *vbt;
236 	u32 *lid_state;
237 };
238 #define OPREGION_SIZE            (8*1024)
239 
240 struct intel_overlay;
241 struct intel_overlay_error_state;
242 
243 struct drm_i915_master_private {
244 	drm_local_map_t *sarea;
245 	struct _drm_i915_sarea *sarea_priv;
246 };
247 #define I915_FENCE_REG_NONE -1
248 #define I915_MAX_NUM_FENCES 32
249 /* 16 fences + sign bit for FENCE_REG_NONE */
250 #define I915_MAX_NUM_FENCE_BITS 6
251 
252 struct drm_i915_fence_reg {
253 	struct list_head lru_list;
254 	struct drm_i915_gem_object *obj;
255 	int pin_count;
256 };
257 
258 #define I2C_NAME_SIZE	20
259 
260 struct sdvo_device_mapping {
261 	u8 initialized;
262 	u8 dvo_port;
263 	u8 slave_addr;
264 	u8 dvo_wiring;
265 	u8 i2c_pin;
266 	u8 ddc_pin;
267 };
268 
269 struct intel_display_error_state;
270 struct drm_i915_error_state {
271 	struct kref ref;
272 	u32 eir;
273 	u32 pgtbl_er;
274 	u32 ier;
275 	u32 ccid;
276 	u32 derrmr;
277 	u32 forcewake;
278 	bool waiting[I915_NUM_RINGS];
279 	u32 pipestat[I915_MAX_PIPES];
280 	u32 tail[I915_NUM_RINGS];
281 	u32 head[I915_NUM_RINGS];
282 	u32 ctl[I915_NUM_RINGS];
283 	u32 ipeir[I915_NUM_RINGS];
284 	u32 ipehr[I915_NUM_RINGS];
285 	u32 instdone[I915_NUM_RINGS];
286 	u32 acthd[I915_NUM_RINGS];
287 	u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
288 	u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
289 	u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
290 	/* our own tracking of ring head and tail */
291 	u32 cpu_ring_head[I915_NUM_RINGS];
292 	u32 cpu_ring_tail[I915_NUM_RINGS];
293 	u32 error; /* gen6+ */
294 	u32 err_int; /* gen7 */
295 	u32 instpm[I915_NUM_RINGS];
296 	u32 instps[I915_NUM_RINGS];
297 	u32 extra_instdone[I915_NUM_INSTDONE_REG];
298 	u32 seqno[I915_NUM_RINGS];
299 	u64 bbaddr;
300 	u32 fault_reg[I915_NUM_RINGS];
301 	u32 done_reg;
302 	u32 faddr[I915_NUM_RINGS];
303 	u64 fence[I915_MAX_NUM_FENCES];
304 	struct timeval time;
305 	struct drm_i915_error_ring {
306 		struct drm_i915_error_object {
307 			int page_count;
308 			u32 gtt_offset;
309 			u32 **pages;
310 		} *ringbuffer, *batchbuffer;
311 		struct drm_i915_error_request {
312 			long err_jiffies;
313 			u32 seqno;
314 			u32 tail;
315 		} *requests;
316 		int num_requests;
317 	} ring[I915_NUM_RINGS];
318 	struct drm_i915_error_buffer {
319 		size_t size;
320 		u32 name;
321 		u32 rseqno, wseqno;
322 		u32 gtt_offset;
323 		u32 read_domains;
324 		u32 write_domain;
325 		s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
326 		s32 pinned:2;
327 		u32 tiling:2;
328 		u32 dirty:1;
329 		u32 purgeable:1;
330 		u32 ring:4;
331 		u32 cache_level:2;
332 	} *active_bo, *pinned_bo;
333 	u32 active_bo_count, pinned_bo_count;
334 	struct intel_overlay_error_state *overlay;
335 	struct intel_display_error_state *display;
336 };
337 
338 struct intel_crtc_config;
339 struct intel_crtc;
340 struct intel_limit;
341 struct dpll;
342 
343 struct drm_i915_display_funcs {
344 	bool (*fbc_enabled)(struct drm_device *dev);
345 	void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
346 	void (*disable_fbc)(struct drm_device *dev);
347 	int (*get_display_clock_speed)(struct drm_device *dev);
348 	int (*get_fifo_size)(struct drm_device *dev, int plane);
349 	/**
350 	 * find_dpll() - Find the best values for the PLL
351 	 * @limit: limits for the PLL
352 	 * @crtc: current CRTC
353 	 * @target: target frequency in kHz
354 	 * @refclk: reference clock frequency in kHz
355 	 * @match_clock: if provided, @best_clock P divider must
356 	 *               match the P divider from @match_clock
357 	 *               used for LVDS downclocking
358 	 * @best_clock: best PLL values found
359 	 *
360 	 * Returns true on success, false on failure.
361 	 */
362 	bool (*find_dpll)(const struct intel_limit *limit,
363 			  struct drm_crtc *crtc,
364 			  int target, int refclk,
365 			  struct dpll *match_clock,
366 			  struct dpll *best_clock);
367 	void (*update_wm)(struct drm_device *dev);
368 	void (*update_sprite_wm)(struct drm_device *dev, int pipe,
369 				 uint32_t sprite_width, int pixel_size,
370 				 bool enable);
371 	void (*modeset_global_resources)(struct drm_device *dev);
372 	/* Returns the active state of the crtc, and if the crtc is active,
373 	 * fills out the pipe-config with the hw state. */
374 	bool (*get_pipe_config)(struct intel_crtc *,
375 				struct intel_crtc_config *);
376 	int (*crtc_mode_set)(struct drm_crtc *crtc,
377 			     int x, int y,
378 			     struct drm_framebuffer *old_fb);
379 	void (*crtc_enable)(struct drm_crtc *crtc);
380 	void (*crtc_disable)(struct drm_crtc *crtc);
381 	void (*off)(struct drm_crtc *crtc);
382 	void (*write_eld)(struct drm_connector *connector,
383 			  struct drm_crtc *crtc);
384 	void (*fdi_link_train)(struct drm_crtc *crtc);
385 	void (*init_clock_gating)(struct drm_device *dev);
386 	int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
387 			struct drm_framebuffer *fb,
388 			struct drm_i915_gem_object *obj);
389 	int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
390 			    int x, int y);
391 	void (*hpd_irq_setup)(struct drm_device *dev);
392 	/* clock updates for mode set */
393 	/* cursor updates */
394 	/* render clock increase/decrease */
395 	/* display clock increase/decrease */
396 	/* pll clock increase/decrease */
397 };
398 
399 struct drm_i915_gt_funcs {
400 	void (*force_wake_get)(struct drm_i915_private *dev_priv);
401 	void (*force_wake_put)(struct drm_i915_private *dev_priv);
402 };
403 
404 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
405 	func(is_mobile) sep \
406 	func(is_i85x) sep \
407 	func(is_i915g) sep \
408 	func(is_i945gm) sep \
409 	func(is_g33) sep \
410 	func(need_gfx_hws) sep \
411 	func(is_g4x) sep \
412 	func(is_pineview) sep \
413 	func(is_broadwater) sep \
414 	func(is_crestline) sep \
415 	func(is_ivybridge) sep \
416 	func(is_valleyview) sep \
417 	func(is_haswell) sep \
418 	func(has_force_wake) sep \
419 	func(has_fbc) sep \
420 	func(has_pipe_cxsr) sep \
421 	func(has_hotplug) sep \
422 	func(cursor_needs_physical) sep \
423 	func(has_overlay) sep \
424 	func(overlay_needs_physical) sep \
425 	func(supports_tv) sep \
426 	func(has_bsd_ring) sep \
427 	func(has_blt_ring) sep \
428 	func(has_vebox_ring) sep \
429 	func(has_llc) sep \
430 	func(has_ddi) sep \
431 	func(has_fpga_dbg)
432 
433 #define DEFINE_FLAG(name) u8 name:1
434 #define SEP_SEMICOLON ;
435 
436 struct intel_device_info {
437 	u32 display_mmio_offset;
438 	u8 num_pipes:3;
439 	u8 gen;
440 	DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
441 };
442 
443 #undef DEFINE_FLAG
444 #undef SEP_SEMICOLON
445 
446 enum i915_cache_level {
447 	I915_CACHE_NONE = 0,
448 	I915_CACHE_LLC,
449 	I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
450 };
451 
452 typedef uint32_t gen6_gtt_pte_t;
453 
454 /* The Graphics Translation Table is the way in which GEN hardware translates a
455  * Graphics Virtual Address into a Physical Address. In addition to the normal
456  * collateral associated with any va->pa translations GEN hardware also has a
457  * portion of the GTT which can be mapped by the CPU and remain both coherent
458  * and correct (in cases like swizzling). That region is referred to as GMADR in
459  * the spec.
460  */
461 struct i915_gtt {
462 	unsigned long start;		/* Start offset of used GTT */
463 	size_t total;			/* Total size GTT can map */
464 	size_t stolen_size;		/* Total size of stolen memory */
465 
466 	unsigned long mappable_end;	/* End offset that we can CPU map */
467 	drm_local_map_t gtt_mapping;
468 	unsigned long mappable_base;	/* PA of our GMADR */
469 
470 
471 	struct drm_gem_object *scratch_page;
472 
473 	caddr_t	virtual_gtt;
474 
475 	/* global gtt ops */
476 	int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
477 			  size_t *stolen);
478 	void (*gtt_remove)(struct drm_device *dev);
479 	void (*gtt_clear_range)(struct drm_device *dev,
480 				struct drm_i915_gem_object *obj,
481 				uint32_t type);
482 	void (*gtt_insert_entries)(struct drm_i915_gem_object *obj,
483 				   enum i915_cache_level cache_level);
484 	gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,
485 				     uint64_t addr,
486 				     enum i915_cache_level level);
487 };
488 #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
489 
490 #define I915_PPGTT_PD_ENTRIES 512
491 #define I915_PPGTT_PT_ENTRIES 1024
492 struct i915_hw_ppgtt {
493 	struct drm_device *dev;
494 	unsigned num_pd_entries;
495 	pfn_t *pt_pages;
496 	uint32_t pd_offset;
497 	ddi_dma_handle_t dma_hdl;
498 	ddi_acc_handle_t acc_hdl;
499 	caddr_t kaddr;
500 	size_t real_size;	/* real size of memory */
501 	uint64_t	scratch_page_paddr;
502 	/* pte functions, mirroring the interface of the global gtt. */
503 	void (*clear_range)(struct i915_hw_ppgtt *ppgtt,
504 			    unsigned int first_entry,
505 			    unsigned int num_entries);
506 	void (*insert_entries)(struct i915_hw_ppgtt *ppgtt,
507 				    unsigned first_entry, unsigned num_entries,
508 				    pfn_t *pages, enum i915_cache_level cache_level);
509 	gen6_gtt_pte_t (*pte_encode)(struct drm_device *dev,
510 				     uint64_t addr,
511 				     enum i915_cache_level level);
512 	int (*enable)(struct drm_device *dev);
513 	void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
514 };
515 
516 struct i915_ctx_hang_stats {
517 	/* This context had batch pending when hang was declared */
518 	unsigned batch_pending;
519 
520 	/* This context had batch active when hang was declared */
521 	unsigned batch_active;
522 };
523 
524 /* This must match up with the value previously used for execbuf2.rsvd1. */
525 #define DEFAULT_CONTEXT_ID 0
526 struct i915_hw_context {
527 	struct kref ref;
528 	int id;
529 	bool is_initialized;
530 	struct drm_i915_file_private *file_priv;
531 	struct intel_ring_buffer *ring;
532 	struct drm_i915_gem_object *obj;
533 	struct i915_ctx_hang_stats hang_stats;
534 };
535 
536 enum no_fbc_reason {
537 	FBC_NO_OUTPUT, /* no outputs enabled to compress */
538 	FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
539 	FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
540 	FBC_MODE_TOO_LARGE, /* mode too large for compression */
541 	FBC_BAD_PLANE, /* fbc not supported on plane */
542 	FBC_NOT_TILED, /* buffer not tiled */
543 	FBC_MULTIPLE_PIPES, /* more than one pipe active */
544 	FBC_MODULE_PARAM,
545 };
546 
547 enum intel_pch {
548 	PCH_NONE = 0,	/* No PCH present */
549 	PCH_IBX,	/* Ibexpeak PCH */
550 	PCH_CPT,	/* Cougarpoint PCH */
551 	PCH_LPT,	/* Lynxpoint PCH */
552 	PCH_NOP,
553 };
554 
555 enum intel_sbi_destination {
556 	SBI_ICLK,
557 	SBI_MPHY,
558 };
559 
560 #define QUIRK_PIPEA_FORCE (1<<0)
561 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
562 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
563 #define QUIRK_NO_PCH_PWM_ENABLE (1<<3)
564 
565 struct intel_fbdev;
566 struct intel_fbc_work;
567 
568 struct intel_gmbus {
569 	struct i2c_adapter adapter;
570 	bool force_bit;
571 	u32 reg0;
572 	u32 gpio_reg;
573 	struct drm_i915_private *dev_priv;
574 };
575 
576 typedef struct drm_i915_bridge_dev {
577 	ldi_ident_t ldi_id;
578 	ldi_handle_t bridge_dev_hdl;
579 } drm_i915_bridge_dev_t;
580 
581 struct i915_suspend_saved_registers {
582 	u8 saveLBB;
583 	u32 saveDSPACNTR;
584 	u32 saveDSPBCNTR;
585 	u32 saveDSPARB;
586 	u32 saveHWS;
587 	u32 savePIPEACONF;
588 	u32 savePIPEBCONF;
589 	u32 savePIPEASRC;
590 	u32 savePIPEBSRC;
591 	u32 saveFPA0;
592 	u32 saveFPA1;
593 	u32 saveDPLL_A;
594 	u32 saveDPLL_A_MD;
595 	u32 saveHTOTAL_A;
596 	u32 saveHBLANK_A;
597 	u32 saveHSYNC_A;
598 	u32 saveVTOTAL_A;
599 	u32 saveVBLANK_A;
600 	u32 saveVSYNC_A;
601 	u32 saveBCLRPAT_A;
602 	u32 saveTRANSACONF;
603 	u32 saveTRANS_HTOTAL_A;
604 	u32 saveTRANS_HBLANK_A;
605 	u32 saveTRANS_HSYNC_A;
606 	u32 saveTRANS_VTOTAL_A;
607 	u32 saveTRANS_VBLANK_A;
608 	u32 saveTRANS_VSYNC_A;
609 	u32 savePIPEASTAT;
610 	u32 saveDSPASTRIDE;
611 	u32 saveDSPASIZE;
612 	u32 saveDSPAPOS;
613 	u32 saveDSPAADDR;
614 	u32 saveDSPASURF;
615 	u32 saveDSPATILEOFF;
616 	u32 savePFIT_PGM_RATIOS;
617 	u32 saveBLC_HIST_CTL;
618 	u32 saveBLC_PWM_CTL;
619 	u32 saveBLC_PWM_CTL2;
620 	u32 saveBLC_CPU_PWM_CTL;
621 	u32 saveBLC_CPU_PWM_CTL2;
622 	u32 saveFPB0;
623 	u32 saveFPB1;
624 	u32 saveDPLL_B;
625 	u32 saveDPLL_B_MD;
626 	u32 saveHTOTAL_B;
627 	u32 saveHBLANK_B;
628 	u32 saveHSYNC_B;
629 	u32 saveVTOTAL_B;
630 	u32 saveVBLANK_B;
631 	u32 saveVSYNC_B;
632 	u32 saveBCLRPAT_B;
633 	u32 saveTRANSBCONF;
634 	u32 saveTRANS_HTOTAL_B;
635 	u32 saveTRANS_HBLANK_B;
636 	u32 saveTRANS_HSYNC_B;
637 	u32 saveTRANS_VTOTAL_B;
638 	u32 saveTRANS_VBLANK_B;
639 	u32 saveTRANS_VSYNC_B;
640 	u32 savePIPEBSTAT;
641 	u32 saveDSPBSTRIDE;
642 	u32 saveDSPBSIZE;
643 	u32 saveDSPBPOS;
644 	u32 saveDSPBADDR;
645 	u32 saveDSPBSURF;
646 	u32 saveDSPBTILEOFF;
647 	u32 saveVGA0;
648 	u32 saveVGA1;
649 	u32 saveVGA_PD;
650 	u32 saveVGACNTRL;
651 	u32 saveADPA;
652 	u32 saveLVDS;
653 	u32 savePP_ON_DELAYS;
654 	u32 savePP_OFF_DELAYS;
655 	u32 saveDVOA;
656 	u32 saveDVOB;
657 	u32 saveDVOC;
658 	u32 savePP_ON;
659 	u32 savePP_OFF;
660 	u32 savePP_CONTROL;
661 	u32 savePP_DIVISOR;
662 	u32 savePFIT_CONTROL;
663 	u32 save_palette_a[256];
664 	u32 save_palette_b[256];
665 	u32 saveDPFC_CB_BASE;
666 	u32 saveFBC_CFB_BASE;
667 	u32 saveFBC_LL_BASE;
668 	u32 saveFBC_CONTROL;
669 	u32 saveFBC_CONTROL2;
670 	u32 saveIER;
671 	u32 saveIIR;
672 	u32 saveIMR;
673 	u32 saveDEIER;
674 	u32 saveDEIMR;
675 	u32 saveGTIER;
676 	u32 saveGTIMR;
677 	u32 saveFDI_RXA_IMR;
678 	u32 saveFDI_RXB_IMR;
679 	u32 saveCACHE_MODE_0;
680 	u32 saveMI_ARB_STATE;
681 	u32 saveSWF0[16];
682 	u32 saveSWF1[16];
683 	u32 saveSWF2[3];
684 	u8 saveMSR;
685 	u8 saveSR[8];
686 	u8 saveGR[25];
687 	u8 saveAR_INDEX;
688 	u8 saveAR[21];
689 	u8 saveDACMASK;
690 	u8 saveCR[37];
691 	uint64_t saveFENCE[I915_MAX_NUM_FENCES];
692 	u32 saveCURACNTR;
693 	u32 saveCURAPOS;
694 	u32 saveCURABASE;
695 	u32 saveCURBCNTR;
696 	u32 saveCURBPOS;
697 	u32 saveCURBBASE;
698 	u32 saveCURSIZE;
699 	u32 saveDP_B;
700 	u32 saveDP_C;
701 	u32 saveDP_D;
702 	u32 savePIPEA_GMCH_DATA_M;
703 	u32 savePIPEB_GMCH_DATA_M;
704 	u32 savePIPEA_GMCH_DATA_N;
705 	u32 savePIPEB_GMCH_DATA_N;
706 	u32 savePIPEA_DP_LINK_M;
707 	u32 savePIPEB_DP_LINK_M;
708 	u32 savePIPEA_DP_LINK_N;
709 	u32 savePIPEB_DP_LINK_N;
710 	u32 saveFDI_RXA_CTL;
711 	u32 saveFDI_TXA_CTL;
712 	u32 saveFDI_RXB_CTL;
713 	u32 saveFDI_TXB_CTL;
714 	u32 savePFA_CTL_1;
715 	u32 savePFB_CTL_1;
716 	u32 savePFA_WIN_SZ;
717 	u32 savePFB_WIN_SZ;
718 	u32 savePFA_WIN_POS;
719 	u32 savePFB_WIN_POS;
720 	u32 savePCH_DREF_CONTROL;
721 	u32 saveDISP_ARB_CTL;
722 	u32 savePIPEA_DATA_M1;
723 	u32 savePIPEA_DATA_N1;
724 	u32 savePIPEA_LINK_M1;
725 	u32 savePIPEA_LINK_N1;
726 	u32 savePIPEB_DATA_M1;
727 	u32 savePIPEB_DATA_N1;
728 	u32 savePIPEB_LINK_M1;
729 	u32 savePIPEB_LINK_N1;
730 	u32 saveMCHBAR_RENDER_STANDBY;
731 	u32 savePCH_PORT_HOTPLUG;
732 	u32 pgtbl_ctl;
733 };
734 
735 
736 struct batch_info_list {
737 	struct list_head head;
738 	uint32_t num;
739 	uint32_t seqno;
740 	caddr_t *obj_list;
741 };
742 
743 struct intel_gen6_power_mgmt {
744 	struct work_struct work;
745 	struct work_struct vlv_work;
746 	struct timer_list vlv_timer;
747 	u32 pm_iir;
748 	/* lock - irqsave spinlock that protectects the work_struct and
749 	 * pm_iir. */
750 	spinlock_t lock;
751 
752 	/* The below variables an all the rps hw state are protected by
753 	 * dev->struct mutext. */
754 	u8 cur_delay;
755 	u8 min_delay;
756 	u8 max_delay;
757 	u8 rpe_delay;
758 	u8 hw_max;
759 
760 	struct work_struct delayed_resume_work;
761 	struct timer_list delayed_resume_timer;
762 
763 	/*
764 	 * Protects RPS/RC6 register access and PCU communication.
765 	 * Must be taken after struct_mutex if nested.
766 	 */
767 	struct mutex hw_lock;
768 };
769 
770 /* defined intel_pm.c */
771 extern spinlock_t mchdev_lock;
772 
773 struct intel_ilk_power_mgmt {
774 	u8 cur_delay;
775 	u8 min_delay;
776 	u8 max_delay;
777 	u8 fmax;
778 	u8 fstart;
779 
780 	u64 last_count1;
781 	unsigned long last_time1;
782 	unsigned long chipset_power;
783 	u64 last_count2;
784 	clock_t	last_time2;
785 	unsigned long gfx_power;
786 	u8 corr;
787 
788 	int c_m;
789 	int r_t;
790 
791 	struct drm_i915_gem_object *pwrctx;
792 	struct drm_i915_gem_object *renderctx;
793 };
794 
795 /* Power well structure for haswell */
796 struct i915_power_well {
797 	struct drm_device *device;
798 	spinlock_t lock;
799 	/* power well enable/disable usage count */
800 	int count;
801 	int i915_request;
802 };
803 
804 struct i915_dri1_state {
805 	unsigned allow_batchbuffer : 1;
806 	drm_local_map_t	gfx_hws_cpu_addr;
807 
808 	unsigned int cpp;
809 	int back_offset;
810 	int front_offset;
811 	int current_page;
812 	int page_flipping;
813 
814 	uint32_t counter;
815 };
816 
817 struct intel_l3_parity {
818 	u32 *remap_info;
819 	struct work_struct error_work;
820 };
821 
822 struct i915_gem_mm {
823 	/** Memory allocator for GTT stolen memory */
824 	struct drm_mm stolen;
825 	/** Memory allocator for GTT */
826 	struct drm_mm gtt_space;
827 	/** List of all objects in gtt_space. Used to restore gtt
828 	 * mappings on resume */
829 	struct list_head bound_list;
830 	/**
831 	 * List of objects which are not bound to the GTT (thus
832 	 * are idle and not used by the GPU) but still have
833 	 * (presumably uncached) pages still attached.
834 	 */
835 	struct list_head unbound_list;
836 
837 	/** Usable portion of the GTT for GEM */
838 	unsigned long stolen_base; /* limited to low memory (32-bit) */
839 
840 	int gtt_mtrr;
841 
842 	/** PPGTT used for aliasing the PPGTT with the GTT */
843 	struct i915_hw_ppgtt *aliasing_ppgtt;
844 
845 	/**
846 	 * List of objects currently involved in rendering.
847 	 *
848 	 * Includes buffers having the contents of their GPU caches
849 	 * flushed, not necessarily primitives.  last_rendering_seqno
850 	 * represents when the rendering involved will be completed.
851 	 *
852 	 * A reference is held on the buffer while on this list.
853 	 */
854 	struct list_head active_list;
855 
856 	/**
857 	 * LRU list of objects which are not in the ringbuffer and
858 	 * are ready to unbind, but are still in the GTT.
859 	 *
860 	 * last_rendering_seqno is 0 while an object is in this list.
861 	 *
862 	 * A reference is not held on the buffer while on this list,
863 	 * as merely being GTT-bound shouldn't prevent its being
864 	 * freed, and we'll pull it off the list in the free path.
865 	 */
866 	struct list_head inactive_list;
867 
868 	/** LRU list of objects with fence regs on them. */
869 	struct list_head fence_list;
870 
871 	/**
872 	 * We leave the user IRQ off as much as possible,
873 	 * but this means that requests will finish and never
874 	 * be retired once the system goes idle. Set a timer to
875 	 * fire periodically while the ring is running. When it
876 	 * fires, go retire requests.
877 	 */
878 	struct work_struct retire_work;
879 	struct timer_list retire_timer;
880 
881 	/**
882 	 * Are we in a non-interruptible section of code like
883 	 * modesetting?
884 	 */
885 	bool interruptible;
886 
887 	/**
888 	 * Flag if the X Server, and thus DRM, is not currently in
889 	 * control of the device.
890 	 *
891 	 * This is set between LeaveVT and EnterVT.  It needs to be
892 	 * replaced with a semaphore.  It also needs to be
893 	 * transitioned away from for kernel modesetting.
894 	 */
895 	int suspended;
896 
897 	/** Bit 6 swizzling required for X tiling */
898 	uint32_t bit_6_swizzle_x;
899 	/** Bit 6 swizzling required for Y tiling */
900 	uint32_t bit_6_swizzle_y;
901 
902 	/* storage for physical objects */
903 	struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
904 
905 	/* accounting, useful for userland debugging */
906 	size_t object_memory;
907 	u32 object_count;
908 };
909 
910 struct drm_i915_error_state_buf {
911 	unsigned bytes;
912 	unsigned size;
913 	int err;
914 	u8 *buf;
915 	uint64_t start;
916 	uint64_t pos;
917 };
918 
919 struct i915_gpu_error {
920 	/* For hangcheck timer */
921 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
922 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
923 	struct timer_list hangcheck_timer;
924 
925 	/* For reset and error_state handling. */
926 	spinlock_t lock;
927 	/* Protected by the above dev->gpu_error.lock. */
928 	struct drm_i915_error_state *first_error;
929 	struct work_struct work;
930 
931 	unsigned long last_reset;
932 
933 	/**
934 	 * State variable and reset counter controlling the reset flow
935 	 *
936 	 * Upper bits are for the reset counter.  This counter is used by the
937 	 * wait_seqno code to race-free noticed that a reset event happened and
938 	 * that it needs to restart the entire ioctl (since most likely the
939 	 * seqno it waited for won't ever signal anytime soon).
940 	 *
941 	 * This is important for lock-free wait paths, where no contended lock
942 	 * naturally enforces the correct ordering between the bail-out of the
943 	 * waiter and the gpu reset work code.
944 	 *
945 	 * Lowest bit controls the reset state machine: Set means a reset is in
946 	 * progress. This state will (presuming we don't have any bugs) decay
947 	 * into either unset (successful reset) or the special WEDGED value (hw
948 	 * terminally sour). All waiters on the reset_queue will be woken when
949 	 * that happens.
950 	 */
951 	atomic_t reset_counter;
952 
953 	/**
954 	 * Special values/flags for reset_counter
955 	 *
956 	 * Note that the code relies on
957 	 * 	I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
958 	 * being true.
959 	 */
960 #define I915_RESET_IN_PROGRESS_FLAG	1
961 #define I915_WEDGED			0xffffffff
962 
963 	/**
964 	 * Waitqueue to signal when the reset has completed. Used by clients
965 	 * that wait for dev_priv->mm.wedged to settle.
966 	 */
967 	wait_queue_head_t reset_queue;
968 
969 	/* For gpu hang simulation. */
970 	unsigned int stop_rings;
971 };
972 
973 enum modeset_restore {
974 	MODESET_ON_LID_OPEN,
975 	MODESET_DONE,
976 	MODESET_SUSPENDED,
977 };
978 
979 struct intel_vbt_data {
980 	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
981 	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
982 
983 	/* Feature bits */
984 	unsigned int int_tv_support:1;
985 	unsigned int lvds_dither:1;
986 	unsigned int lvds_vbt:1;
987 	unsigned int int_crt_support:1;
988 	unsigned int lvds_use_ssc:1;
989 	unsigned int display_clock_mode:1;
990 	unsigned int fdi_rx_polarity_inverted:1;
991 	int lvds_ssc_freq;
992 	unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
993 
994 	/* eDP */
995 	int edp_rate;
996 	int edp_lanes;
997 	int edp_preemphasis;
998 	int edp_vswing;
999 	bool edp_initialized;
1000 	bool edp_support;
1001 	int edp_bpp;
1002 	struct edp_power_seq edp_pps;
1003 
1004 	int crt_ddc_pin;
1005 
1006 	int child_dev_num;
1007 	struct child_device_config *child_dev;
1008 };
1009 
1010 typedef struct drm_i915_private {
1011 	struct drm_device *dev;
1012 
1013 	const struct intel_device_info *info;
1014 
1015 	int relative_constants_mode;
1016 
1017 	drm_local_map_t *regs;
1018 	struct drm_i915_gt_funcs gt;
1019 	/** gt_fifo_count and the subsequent register write are synchronized
1020 	 * with dev->struct_mutex. */
1021 	unsigned gt_fifo_count;
1022 	/** forcewake_count is protected by gt_lock */
1023 	unsigned forcewake_count;
1024 	/** gt_lock is also taken in irq contexts. */
1025 	spinlock_t gt_lock;
1026 
1027 	struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1028 
1029 	/** gmbus_mutex protects against concurrent usage of the single hw gmbus
1030 	 * controller on different i2c buses. */
1031 	struct mutex gmbus_mutex;
1032 
1033 	/**
1034 	 * Base address of the gmbus and gpio block.
1035 	 */
1036 	uint32_t gpio_mmio_base;
1037 
1038 	wait_queue_head_t gmbus_wait_queue;
1039 
1040 	struct drm_i915_bridge_dev bridge_dev;
1041 	struct intel_ring_buffer ring[I915_NUM_RINGS];
1042 	uint32_t last_seqno, next_seqno;
1043 
1044 	drm_dma_handle_t *status_page_dmah;
1045 	uint32_t counter;
1046 
1047 	atomic_t irq_received;
1048 	u32 trace_irq_seqno;
1049 
1050 	/* protects the irq masks */
1051 	spinlock_t irq_lock;
1052 
1053 	/* DPIO indirect register protection */
1054 	spinlock_t dpio_lock;
1055 
1056 	/** Cached value of IMR to avoid reads in updating the bitfield */
1057 	u32 irq_mask;
1058 	u32 gt_irq_mask;
1059 
1060 	struct work_struct hotplug_work;
1061 	bool enable_hotplug_processing;
1062 	struct {
1063 		unsigned long hpd_last_jiffies;
1064 		int hpd_cnt;
1065 		enum {
1066 			HPD_ENABLED = 0,
1067 			HPD_DISABLED = 1,
1068 			HPD_MARK_DISABLED = 2
1069 		} hpd_mark;
1070 	} hpd_stats[HPD_NUM_PINS];
1071 	u32 hpd_event_bits;
1072 	struct timer_list hotplug_reenable_timer;
1073 
1074 	int num_plane;
1075 
1076 	unsigned long cfb_size;
1077 	unsigned int cfb_fb;
1078 	enum plane cfb_plane;
1079 	int cfb_y;
1080 	struct intel_fbc_work *fbc_work;
1081 	struct timer_list fbc_timer;
1082 
1083 	struct intel_opregion opregion;
1084 	struct intel_vbt_data vbt;
1085 
1086 	/* overlay */
1087 	struct intel_overlay *overlay;
1088 	unsigned int sprite_scaling_enabled;
1089 
1090 	/* backlight */
1091 	struct {
1092 		int level;
1093 		bool enabled;
1094 		spinlock_t lock; /* bl registers and the above bl fields */
1095 		struct backlight_device *device;
1096 	} backlight;
1097 
1098 	/* LVDS info */
1099 	struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1100 	struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1101 	bool no_aux_handshake;
1102 
1103 	struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1104 	int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1105 	int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1106 
1107 	unsigned int fsb_freq, mem_freq, is_ddr3;
1108 
1109 	struct workqueue_struct *wq;
1110 	struct workqueue_struct *other_wq;
1111 
1112 	/* Display functions */
1113 	struct drm_i915_display_funcs display;
1114 
1115 	/* PCH chipset type */
1116 	enum intel_pch pch_type;
1117 	unsigned short pch_id;
1118 
1119 	unsigned long quirks;
1120 	bool vt_holding;
1121 	bool isX;
1122 	bool gfx_state_saved;
1123 
1124 	/* Register state */
1125 	enum modeset_restore modeset_restore;
1126 	struct mutex modeset_restore_lock;
1127 
1128 	struct i915_gtt gtt;
1129 
1130 	struct i915_gem_mm mm;
1131 
1132 	/* Kernel Modesetting */
1133 
1134 	struct sdvo_device_mapping sdvo_mappings[2];
1135 
1136 	struct drm_crtc *plane_to_crtc_mapping[3];
1137 	struct drm_crtc *pipe_to_crtc_mapping[3];
1138 	wait_queue_head_t pending_flip_queue;
1139 
1140 	int num_shared_dpll;
1141 	struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1142 	struct intel_ddi_plls ddi_plls;
1143 
1144 	/* Reclocking support */
1145 	bool render_reclock_avail;
1146 	bool lvds_downclock_avail;
1147 	/* indicates the reduced downclock for LVDS*/
1148 	int lvds_downclock;
1149 	u16 orig_clock;
1150 
1151 	bool mchbar_need_disable;
1152 
1153 	struct intel_l3_parity l3_parity;
1154 
1155 	/* gen6+ rps state */
1156 	struct intel_gen6_power_mgmt rps;
1157 
1158 	/* ilk-only ips/rps state. Everything in here is protected by the global
1159 	 * mchdev_lock in intel_pm.c */
1160 	struct intel_ilk_power_mgmt ips;
1161 
1162 	/* Haswell power well */
1163 	struct i915_power_well power_well;
1164 
1165 	enum no_fbc_reason no_fbc_reason;
1166 
1167 	struct drm_mm_node *compressed_fb;
1168 	struct drm_mm_node *compressed_llb;
1169 
1170 	struct timer_list gpu_top_timer;
1171 	struct i915_gpu_error gpu_error;
1172 	int gpu_hang;
1173 	struct drm_i915_gem_object *vlv_pctx;
1174 
1175 	/* list of fbdev register on this device */
1176 	struct intel_fbdev *fbdev;
1177 
1178 
1179 	struct drm_property *broadcast_rgb_property;
1180 	struct drm_property *force_audio_property;
1181 
1182 	bool hw_contexts_disabled;
1183 	uint32_t hw_context_size;
1184 
1185 	u32 fdi_rx_config;
1186 
1187 	struct i915_suspend_saved_registers regfile;
1188 
1189 	struct drm_i915_gem_object *fbcon_obj;
1190 
1191 	/* Old dri1 support infrastructure, beware the dragons ya fools entering
1192 	 * here! */
1193 	struct i915_dri1_state dri1;
1194 	struct list_head batch_list;
1195 } drm_i915_private_t;
1196 
1197 /* Iterate over initialised rings */
1198 #define for_each_ring(ring__, dev_priv__, i__) \
1199 	for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1200 		if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1201 
1202 enum hdmi_force_audio {
1203 	HDMI_AUDIO_OFF_DVI = -2,	/* no aux data for HDMI-DVI converter */
1204 	HDMI_AUDIO_OFF,			/* force turn off HDMI audio */
1205 	HDMI_AUDIO_AUTO,		/* trust EDID */
1206 	HDMI_AUDIO_ON,			/* force turn on HDMI audio */
1207 };
1208 
1209 #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
1210 
1211 struct drm_i915_gem_object_ops {
1212 	/* Interface between the GEM object and its backing storage.
1213 	 * get_pages() is called once prior to the use of the associated set
1214 	 * of pages before to binding them into the GTT, and put_pages() is
1215 	 * called after we no longer need them. As we expect there to be
1216 	 * associated cost with migrating pages between the backing storage
1217 	 * and making them available for the GPU (e.g. clflush), we may hold
1218 	 * onto the pages after they are no longer referenced by the GPU
1219 	 * in case they may be used again shortly (for example migrating the
1220 	 * pages to a different memory domain within the GTT). put_pages()
1221 	 * will therefore most likely be called when the object itself is
1222 	 * being released or under memory pressure (where we attempt to
1223 	 * reap pages for the shrinker).
1224 	 */
1225 	int (*get_pages)(struct drm_i915_gem_object *);
1226 	void (*put_pages)(struct drm_i915_gem_object *);
1227 };
1228 
1229 struct drm_i915_gem_object {
1230 	struct drm_gem_object base;
1231 
1232 	const struct drm_i915_gem_object_ops *ops;
1233 
1234 	/** Current space allocated to this object in the GTT, if any. */
1235 	struct drm_mm_node *gtt_space;
1236 	/** Stolen memory for this object, instead of being backed by shmem. */
1237 	struct drm_mm_node *stolen;
1238 	struct list_head global_list;
1239 
1240 	/** This object's place on the active/flushing/inactive lists */
1241 	struct list_head ring_list;
1242 	struct list_head mm_list;
1243 	/** This object's place on eviction list */
1244 	struct list_head exec_list;
1245 
1246 	/**
1247 	 * This is set if the object is on the active or flushing lists
1248 	 * (has pending rendering), and is not set if it's on inactive (ready
1249 	 * to be unbound).
1250 	 */
1251 	unsigned int active;
1252 
1253 	/**
1254 	 * This is set if the object has been written to since last bound
1255 	 * to the GTT
1256 	 */
1257 	unsigned int dirty;
1258 
1259 	/**
1260 	 * Fence register bits (if any) for this object.  Will be set
1261 	 * as needed when mapped into the GTT.
1262 	 * Protected by dev->struct_mutex.
1263 	 */
1264 	signed int fence_reg;
1265 
1266 	/**
1267 	 * Advice: are the backing pages purgeable?
1268 	 */
1269 	unsigned int madv;
1270 
1271 	/**
1272 	 * Current tiling mode for the object.
1273 	 */
1274 	unsigned int tiling_mode : 2;
1275 	/**
1276 	 * Whether the tiling parameters for the currently associated fence
1277 	 * register have changed. Note that for the purposes of tracking
1278 	 * tiling changes we also treat the unfenced register, the register
1279 	 * slot that the object occupies whilst it executes a fenced
1280 	 * command (such as BLT on gen2/3), as a "fence".
1281 	 */
1282 	unsigned int fence_dirty:1;
1283 
1284 	/** How many users have pinned this object in GTT space. The following
1285 	 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1286 	 * (via user_pin_count), execbuffer (objects are not allowed multiple
1287 	 * times for the same batchbuffer), and the framebuffer code. When
1288 	 * switching/pageflipping, the framebuffer code has at most two buffers
1289 	 * pinned per crtc.
1290 	 *
1291 	 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1292 	 * bits with absolutely no headroom. So use 4 bits. */
1293 	unsigned int pin_count;
1294 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1295 
1296 	/**
1297 	 * Is the object at the current location in the gtt mappable and
1298 	 * fenceable? Used to avoid costly recalculations.
1299 	 */
1300 	unsigned int map_and_fenceable;
1301 	int	agp_mem;
1302 	/**
1303 	 * Whether the current gtt mapping needs to be mappable (and isn't just
1304 	 * mappable by accident). Track pin and fault separate for a more
1305 	 * accurate mappable working set.
1306 	 */
1307 	unsigned int fault_mappable;
1308 	unsigned int pin_mappable;
1309 
1310 	/*
1311 	 * Is the GPU currently using a fence to access this buffer,
1312 	 */
1313 	unsigned int pending_fenced_gpu_access;
1314 	unsigned int fenced_gpu_access;
1315 
1316 	unsigned int cache_level;
1317 
1318 	unsigned int has_aliasing_ppgtt_mapping;
1319 	unsigned int has_global_gtt_mapping;
1320 	unsigned int has_dma_mapping;
1321 
1322 	caddr_t *page_list;
1323 	int pages_pin_count;
1324 
1325 	/**
1326 	 * DMAR support
1327 	 */
1328 	struct scatterlist *sg_list;
1329 	int num_sg;
1330 
1331 	/**
1332 	 * Used for performing relocations during execbuffer insertion.
1333 	 */
1334 	unsigned long exec_handle;
1335 	struct drm_i915_gem_exec_object2 *exec_entry;
1336 
1337 	/**
1338 	 * Current offset of the object in GTT space.
1339 	 *
1340 	 * This is the same as gtt_space->start
1341 	 */
1342 	uint32_t gtt_offset;
1343 
1344 	struct intel_ring_buffer *ring;
1345 
1346 	/**
1347 	 * Fake offset for use by mmap(2)
1348 	 */
1349 	uint64_t mmap_offset;
1350 
1351 	/** Breadcrumb of last rendering to the buffer. */
1352 	uint32_t last_read_seqno;
1353 	uint32_t last_write_seqno;
1354 	/** Breadcrumb of last fenced GPU access to the buffer. */
1355 	uint32_t last_fenced_seqno;
1356 
1357 	/** Current tiling mode for the object. */
1358 	uint32_t stride;
1359 
1360 	/** Record of address bit 17 of each page at last unbind. */
1361 	unsigned long *bit_17;
1362 
1363 	/** User space pin count and filp owning the pin */
1364 	uint32_t user_pin_count;
1365 	struct drm_file *pin_filp;
1366 
1367 	/** for phy allocated objects */
1368 	struct drm_i915_gem_phys_object *phys_obj;
1369 
1370 	/** OSOL: for cursor objects */
1371 	u8 is_cursor;
1372 };
1373 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1374 
1375 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1376 
1377 /**
1378  * Request queue structure.
1379  *
1380  * The request queue allows us to note sequence numbers that have been emitted
1381  * and may be associated with active buffers to be retired.
1382  *
1383  * By keeping this list, we can avoid having to do questionable
1384  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1385  * an emission time with seqnos for tracking how far ahead of the GPU we are.
1386  */
1387 struct drm_i915_gem_request {
1388 	/** On Which ring this request was generated */
1389 	struct intel_ring_buffer *ring;
1390 
1391 	/** GEM sequence number associated with this request. */
1392 	uint32_t seqno;
1393 
1394 	/** Position in the ringbuffer of the start of the request */
1395 	u32 head;
1396 
1397 	/** Postion in the ringbuffer of the end of the request */
1398 	u32 tail;
1399 
1400 	/** Context related to this request */
1401 	struct i915_hw_context *ctx;
1402 
1403 	/** Batch buffer related to this request if any */
1404 	struct drm_i915_gem_object *batch_obj;
1405 
1406 	/** Time at which this request was emitted, in jiffies. */
1407 	unsigned long emitted_jiffies;
1408 
1409 	/** global list entry for this request */
1410 	struct list_head list;
1411 
1412 	struct drm_i915_file_private *file_priv;
1413 	/** file_priv list entry for this request */
1414 	struct list_head client_list;
1415 };
1416 
1417 struct drm_i915_file_private {
1418 	struct {
1419 		spinlock_t lock;
1420 		struct list_head request_list;
1421 	} mm;
1422 	/** 1 open, 0 close*/
1423 	int status;
1424 	struct idr context_idr;
1425 
1426 	struct i915_ctx_hang_stats hang_stats;
1427 };
1428 
1429 #if defined(__sun)
1430 /* These definitions conflict with those in x86_archext.h */
1431 #undef IS_IVYBRIDGE
1432 #undef IS_HASWELL
1433 #endif
1434 
1435 #define INTEL_INFO(dev)	(((struct drm_i915_private *) (dev)->dev_private)->info)
1436 
1437 #define IS_I830(dev)		((dev)->pci_device == 0x3577)
1438 #define IS_845G(dev)		((dev)->pci_device == 0x2562)
1439 #define IS_I85X(dev)		(INTEL_INFO(dev)->is_i85x)
1440 #define IS_I865G(dev)		((dev)->pci_device == 0x2572)
1441 #define IS_I915G(dev)		(INTEL_INFO(dev)->is_i915g)
1442 #define IS_I915GM(dev)		((dev)->pci_device == 0x2592)
1443 #define IS_I945G(dev)		((dev)->pci_device == 0x2772)
1444 #define IS_I945GM(dev)		(INTEL_INFO(dev)->is_i945gm)
1445 #define IS_BROADWATER(dev)	(INTEL_INFO(dev)->is_broadwater)
1446 #define IS_CRESTLINE(dev)	(INTEL_INFO(dev)->is_crestline)
1447 #define IS_GM45(dev)		((dev)->pci_device == 0x2A42)
1448 #define IS_G4X(dev)		(INTEL_INFO(dev)->is_g4x)
1449 #define IS_PINEVIEW_G(dev)	((dev)->pci_device == 0xa001)
1450 #define IS_PINEVIEW_M(dev)	((dev)->pci_device == 0xa011)
1451 #define IS_PINEVIEW(dev)	(INTEL_INFO(dev)->is_pineview)
1452 #define IS_G33(dev)		(INTEL_INFO(dev)->is_g33)
1453 #define IS_IRONLAKE_D(dev)	((dev)->pci_device == 0x0042)
1454 #define IS_IRONLAKE_M(dev)	((dev)->pci_device == 0x0046)
1455 #define	IS_IVYBRIDGE(dev)	(INTEL_INFO(dev)->is_ivybridge)
1456 #define IS_IVB_GT1(dev)		((dev)->pci_device == 0x0156 || \
1457 				 (dev)->pci_device == 0x0152 ||	\
1458 				 (dev)->pci_device == 0x015a)
1459 #define IS_SNB_GT1(dev)		((dev)->pci_device == 0x0102 || \
1460 				 (dev)->pci_device == 0x0106 ||	\
1461 				 (dev)->pci_device == 0x010A)
1462 #define IS_VALLEYVIEW(dev)	(INTEL_INFO(dev)->is_valleyview)
1463 #define IS_HASWELL(dev)	(INTEL_INFO(dev)->is_haswell)
1464 #define IS_MOBILE(dev)		(INTEL_INFO(dev)->is_mobile)
1465 #define IS_ULT(dev)		(IS_HASWELL(dev) && \
1466 				 ((dev)->pci_device & 0xFF00) == 0x0A00)
1467 
1468 /*
1469  * The genX designation typically refers to the render engine, so render
1470  * capability related checks should use IS_GEN, while display and other checks
1471  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1472  * chips, etc.).
1473  */
1474 #define IS_GEN2(dev)	(INTEL_INFO(dev)->gen == 2)
1475 #define IS_GEN3(dev)	(INTEL_INFO(dev)->gen == 3)
1476 #define IS_GEN4(dev)	(INTEL_INFO(dev)->gen == 4)
1477 #define IS_GEN5(dev)	(INTEL_INFO(dev)->gen == 5)
1478 #define IS_GEN6(dev)	(INTEL_INFO(dev)->gen == 6)
1479 #define IS_GEN7(dev)	(INTEL_INFO(dev)->gen == 7)
1480 
1481 #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
1482 #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
1483 #define HAS_VEBOX(dev)          (INTEL_INFO(dev)->has_vebox_ring)
1484 #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
1485 #define I915_NEED_GFX_HWS(dev)	(INTEL_INFO(dev)->need_gfx_hws)
1486 
1487 #define HAS_HW_CONTEXTS(dev)	(INTEL_INFO(dev)->gen >= 6)
1488 #define HAS_ALIASING_PPGTT(dev)	(INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1489 
1490 #define HAS_OVERLAY(dev) 		(INTEL_INFO(dev)->has_overlay)
1491 #define OVERLAY_NEEDS_PHYSICAL(dev)	(INTEL_INFO(dev)->overlay_needs_physical)
1492 
1493 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1494 #define HAS_BROKEN_CS_TLB(dev)		(IS_I830(dev) || IS_845G(dev))
1495 
1496 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1497  * rows, which changed the alignment requirements and fence programming.
1498  */
1499 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1500 								  IS_I915GM(dev)))
1501 #define SUPPORTS_DIGITAL_OUTPUTS(dev)	(!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1502 #define SUPPORTS_INTEGRATED_HDMI(dev)	(IS_G4X(dev) || IS_GEN5(dev))
1503 #define SUPPORTS_INTEGRATED_DP(dev)	(IS_G4X(dev) || IS_GEN5(dev))
1504 #define SUPPORTS_EDP(dev)		(IS_IRONLAKE_M(dev))
1505 #define SUPPORTS_TV(dev)		(INTEL_INFO(dev)->supports_tv)
1506 #define I915_HAS_HOTPLUG(dev)		 (INTEL_INFO(dev)->has_hotplug)
1507 /* dsparb controlled by hw only */
1508 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1509 
1510 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1511 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1512 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1513 
1514 #define HAS_IPS(dev)		(IS_ULT(dev))
1515 
1516 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1517 
1518 #define HAS_DDI(dev)		(INTEL_INFO(dev)->has_ddi)
1519 #define HAS_POWER_WELL(dev)	(IS_HASWELL(dev))
1520 #define HAS_FPGA_DBG_UNCLAIMED(dev)	(INTEL_INFO(dev)->has_fpga_dbg)
1521 
1522 #define INTEL_PCH_DEVICE_ID_MASK		0xff00
1523 #define INTEL_PCH_IBX_DEVICE_ID_TYPE		0x3b00
1524 #define INTEL_PCH_CPT_DEVICE_ID_TYPE		0x1c00
1525 #define INTEL_PCH_PPT_DEVICE_ID_TYPE		0x1e00
1526 #define INTEL_PCH_LPT_DEVICE_ID_TYPE		0x8c00
1527 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE		0x9c00
1528 
1529 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1530 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1531 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1532 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1533 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1534 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1535 
1536 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1537 
1538 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1539 
1540 #define GT_FREQUENCY_MULTIPLIER 50
1541 
1542 
1543 /**
1544  * RC6 is a special power stage which allows the GPU to enter an very
1545  * low-voltage mode when idle, using down to 0V while at this stage.  This
1546  * stage is entered automatically when the GPU is idle when RC6 support is
1547  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1548  *
1549  * There are different RC6 modes available in Intel GPU, which differentiate
1550  * among each other with the latency required to enter and leave RC6 and
1551  * voltage consumed by the GPU in different states.
1552  *
1553  * The combination of the following flags define which states GPU is allowed
1554  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1555  * RC6pp is deepest RC6. Their support by hardware varies according to the
1556  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1557  * which brings the most power savings; deeper states save more power, but
1558  * require higher latency to switch to and wake up.
1559  */
1560 #define INTEL_RC6_ENABLE			(1<<0)
1561 #define INTEL_RC6p_ENABLE			(1<<1)
1562 #define INTEL_RC6pp_ENABLE			(1<<2)
1563 
1564 extern struct drm_ioctl_desc i915_ioctls[];
1565 extern int i915_max_ioctl;
1566 extern unsigned int i915_fbpercrtc;
1567 extern int i915_panel_ignore_lid;
1568 extern unsigned int i915_powersave;
1569 extern int i915_semaphores;
1570 extern unsigned int i915_lvds_downclock;
1571 extern int i915_lvds_channel_mode;
1572 extern int i915_panel_use_ssc;
1573 extern int i915_vbt_sdvo_panel_type;
1574 extern int i915_enable_rc6;
1575 extern int i915_enable_fbc;
1576 extern bool i915_enable_hangcheck;
1577 extern bool i915_try_reset;
1578 extern int i915_enable_ppgtt;
1579 extern int i915_disable_power_well;
1580 extern int i915_enable_ips;
1581 
1582 extern int i915_suspend(struct drm_device *dev);
1583 extern int i915_resume(struct drm_device *dev);
1584 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1585 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1586 extern void i915_driver_entervt(struct drm_device *dev);
1587 extern void i915_driver_leavevt(struct drm_device *dev);
1588 extern void i915_driver_agp_support_detect(struct drm_device *dev, unsigned long flags);
1589 
1590 /* i915_dma.c */
1591 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1592 extern void i915_kernel_lost_context(struct drm_device * dev);
1593 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1594 extern int i915_driver_unload(struct drm_device *);
1595 extern int i915_driver_firstopen(struct drm_device *dev);
1596 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1597 extern void i915_driver_lastclose(struct drm_device * dev);
1598 extern void i915_driver_preclose(struct drm_device *dev,
1599 				 struct drm_file *file_priv);
1600 extern void i915_driver_postclose(struct drm_device *dev,
1601 				  struct drm_file *file_priv);
1602 extern int i915_driver_device_is_agp(struct drm_device * dev);
1603 #ifdef CONFIG_COMPAT
1604 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1605 			      unsigned long arg);
1606 #endif
1607 extern int i915_emit_box(struct drm_device *dev,
1608 			 struct drm_clip_rect *box,
1609 			 int DR1, int DR4);
1610 extern int intel_gpu_reset(struct drm_device *dev);
1611 extern int i915_reset(struct drm_device *dev);
1612 
1613 extern void intel_console_resume(struct work_struct *work);
1614 
1615 extern void i915_emit_mi_flush(drm_device_t *dev, uint32_t flush);
1616 extern int i915_bridge_dev_read_config_word(struct drm_i915_bridge_dev *bridge_dev, int where, u16 *val);
1617 extern int i915_bridge_dev_write_config_word(struct drm_i915_bridge_dev *bridge_dev, int where, u16 val);
1618 
1619 extern void gpu_top_handler(void *data);
1620 /* i915_irq.c */
1621 void i915_hangcheck_elapsed(void* data);
1622 void i915_handle_error(struct drm_device *dev, bool wedged);
1623 
1624 extern void intel_irq_init(struct drm_device *dev);
1625 extern void intel_pm_init(struct drm_device *dev);
1626 extern void intel_hpd_init(struct drm_device *dev);
1627 extern void intel_gt_init(struct drm_device *dev);
1628 extern void intel_gt_sanitize(struct drm_device *dev);
1629 
1630 void i915_error_state_free(struct kref *error_ref);
1631 
1632 void
1633 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1634 
1635 void
1636 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1637 
1638 #ifdef CONFIG_DEBUG_FS
1639 extern void i915_destroy_error_state(struct drm_device *dev);
1640 #else
1641 #define i915_destroy_error_state(x)
1642 #endif
1643 
1644 /* i915_gem.c */
1645 int i915_gem_init_ioctl(DRM_IOCTL_ARGS);
1646 int i915_gem_create_ioctl(DRM_IOCTL_ARGS);
1647 int i915_gem_pread_ioctl(DRM_IOCTL_ARGS);
1648 int i915_gem_pwrite_ioctl(DRM_IOCTL_ARGS);
1649 int i915_gem_mmap_ioctl(DRM_IOCTL_ARGS);
1650 int i915_gem_mmap_gtt_ioctl(DRM_IOCTL_ARGS);
1651 int i915_gem_set_domain_ioctl(DRM_IOCTL_ARGS);
1652 int i915_gem_sw_finish_ioctl(DRM_IOCTL_ARGS);
1653 int i915_gem_execbuffer(DRM_IOCTL_ARGS);
1654 int i915_gem_execbuffer2(DRM_IOCTL_ARGS);
1655 int i915_gem_pin_ioctl(DRM_IOCTL_ARGS);
1656 int i915_gem_unpin_ioctl(DRM_IOCTL_ARGS);
1657 int i915_gem_busy_ioctl(DRM_IOCTL_ARGS);
1658 int i915_gem_get_caching_ioctl(DRM_IOCTL_ARGS);
1659 int i915_gem_set_caching_ioctl(DRM_IOCTL_ARGS);
1660 int i915_gem_throttle_ioctl(DRM_IOCTL_ARGS);
1661 int i915_gem_madvise_ioctl(DRM_IOCTL_ARGS);
1662 int i915_gem_entervt_ioctl(DRM_IOCTL_ARGS);
1663 int i915_gem_leavevt_ioctl(DRM_IOCTL_ARGS);
1664 int i915_gem_set_tiling(DRM_IOCTL_ARGS);
1665 int i915_gem_get_tiling(DRM_IOCTL_ARGS);
1666 int i915_gem_get_aperture_ioctl(DRM_IOCTL_ARGS);
1667 int i915_gem_wait_ioctl(DRM_IOCTL_ARGS);
1668 void i915_gem_load(struct drm_device *dev);
1669 int i915_gem_init_object(struct drm_gem_object *obj);
1670 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1671 			 const struct drm_i915_gem_object_ops *ops);
1672 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1673 						size_t size);
1674 void i915_gem_free_object(struct drm_gem_object *obj);
1675 int i915_gem_object_pin(struct drm_i915_gem_object *obj,
1676 				     uint32_t alignment,
1677 				     bool map_and_fenceable,
1678 				     bool nonblocking);
1679 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1680 int i915_gem_object_unbind(struct drm_i915_gem_object *obj, uint32_t type);
1681 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1682 void i915_gem_lastclose(struct drm_device *dev);
1683 
i915_gem_object_pin_pages(struct drm_i915_gem_object * obj)1684 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1685 {
1686 	BUG_ON(obj->page_list == NULL);
1687 	obj->pages_pin_count++;
1688 }
i915_gem_object_unpin_pages(struct drm_i915_gem_object * obj)1689 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1690 {
1691 	BUG_ON(obj->pages_pin_count == 0);
1692 	obj->pages_pin_count--;
1693 }
1694 
1695 int i915_mutex_lock_interruptible(struct drm_device *dev);
1696 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1697 			 struct intel_ring_buffer *to);
1698 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1699 				    struct intel_ring_buffer *ring);
1700 
1701 int i915_gem_dumb_create(struct drm_file *file_priv,
1702 			 struct drm_device *dev,
1703 			 struct drm_mode_create_dumb *args);
1704 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1705 		      uint32_t handle, uint64_t *offset);
1706 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1707 			  uint32_t handle);
1708 /**
1709  * Returns true if seq1 is later than seq2.
1710  */
1711 static inline bool
i915_seqno_passed(uint32_t seq1,uint32_t seq2)1712 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1713 {
1714 	return (int32_t)(seq1 - seq2) >= 0;
1715 }
1716 
1717 int i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1718 int i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
1719 int i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1720 int i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1721 
1722 static inline bool
i915_gem_object_pin_fence(struct drm_i915_gem_object * obj)1723 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1724 {
1725 	if (obj->fence_reg != I915_FENCE_REG_NONE) {
1726 		struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1727 		dev_priv->fence_regs[obj->fence_reg].pin_count++;
1728 		return true;
1729 	} else
1730 		return false;
1731 }
1732 
1733 static inline void
i915_gem_object_unpin_fence(struct drm_i915_gem_object * obj)1734 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1735 {
1736 	if (obj->fence_reg != I915_FENCE_REG_NONE) {
1737 		struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1738 		dev_priv->fence_regs[obj->fence_reg].pin_count--;
1739 	}
1740 }
1741 
1742 void i915_gem_retire_requests(struct drm_device *dev);
1743 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1744 int i915_gem_check_wedge(struct i915_gpu_error *error,
1745 				      bool interruptible);
i915_reset_in_progress(struct i915_gpu_error * error)1746 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
1747 {
1748 	return (atomic_read(&error->reset_counter)
1749 			& I915_RESET_IN_PROGRESS_FLAG);
1750 }
1751 
i915_terminally_wedged(struct i915_gpu_error * error)1752 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
1753 {
1754 	return atomic_read(&error->reset_counter) == I915_WEDGED;
1755 }
1756 
1757 void i915_gem_reset(struct drm_device *dev);
1758 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1759 int i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1760 			       uint32_t read_domains,
1761 			       uint32_t write_domain);
1762 int i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1763 int i915_gem_init(struct drm_device *dev);
1764 int i915_gem_init_hw(struct drm_device *dev);
1765 void i915_gem_l3_remap(struct drm_device *dev);
1766 void i915_gem_init_swizzling(struct drm_device *dev);
1767 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1768 int i915_gpu_idle(struct drm_device *dev);
1769 int i915_gem_idle(struct drm_device *dev, uint32_t type);
1770 int __i915_add_request(struct intel_ring_buffer *ring,
1771 		       struct drm_file *file,
1772 		       struct drm_i915_gem_object *batch_obj,
1773 		       u32 *seqno);
1774 #define i915_add_request(ring, seqno) \
1775 	__i915_add_request(ring, NULL, NULL, seqno)
1776 int i915_wait_seqno(struct intel_ring_buffer *ring,
1777 				 uint32_t seqno);
1778 void i915_gem_fault(struct drm_gem_object *obj);
1779 int i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1780 				  bool write);
1781 int
1782 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1783 int
1784 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1785 				     u32 alignment,
1786 				     struct intel_ring_buffer *pipelined);
1787 int i915_gem_attach_phys_object(struct drm_device *dev,
1788 				struct drm_i915_gem_object *obj,
1789 				int id,
1790 				int align);
1791 void i915_gem_detach_phys_object(struct drm_device *dev,
1792 				 struct drm_i915_gem_object *obj);
1793 void i915_gem_free_all_phys_object(struct drm_device *dev);
1794 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1795 
1796 uint32_t
1797 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1798 uint32_t
1799 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1800 			    int tiling_mode, bool fenced);
1801 
1802 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1803 				    enum i915_cache_level cache_level);
1804 void i915_gem_restore_fences(struct drm_device *dev);
1805 
1806 /* i915_gem_context.c */
1807 void i915_gem_context_init(struct drm_device *dev);
1808 void i915_gem_context_fini(struct drm_device *dev);
1809 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1810 int i915_switch_context(struct intel_ring_buffer *ring,
1811 			struct drm_file *file, int to_id);
1812 void i915_gem_context_free(struct kref *ctx_ref);
1813 void i915_gem_context_reference(struct i915_hw_context *ctx);
1814 void i915_gem_context_unreference(struct i915_hw_context *ctx);
1815 
1816 struct i915_ctx_hang_stats *
1817 i915_gem_context_get_hang_stats(struct intel_ring_buffer *ring,
1818 				struct drm_file *file,
1819 				u32 id);
1820 int i915_gem_context_create_ioctl(DRM_IOCTL_ARGS);
1821 int i915_gem_context_destroy_ioctl(DRM_IOCTL_ARGS);
1822 
1823 /* i915_gem_gtt.c */
1824 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1825 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1826 			    struct drm_i915_gem_object *obj,
1827 			    enum i915_cache_level cache_level);
1828 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1829 			      struct drm_i915_gem_object *obj);
1830 
1831 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1832 int i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1833 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1834 				enum i915_cache_level cache_level);
1835 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj, uint32_t type);
1836 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1837 int i915_gem_init_global_gtt(struct drm_device *dev);
1838 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
1839 			       unsigned long mappable_end, unsigned long end);
1840 int i915_setup_scratch_page(struct drm_device *dev);
1841 void i915_teardown_scratch_page(struct drm_device *dev);
1842 int i915_gem_gtt_init(struct drm_device *dev);
1843 void intel_rw_gtt(struct drm_device *dev, size_t size,
1844 		uint32_t gtt_offset, void *gttp, uint32_t type);
1845 void i915_clean_gtt(struct drm_device *dev, size_t offset);
1846 void i915_gem_chipset_flush(struct drm_device *dev);
1847 
1848 /* i915_gem_evict.c */
1849 int i915_gem_evict_something(struct drm_device *dev, int min_size,
1850 					  unsigned alignment,
1851 					  unsigned cache_level,
1852 					  bool mappable,
1853 					  bool nonblock);
1854 int i915_gem_evict_everything(struct drm_device *dev);
1855 
1856 /* i915_gem_stolen.c */
1857 int i915_gem_init_stolen(struct drm_device *dev);
1858 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
1859 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
1860 void i915_gem_cleanup_stolen(struct drm_device *dev);
1861 struct drm_i915_gem_object *
1862 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
1863 struct drm_i915_gem_object *
1864 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
1865 					       u32 stolen_offset,
1866 					       u32 gtt_offset,
1867 					       u32 size);
1868 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
1869 
1870 /* i915_gem_tiling.c */
i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object * obj)1871 inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1872 {
1873 	drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1874 
1875 	return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1876 		obj->tiling_mode != I915_TILING_NONE;
1877 }
1878 
1879 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1880 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1881 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1882 
1883 /* i915_gem_debug.c */
1884 void i915_gem_command_decode(uint32_t *data, int count,
1885 				uint32_t hw_offset, struct drm_device *dev);
1886 void register_dump(struct drm_device *dev);
1887 void gtt_dump(struct drm_device *dev);
1888 void ring_dump(struct drm_device *dev, struct intel_ring_buffer *ring);
1889 
1890 #if WATCH_LISTS
1891 int i915_verify_lists(struct drm_device *dev);
1892 #else
1893 #define i915_verify_lists(dev) 0
1894 #endif
1895 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1896 				     int handle);
1897 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1898 			  const char *where, uint32_t mark);
1899 
1900 /* i915_suspend.c */
1901 extern int i915_save_state(struct drm_device *dev);
1902 extern int i915_restore_state(struct drm_device *dev);
1903 
1904 /* i915_ums.c */
1905 void i915_save_display_reg(struct drm_device *dev);
1906 void i915_restore_display_reg(struct drm_device *dev);
1907 
1908 /* intel_i2c.c */
1909 extern int intel_setup_gmbus(struct drm_device *dev);
1910 extern void intel_teardown_gmbus(struct drm_device *dev);
intel_gmbus_is_port_valid(unsigned port)1911 static inline bool intel_gmbus_is_port_valid(unsigned port)
1912 {
1913 	return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1914 }
1915 
1916 extern struct i2c_adapter *intel_gmbus_get_adapter(
1917 		struct drm_i915_private *dev_priv, unsigned port);
1918 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1919 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
intel_gmbus_is_forced_bit(struct i2c_adapter * adapter)1920 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1921 {
1922 	return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1923 }
1924 extern void intel_i2c_reset(struct drm_device *dev);
1925 extern void intel_gmbus_hdmi_set_adapter(struct i2c_adapter *adapter);
1926 
1927 /* modesetting */
1928 extern void intel_modeset_init_hw(struct drm_device *dev);
1929 extern void intel_modeset_suspend_hw(struct drm_device *dev);
1930 extern void intel_modeset_init(struct drm_device *dev);
1931 extern void intel_modeset_gem_init(struct drm_device *dev);
1932 extern void intel_modeset_cleanup(struct drm_device *dev);
1933 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1934 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1935 					bool force_restore);
1936 extern void i915_redisable_vga(struct drm_device *dev);
1937 extern bool intel_fbc_enabled(struct drm_device *dev);
1938 extern void intel_disable_fbc(struct drm_device *dev);
1939 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1940 extern void intel_init_pch_refclk(struct drm_device *dev);
1941 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1942 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
1943 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
1944 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
1945 extern void intel_detect_pch (struct drm_device *dev);
1946 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1947 extern int intel_enable_rc6(const struct drm_device *dev);
1948 extern void intel_increase_pllclock(struct drm_crtc *crtc);
1949 
1950 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1951 int i915_reg_read_ioctl(DRM_IOCTL_ARGS);
1952 
1953 /* overlay */
1954 #ifdef CONFIG_DEBUG_FS
1955 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1956 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1957 
1958 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1959 extern void intel_display_print_error_state(struct seq_file *m,
1960 					    struct drm_device *dev,
1961 					    struct intel_display_error_state *error);
1962 #endif
1963 
1964 /* On SNB platform, before reading ring registers forcewake bit
1965  * must be set to prevent GT core from power down and stale values being
1966  * returned.
1967  */
1968 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1969 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1970 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1971 
1972 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1973 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1974 
1975 /* intel_sideband.c */
1976 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
1977 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
1978 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
1979 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, int reg);
1980 void vlv_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val);
1981 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1982 		   enum intel_sbi_destination destination);
1983 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1984 		     enum intel_sbi_destination destination);
1985 
1986 int vlv_gpu_freq(int ddr_freq, int val);
1987 int vlv_freq_opcode(int ddr_freq, int val);
1988 
1989 #define __i915_read(x) \
1990 u ## x i915_read ## x(struct drm_i915_private *dev_priv, u32 reg);
1991 
1992 __i915_read(8)
1993 __i915_read(16)
1994 __i915_read(32)
1995 __i915_read(64)
1996 #undef __i915_read
1997 
1998 #define __i915_write(x)	\
1999 void i915_write ## x(struct drm_i915_private *dev_priv, u32 reg,	\
2000 				u ## x val);
2001 
2002 __i915_write(8)
2003 __i915_write(16)
2004 __i915_write(32)
2005 __i915_write(64)
2006 #undef __i915_write
2007 
2008 #define I915_READ(reg)          i915_read32(dev_priv, (reg))
2009 #define I915_WRITE(reg, val)    i915_write32(dev_priv, (reg), (u32)(val))
2010 #define	I915_READ_NOTRACE(reg)	DRM_READ32(dev_priv->regs, (reg))
2011 #define	I915_WRITE_NOTRACE(reg, val)	DRM_WRITE32(dev_priv->regs, (reg), (val))
2012 #define I915_READ16(reg)       i915_read16(dev_priv, (reg))
2013 #define I915_WRITE16(reg,val)  i915_write16(dev_priv, (reg), (u16)(val))
2014 #define	I915_READ16_NOTRACE(reg)	DRM_READ16(dev_priv->regs, (reg))
2015 #define	I915_WRITE16_NOTRACE(reg, val)	DRM_WRITE16(dev_priv->regs, (reg), (val))
2016 #define I915_READ8(reg)        i915_read8(dev_priv, (reg))
2017 #define I915_WRITE8(reg,val)   i915_write8(dev_priv, (reg), (u8)(val))
2018 #define I915_WRITE64(reg,val)  i915_write64(dev_priv, (reg), (u64)(val))
2019 #define I915_READ64(reg)       i915_read64(dev_priv, (reg))
2020 #define POSTING_READ(reg)      (void)DRM_READ32(dev_priv->regs, (reg))
2021 #define POSTING_READ16(reg)    (void)DRM_READ16(dev_priv->regs, (reg))
2022 #define POSTING_READ8(reg)     (void)DRM_READ8(dev_priv->regs, (reg))
2023 
2024 /* "Broadcast RGB" property */
2025 #define INTEL_BROADCAST_RGB_AUTO 0
2026 #define INTEL_BROADCAST_RGB_FULL 1
2027 #define INTEL_BROADCAST_RGB_LIMITED 2
2028 
2029 #define PCI_DEVICE_ID_INTEL_82830_HB	0x3575
2030 #define PCI_DEVICE_ID_INTEL_82830_CGC	0x3577
2031 #define PCI_DEVICE_ID_INTEL_82845G_HB	0x2560
2032 #define PCI_DEVICE_ID_INTEL_82845G_IG	0x2562
2033 #define PCI_DEVICE_ID_INTEL_82855GM_IG	0x3582
2034 #define PCI_DEVICE_ID_INTEL_82865_IG	0x2572
2035 
i915_vgacntrl_reg(struct drm_device * dev)2036 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2037 {
2038 	if (HAS_PCH_SPLIT(dev))
2039 		return CPU_VGACNTRL;
2040 	else if (IS_VALLEYVIEW(dev))
2041 		return VLV_VGACNTRL;
2042 	else
2043 		return VGACNTRL;
2044 }
2045 
2046 #endif /* _I915_DRV_H_ */
2047