1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License (the "License").
6 * You may not use this file except in compliance with the License.
7 *
8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9 * or http://www.opensolaris.org/os/licensing.
10 * See the License for the specific language governing permissions
11 * and limitations under the License.
12 *
13 * When distributing Covered Code, include this CDDL HEADER in each
14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15 * If applicable, add the following below this CDDL HEADER, with the
16 * fields enclosed by brackets "[]" replaced with your own identifying
17 * information: Portions Copyright [yyyy] [name of copyright owner]
18 *
19 * CDDL HEADER END
20 */
21 /*
22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved.
23 * Use is subject to license terms.
24 */
25
26 /*
27 * This file contains preset event names from the Performance Application
28 * Programming Interface v3.5 which included the following notice:
29 *
30 * Copyright (c) 2005,6
31 * Innovative Computing Labs
32 * Computer Science Department,
33 * University of Tennessee,
34 * Knoxville, TN.
35 * All Rights Reserved.
36 *
37 *
38 * Redistribution and use in source and binary forms, with or without
39 * modification, are permitted provided that the following conditions are met:
40 *
41 * * Redistributions of source code must retain the above copyright notice,
42 * this list of conditions and the following disclaimer.
43 * * Redistributions in binary form must reproduce the above copyright
44 * notice, this list of conditions and the following disclaimer in the
45 * documentation and/or other materials provided with the distribution.
46 * * Neither the name of the University of Tennessee nor the names of its
47 * contributors may be used to endorse or promote products derived from
48 * this software without specific prior written permission.
49 *
50 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
51 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
52 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
53 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
54 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
55 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
56 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
57 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
58 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
59 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
60 * POSSIBILITY OF SUCH DAMAGE.
61 *
62 *
63 * This open source software license conforms to the BSD License template.
64 */
65
66 /*
67 * Portions Copyright 2009 Advanced Micro Devices, Inc.
68 * Copyright 2019 Joyent, Inc.
69 * Copyright 2023 Oxide Computer Company
70 */
71
72 /*
73 * Performance Counter Back-End for AMD Opteron and AMD Athlon 64 processors.
74 */
75
76 #include <sys/cpuvar.h>
77 #include <sys/param.h>
78 #include <sys/systm.h>
79 #include <sys/cpc_pcbe.h>
80 #include <sys/kmem.h>
81 #include <sys/sdt.h>
82 #include <sys/modctl.h>
83 #include <sys/errno.h>
84 #include <sys/debug.h>
85 #include <sys/archsystm.h>
86 #include <sys/x86_archext.h>
87 #include <sys/privregs.h>
88 #include <sys/ddi.h>
89 #include <sys/sunddi.h>
90
91 #include "opteron_pcbe_table.h"
92 #include <opteron_pcbe_cpcgen.h>
93
94 static int opt_pcbe_init(void);
95 static uint_t opt_pcbe_ncounters(void);
96 static const char *opt_pcbe_impl_name(void);
97 static const char *opt_pcbe_cpuref(void);
98 static char *opt_pcbe_list_events(uint_t picnum);
99 static char *opt_pcbe_list_attrs(void);
100 static uint64_t opt_pcbe_event_coverage(char *event);
101 static uint64_t opt_pcbe_overflow_bitmap(void);
102 static int opt_pcbe_configure(uint_t picnum, char *event, uint64_t preset,
103 uint32_t flags, uint_t nattrs, kcpc_attr_t *attrs, void **data,
104 void *token);
105 static void opt_pcbe_program(void *token);
106 static void opt_pcbe_allstop(void);
107 static void opt_pcbe_sample(void *token);
108 static void opt_pcbe_free(void *config);
109
110 static pcbe_ops_t opt_pcbe_ops = {
111 PCBE_VER_1,
112 CPC_CAP_OVERFLOW_INTERRUPT,
113 opt_pcbe_ncounters,
114 opt_pcbe_impl_name,
115 opt_pcbe_cpuref,
116 opt_pcbe_list_events,
117 opt_pcbe_list_attrs,
118 opt_pcbe_event_coverage,
119 opt_pcbe_overflow_bitmap,
120 opt_pcbe_configure,
121 opt_pcbe_program,
122 opt_pcbe_allstop,
123 opt_pcbe_sample,
124 opt_pcbe_free
125 };
126
127 /*
128 * Base MSR addresses for the PerfEvtSel registers and the counters themselves.
129 * Add counter number to base address to get corresponding MSR address.
130 */
131 #define PES_BASE_ADDR 0xC0010000
132 #define PIC_BASE_ADDR 0xC0010004
133
134 /*
135 * Base MSR addresses for the PerfEvtSel registers and counters. The counter and
136 * event select registers are interleaved, so one needs to multiply the counter
137 * number by two to determine what they should be set to.
138 */
139 #define PES_EXT_BASE_ADDR 0xC0010200
140 #define PIC_EXT_BASE_ADDR 0xC0010201
141
142 /*
143 * The number of counters present depends on which CPU features are present.
144 */
145 #define OPT_PCBE_DEF_NCOUNTERS 4
146 #define OPT_PCBE_EXT_NCOUNTERS 6
147
148 /*
149 * Define offsets and masks for the fields in the Performance
150 * Event-Select (PES) registers.
151 */
152 #define OPT_PES_HOST_SHIFT 41
153 #define OPT_PES_GUEST_SHIFT 40
154 #define OPT_PES_EVSELHI_SHIFT 32
155 #define OPT_PES_CMASK_SHIFT 24
156 #define OPT_PES_CMASK_MASK 0xFF
157 #define OPT_PES_INV_SHIFT 23
158 #define OPT_PES_ENABLE_SHIFT 22
159 #define OPT_PES_INT_SHIFT 20
160 #define OPT_PES_PC_SHIFT 19
161 #define OPT_PES_EDGE_SHIFT 18
162 #define OPT_PES_OS_SHIFT 17
163 #define OPT_PES_USR_SHIFT 16
164 #define OPT_PES_UMASK_SHIFT 8
165 #define OPT_PES_UMASK_MASK 0xFF
166
167 #define OPT_PES_INV (1ULL << OPT_PES_INV_SHIFT)
168 #define OPT_PES_ENABLE (1ULL << OPT_PES_ENABLE_SHIFT)
169 #define OPT_PES_INT (1ULL << OPT_PES_INT_SHIFT)
170 #define OPT_PES_PC (1ULL << OPT_PES_PC_SHIFT)
171 #define OPT_PES_EDGE (1ULL << OPT_PES_EDGE_SHIFT)
172 #define OPT_PES_OS (1ULL << OPT_PES_OS_SHIFT)
173 #define OPT_PES_USR (1ULL << OPT_PES_USR_SHIFT)
174 #define OPT_PES_HOST (1ULL << OPT_PES_HOST_SHIFT)
175 #define OPT_PES_GUEST (1ULL << OPT_PES_GUEST_SHIFT)
176
177 typedef struct _opt_pcbe_config {
178 uint8_t opt_picno; /* Counter number: 0, 1, 2, or 3 */
179 uint64_t opt_evsel; /* Event Selection register */
180 uint64_t opt_rawpic; /* Raw counter value */
181 } opt_pcbe_config_t;
182
183 opt_pcbe_config_t nullcfgs[OPT_PCBE_EXT_NCOUNTERS] = {
184 { 0, 0, 0 },
185 { 1, 0, 0 },
186 { 2, 0, 0 },
187 { 3, 0, 0 },
188 { 4, 0, 0 },
189 { 5, 0, 0 },
190 };
191
192 typedef uint64_t (*opt_pcbe_addr_f)(uint_t);
193
194 typedef struct opt_pcbe_data {
195 uint_t opd_ncounters;
196 uint_t opd_cmask;
197 opt_pcbe_addr_f opd_pesf;
198 opt_pcbe_addr_f opd_picf;
199 } opt_pcbe_data_t;
200
201 opt_pcbe_data_t opd;
202
203 #define MASK48 0xFFFFFFFFFFFF
204
205 #define EV_END {NULL, 0}
206 #define GEN_EV_END {NULL, NULL, 0 }
207
208 /*
209 * The following Macros are used to define tables of events that are used by
210 * various families and some generic classes of events.
211 *
212 * When programming a performance counter there are two different values that we
213 * need to set:
214 *
215 * o Event - Determines the general class of event that is being used.
216 * o Unit - A further breakdown that gives more specific value.
217 *
218 * Prior to the introduction of family 17h support, all family specific events
219 * were programmed based on their event. The generic events, which tried to
220 * provide PAPI mappings to events specified an additional unit mask.
221 *
222 * Starting with Family 17h, CPU performance counters default to using both the
223 * unit mask and the event select. Generic events are always aliases to a
224 * specific event/unit pair, hence why the units for them are always zero. In
225 * addition, the naming of events in family 17h has been changed to reflect
226 * AMD's guide. While this is a departure from what people are used to, it is
227 * believed that matching the more detailed literature that folks are told to
228 * reference is more valuable.
229 */
230
231 #define AMD_cmn_events \
232 { "FP_dispatched_fpu_ops", 0x0 }, \
233 { "FP_cycles_no_fpu_ops_retired", 0x1 }, \
234 { "FP_dispatched_fpu_ops_ff", 0x2 }, \
235 { "LS_seg_reg_load", 0x20 }, \
236 { "LS_uarch_resync_self_modify", 0x21 }, \
237 { "LS_uarch_resync_snoop", 0x22 }, \
238 { "LS_buffer_2_full", 0x23 }, \
239 { "LS_locked_operation", 0x24 }, \
240 { "LS_retired_cflush", 0x26 }, \
241 { "LS_retired_cpuid", 0x27 }, \
242 { "DC_access", 0x40 }, \
243 { "DC_miss", 0x41 }, \
244 { "DC_refill_from_L2", 0x42 }, \
245 { "DC_refill_from_system", 0x43 }, \
246 { "DC_copyback", 0x44 }, \
247 { "DC_dtlb_L1_miss_L2_hit", 0x45 }, \
248 { "DC_dtlb_L1_miss_L2_miss", 0x46 }, \
249 { "DC_misaligned_data_ref", 0x47 }, \
250 { "DC_uarch_late_cancel_access", 0x48 }, \
251 { "DC_uarch_early_cancel_access", 0x49 }, \
252 { "DC_1bit_ecc_error_found", 0x4A }, \
253 { "DC_dispatched_prefetch_instr", 0x4B }, \
254 { "DC_dcache_accesses_by_locks", 0x4C }, \
255 { "BU_memory_requests", 0x65 }, \
256 { "BU_data_prefetch", 0x67 }, \
257 { "BU_system_read_responses", 0x6C }, \
258 { "BU_cpu_clk_unhalted", 0x76 }, \
259 { "BU_internal_L2_req", 0x7D }, \
260 { "BU_fill_req_missed_L2", 0x7E }, \
261 { "BU_fill_into_L2", 0x7F }, \
262 { "IC_fetch", 0x80 }, \
263 { "IC_miss", 0x81 }, \
264 { "IC_refill_from_L2", 0x82 }, \
265 { "IC_refill_from_system", 0x83 }, \
266 { "IC_itlb_L1_miss_L2_hit", 0x84 }, \
267 { "IC_itlb_L1_miss_L2_miss", 0x85 }, \
268 { "IC_uarch_resync_snoop", 0x86 }, \
269 { "IC_instr_fetch_stall", 0x87 }, \
270 { "IC_return_stack_hit", 0x88 }, \
271 { "IC_return_stack_overflow", 0x89 }, \
272 { "FR_retired_x86_instr_w_excp_intr", 0xC0 }, \
273 { "FR_retired_uops", 0xC1 }, \
274 { "FR_retired_branches_w_excp_intr", 0xC2 }, \
275 { "FR_retired_branches_mispred", 0xC3 }, \
276 { "FR_retired_taken_branches", 0xC4 }, \
277 { "FR_retired_taken_branches_mispred", 0xC5 }, \
278 { "FR_retired_far_ctl_transfer", 0xC6 }, \
279 { "FR_retired_resyncs", 0xC7 }, \
280 { "FR_retired_near_rets", 0xC8 }, \
281 { "FR_retired_near_rets_mispred", 0xC9 }, \
282 { "FR_retired_taken_branches_mispred_addr_miscomp", 0xCA },\
283 { "FR_retired_fastpath_double_op_instr", 0xCC }, \
284 { "FR_intr_masked_cycles", 0xCD }, \
285 { "FR_intr_masked_while_pending_cycles", 0xCE }, \
286 { "FR_taken_hardware_intrs", 0xCF }, \
287 { "FR_nothing_to_dispatch", 0xD0 }, \
288 { "FR_dispatch_stalls", 0xD1 }, \
289 { "FR_dispatch_stall_branch_abort_to_retire", 0xD2 }, \
290 { "FR_dispatch_stall_serialization", 0xD3 }, \
291 { "FR_dispatch_stall_segment_load", 0xD4 }, \
292 { "FR_dispatch_stall_reorder_buffer_full", 0xD5 }, \
293 { "FR_dispatch_stall_resv_stations_full", 0xD6 }, \
294 { "FR_dispatch_stall_fpu_full", 0xD7 }, \
295 { "FR_dispatch_stall_ls_full", 0xD8 }, \
296 { "FR_dispatch_stall_waiting_all_quiet", 0xD9 }, \
297 { "FR_dispatch_stall_far_ctl_trsfr_resync_branch_pend", 0xDA },\
298 { "FR_fpu_exception", 0xDB }, \
299 { "FR_num_brkpts_dr0", 0xDC }, \
300 { "FR_num_brkpts_dr1", 0xDD }, \
301 { "FR_num_brkpts_dr2", 0xDE }, \
302 { "FR_num_brkpts_dr3", 0xDF }, \
303 { "NB_mem_ctrlr_page_access", 0xE0 }, \
304 { "NB_mem_ctrlr_turnaround", 0xE3 }, \
305 { "NB_mem_ctrlr_bypass_counter_saturation", 0xE4 }, \
306 { "NB_cpu_io_to_mem_io", 0xE9 }, \
307 { "NB_cache_block_commands", 0xEA }, \
308 { "NB_sized_commands", 0xEB }, \
309 { "NB_ht_bus0_bandwidth", 0xF6 }
310
311 #define AMD_FAMILY_f_events \
312 { "BU_quadwords_written_to_system", 0x6D }, \
313 { "FR_retired_fpu_instr", 0xCB }, \
314 { "NB_mem_ctrlr_page_table_overflow", 0xE1 }, \
315 { "NB_sized_blocks", 0xE5 }, \
316 { "NB_ECC_errors", 0xE8 }, \
317 { "NB_probe_result", 0xEC }, \
318 { "NB_gart_events", 0xEE }, \
319 { "NB_ht_bus1_bandwidth", 0xF7 }, \
320 { "NB_ht_bus2_bandwidth", 0xF8 }
321
322 #define AMD_FAMILY_10h_events \
323 { "FP_retired_sse_ops", 0x3 }, \
324 { "FP_retired_move_ops", 0x4 }, \
325 { "FP_retired_serialize_ops", 0x5 }, \
326 { "FP_serialize_ops_cycles", 0x6 }, \
327 { "LS_cancelled_store_to_load_fwd_ops", 0x2A }, \
328 { "LS_smi_received", 0x2B }, \
329 { "DC_dtlb_L1_hit", 0x4D }, \
330 { "LS_ineffective_prefetch", 0x52 }, \
331 { "LS_global_tlb_flush", 0x54 }, \
332 { "BU_octwords_written_to_system", 0x6D }, \
333 { "Page_size_mismatches", 0x165 }, \
334 { "IC_eviction", 0x8B }, \
335 { "IC_cache_lines_invalidate", 0x8C }, \
336 { "IC_itlb_reload", 0x99 }, \
337 { "IC_itlb_reload_aborted", 0x9A }, \
338 { "FR_retired_mmx_sse_fp_instr", 0xCB }, \
339 { "Retired_x87_fp_ops", 0x1C0 }, \
340 { "IBS_ops_tagged", 0x1CF }, \
341 { "LFENCE_inst_retired", 0x1D3 }, \
342 { "SFENCE_inst_retired", 0x1D4 }, \
343 { "MFENCE_inst_retired", 0x1D5 }, \
344 { "NB_mem_ctrlr_page_table_overflow", 0xE1 }, \
345 { "NB_mem_ctrlr_dram_cmd_slots_missed", 0xE2 }, \
346 { "NB_thermal_status", 0xE8 }, \
347 { "NB_probe_results_upstream_req", 0xEC }, \
348 { "NB_gart_events", 0xEE }, \
349 { "NB_mem_ctrlr_req", 0x1F0 }, \
350 { "CB_cpu_to_dram_req_to_target", 0x1E0 }, \
351 { "CB_io_to_dram_req_to_target", 0x1E1 }, \
352 { "CB_cpu_read_cmd_latency_to_target_0_to_3", 0x1E2 }, \
353 { "CB_cpu_read_cmd_req_to_target_0_to_3", 0x1E3 }, \
354 { "CB_cpu_read_cmd_latency_to_target_4_to_7", 0x1E4 }, \
355 { "CB_cpu_read_cmd_req_to_target_4_to_7", 0x1E5 }, \
356 { "CB_cpu_cmd_latency_to_target_0_to_7", 0x1E6 }, \
357 { "CB_cpu_req_to_target_0_to_7", 0x1E7 }, \
358 { "NB_ht_bus1_bandwidth", 0xF7 }, \
359 { "NB_ht_bus2_bandwidth", 0xF8 }, \
360 { "NB_ht_bus3_bandwidth", 0x1F9 }, \
361 { "L3_read_req", 0x4E0 }, \
362 { "L3_miss", 0x4E1 }, \
363 { "L3_l2_eviction_l3_fill", 0x4E2 }, \
364 { "L3_eviction", 0x4E3 }
365
366 #define AMD_FAMILY_11h_events \
367 { "BU_quadwords_written_to_system", 0x6D }, \
368 { "FR_retired_mmx_fp_instr", 0xCB }, \
369 { "NB_mem_ctrlr_page_table_events", 0xE1 }, \
370 { "NB_thermal_status", 0xE8 }, \
371 { "NB_probe_results_upstream_req", 0xEC }, \
372 { "NB_dev_events", 0xEE }, \
373 { "NB_mem_ctrlr_req", 0x1F0 }
374
375 #define AMD_cmn_generic_events \
376 { "PAPI_br_ins", "FR_retired_branches_w_excp_intr", 0x0 },\
377 { "PAPI_br_msp", "FR_retired_branches_mispred", 0x0 }, \
378 { "PAPI_br_tkn", "FR_retired_taken_branches", 0x0 }, \
379 { "PAPI_fp_ops", "FP_dispatched_fpu_ops", 0x3 }, \
380 { "PAPI_fad_ins", "FP_dispatched_fpu_ops", 0x1 }, \
381 { "PAPI_fml_ins", "FP_dispatched_fpu_ops", 0x2 }, \
382 { "PAPI_fpu_idl", "FP_cycles_no_fpu_ops_retired", 0x0 }, \
383 { "PAPI_tot_cyc", "BU_cpu_clk_unhalted", 0x0 }, \
384 { "PAPI_tot_ins", "FR_retired_x86_instr_w_excp_intr", 0x0 }, \
385 { "PAPI_l1_dca", "DC_access", 0x0 }, \
386 { "PAPI_l1_dcm", "DC_miss", 0x0 }, \
387 { "PAPI_l1_ldm", "DC_refill_from_L2", 0xe }, \
388 { "PAPI_l1_stm", "DC_refill_from_L2", 0x10 }, \
389 { "PAPI_l1_ica", "IC_fetch", 0x0 }, \
390 { "PAPI_l1_icm", "IC_miss", 0x0 }, \
391 { "PAPI_l1_icr", "IC_fetch", 0x0 }, \
392 { "PAPI_l2_dch", "DC_refill_from_L2", 0x1e }, \
393 { "PAPI_l2_dcm", "DC_refill_from_system", 0x1e }, \
394 { "PAPI_l2_dcr", "DC_refill_from_L2", 0xe }, \
395 { "PAPI_l2_dcw", "DC_refill_from_L2", 0x10 }, \
396 { "PAPI_l2_ich", "IC_refill_from_L2", 0x0 }, \
397 { "PAPI_l2_icm", "IC_refill_from_system", 0x0 }, \
398 { "PAPI_l2_ldm", "DC_refill_from_system", 0xe }, \
399 { "PAPI_l2_stm", "DC_refill_from_system", 0x10 }, \
400 { "PAPI_res_stl", "FR_dispatch_stalls", 0x0 }, \
401 { "PAPI_stl_icy", "FR_nothing_to_dispatch", 0x0 }, \
402 { "PAPI_hw_int", "FR_taken_hardware_intrs", 0x0 }
403
404 #define OPT_cmn_generic_events \
405 { "PAPI_tlb_dm", "DC_dtlb_L1_miss_L2_miss", 0x0 }, \
406 { "PAPI_tlb_im", "IC_itlb_L1_miss_L2_miss", 0x0 }, \
407 { "PAPI_fp_ins", "FR_retired_fpu_instr", 0xd }, \
408 { "PAPI_vec_ins", "FR_retired_fpu_instr", 0x4 }
409
410 #define AMD_FAMILY_10h_generic_events \
411 { "PAPI_tlb_dm", "DC_dtlb_L1_miss_L2_miss", 0x7 }, \
412 { "PAPI_tlb_im", "IC_itlb_L1_miss_L2_miss", 0x3 }, \
413 { "PAPI_l3_dcr", "L3_read_req", 0xf1 }, \
414 { "PAPI_l3_icr", "L3_read_req", 0xf2 }, \
415 { "PAPI_l3_tcr", "L3_read_req", 0xf7 }, \
416 { "PAPI_l3_stm", "L3_miss", 0xf4 }, \
417 { "PAPI_l3_ldm", "L3_miss", 0xf3 }, \
418 { "PAPI_l3_tcm", "L3_miss", 0xf7 }
419
420 static const amd_event_t family_f_events[] = {
421 AMD_cmn_events,
422 AMD_FAMILY_f_events,
423 EV_END
424 };
425
426 static const amd_event_t family_10h_events[] = {
427 AMD_cmn_events,
428 AMD_FAMILY_10h_events,
429 EV_END
430 };
431
432 static const amd_event_t family_11h_events[] = {
433 AMD_cmn_events,
434 AMD_FAMILY_11h_events,
435 EV_END
436 };
437
438 static const amd_generic_event_t opt_generic_events[] = {
439 AMD_cmn_generic_events,
440 OPT_cmn_generic_events,
441 GEN_EV_END
442 };
443
444 static const amd_generic_event_t family_10h_generic_events[] = {
445 AMD_cmn_generic_events,
446 AMD_FAMILY_10h_generic_events,
447 GEN_EV_END
448 };
449
450 /*
451 * For Family 17h and Family 19h, the cpcgen utility generates all of our events
452 * including ones that need specific unit codes, therefore we leave all unit
453 * codes out of these. Zen 1, Zen 2, and Zen 3 have different event sets that
454 * they support.
455 */
456 static const amd_generic_event_t family_17h_zen1_papi_events[] = {
457 { "PAPI_br_cn", "ExRetCond" },
458 { "PAPI_br_ins", "ExRetBrn" },
459 { "PAPI_fpu_idl", "FpSchedEmpty" },
460 { "PAPI_tot_cyc", "LsNotHaltedCyc" },
461 { "PAPI_tot_ins", "ExRetInstr" },
462 { "PAPI_tlb_dm", "LsL1DTlbMiss" },
463 { "PAPI_tlb_im", "BpL1TlbMissL2Miss" },
464 GEN_EV_END
465 };
466
467 static const amd_generic_event_t family_17h_zen2_papi_events[] = {
468 { "PAPI_br_cn", "ExRetCond" },
469 { "PAPI_br_ins", "ExRetBrn" },
470 { "PAPI_tot_cyc", "LsNotHaltedCyc" },
471 { "PAPI_tot_ins", "ExRetInstr" },
472 { "PAPI_tlb_dm", "LsL1DTlbMiss" },
473 { "PAPI_tlb_im", "BpL1TlbMissL2Miss" },
474 GEN_EV_END
475 };
476
477 static const amd_generic_event_t family_19h_zen3_papi_events[] = {
478 { "PAPI_br_cn", "ExRetCond" },
479 { "PAPI_br_ins", "ExRetBrn" },
480 { "PAPI_tot_cyc", "LsNotHaltedCyc" },
481 { "PAPI_tot_ins", "ExRetInstr" },
482 { "PAPI_tlb_dm", "LsL1DTlbMiss" },
483 { "PAPI_tlb_im", "BpL1TlbMissL2TlbMiss" },
484 GEN_EV_END
485 };
486
487 static const amd_generic_event_t family_19h_zen4_papi_events[] = {
488 { "PAPI_br_cn", "ExRetCond" },
489 { "PAPI_br_ins", "ExRetBrn" },
490 { "PAPI_tot_cyc", "LsNotHaltedCyc" },
491 { "PAPI_tot_ins", "ExRetInstr" },
492 { "PAPI_tlb_dm", "LsL1DTlbMiss" },
493 { "PAPI_tlb_im", "BpL1TlbMissL2TlbMiss" },
494 GEN_EV_END
495 };
496
497
498
499 static char *evlist;
500 static size_t evlist_sz;
501 static const amd_event_t *amd_events = NULL;
502 static uint_t amd_family, amd_model;
503 static const amd_generic_event_t *amd_generic_events = NULL;
504
505 static char amd_fam_f_rev_ae_bkdg[] = "See \"BIOS and Kernel Developer's "
506 "Guide for AMD Athlon 64 and AMD Opteron Processors\" (AMD publication 26094)";
507 static char amd_fam_f_NPT_bkdg[] = "See \"BIOS and Kernel Developer's Guide "
508 "for AMD NPT Family 0Fh Processors\" (AMD publication 32559)";
509 static char amd_fam_10h_bkdg[] = "See \"BIOS and Kernel Developer's Guide "
510 "(BKDG) For AMD Family 10h Processors\" (AMD publication 31116)";
511 static char amd_fam_11h_bkdg[] = "See \"BIOS and Kernel Developer's Guide "
512 "(BKDG) For AMD Family 11h Processors\" (AMD publication 41256)";
513 static char amd_fam_17h_zen1_reg[] = "See \"Open-Source Register Reference For "
514 "AMD Family 17h Processors Models 00h-2Fh\" (AMD publication 56255) and "
515 "amd_f17h_zen1_events(3CPC)";
516 static char amd_fam_17h_zen2_reg[] = "See \"Preliminary Processor Programming "
517 "Reference (PPR) for AMD Family 17h Model 31h, Revision B0 Processors\" "
518 "(AMD publication 55803), \"Processor Programming Reference (PPR) for AMD "
519 "Family 17h Model 71h, Revision B0 Processors\" (AMD publication 56176), and "
520 "amd_f17h_zen2_events(3CPC)";
521 static char amd_fam_19h_zen3_reg[] = "See \"Preliminary Processor Programming "
522 "Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors Volume "
523 "1 of 2\" (AMD publication 55898), \"Processor Programming Reference (PPR) "
524 "for AMD Family 19h Model 21h, Revision B0 Processors\" (AMD publication "
525 "56214), and amd_f19h_zen3_events(3CPC)";
526 static char amd_fam_19h_zen4_reg[] = "See \"Processor Programming Reference "
527 "(PPR) for AMD Family 19h Model 11h, Revision B1 Processors Volume 1 of 6\" "
528 "(AMD publication 55901), \"Processor Programming Reference (PPR) for AMD "
529 "Family 19h Model 61h, Revision B1 Processors\" (AMD publication 56713), "
530 "\"Processor Programming Reference (PPR) for AMD Family 19h Model 70h, "
531 "Revision A0 Processors\" (AMD publication 57019), and "
532 "amd_f19h_zen4_events(3CPC)";
533
534
535 static char amd_pcbe_impl_name[64];
536 static char *amd_pcbe_cpuref;
537
538
539 #define BITS(v, u, l) \
540 (((v) >> (l)) & ((1 << (1 + (u) - (l))) - 1))
541
542 static uint64_t
opt_pcbe_pes_addr(uint_t counter)543 opt_pcbe_pes_addr(uint_t counter)
544 {
545 ASSERT3U(counter, <, opd.opd_ncounters);
546 return (PES_BASE_ADDR + counter);
547 }
548
549 static uint64_t
opt_pcbe_pes_ext_addr(uint_t counter)550 opt_pcbe_pes_ext_addr(uint_t counter)
551 {
552 ASSERT3U(counter, <, opd.opd_ncounters);
553 return (PES_EXT_BASE_ADDR + 2 * counter);
554 }
555
556 static uint64_t
opt_pcbe_pic_addr(uint_t counter)557 opt_pcbe_pic_addr(uint_t counter)
558 {
559 ASSERT3U(counter, <, opd.opd_ncounters);
560 return (PIC_BASE_ADDR + counter);
561 }
562
563 static uint64_t
opt_pcbe_pic_ext_addr(uint_t counter)564 opt_pcbe_pic_ext_addr(uint_t counter)
565 {
566 ASSERT3U(counter, <, opd.opd_ncounters);
567 return (PIC_EXT_BASE_ADDR + 2 * counter);
568 }
569
570 static int
opt_pcbe_init(void)571 opt_pcbe_init(void)
572 {
573 const amd_event_t *evp;
574 const amd_generic_event_t *gevp;
575 x86_uarchrev_t uarchrev;
576
577 amd_family = cpuid_getfamily(CPU);
578 amd_model = cpuid_getmodel(CPU);
579 uarchrev = cpuid_getuarchrev(CPU);
580
581 /*
582 * Make sure this really _is_ an Opteron or Athlon 64 system. The kernel
583 * loads this module based on its name in the module directory, but it
584 * could have been renamed.
585 */
586 if ((cpuid_getvendor(CPU) != X86_VENDOR_AMD || amd_family < 0xf) &&
587 cpuid_getvendor(CPU) != X86_VENDOR_HYGON)
588 return (-1);
589
590 if (amd_family == 0xf) {
591 /* Some tools expect this string for family 0fh */
592 (void) snprintf(amd_pcbe_impl_name, sizeof (amd_pcbe_impl_name),
593 "AMD Opteron & Athlon64");
594 } else {
595 (void) snprintf(amd_pcbe_impl_name, sizeof (amd_pcbe_impl_name),
596 "%s Family %02xh",
597 cpuid_getvendor(CPU) == X86_VENDOR_HYGON ? "Hygon" : "AMD",
598 amd_family);
599 }
600
601 /*
602 * Determine whether or not the extended counter set is supported on
603 * this processor.
604 */
605 if (is_x86_feature(x86_featureset, X86FSET_AMD_PCEC)) {
606 opd.opd_ncounters = OPT_PCBE_EXT_NCOUNTERS;
607 opd.opd_pesf = opt_pcbe_pes_ext_addr;
608 opd.opd_picf = opt_pcbe_pic_ext_addr;
609 } else {
610 opd.opd_ncounters = OPT_PCBE_DEF_NCOUNTERS;
611 opd.opd_pesf = opt_pcbe_pes_addr;
612 opd.opd_picf = opt_pcbe_pic_addr;
613 }
614 opd.opd_cmask = (1 << opd.opd_ncounters) - 1;
615
616 /*
617 * Figure out processor revision here and assign appropriate
618 * event configuration.
619 */
620 switch (uarchrev_uarch(uarchrev)) {
621 case X86_UARCH_AMD_LEGACY:
622 switch (amd_family) {
623 case 0xf: {
624 x86_chiprev_t rev;
625
626 rev = cpuid_getchiprev(CPU);
627
628 if (chiprev_at_least(rev,
629 X86_CHIPREV_AMD_LEGACY_F_REV_F)) {
630 amd_pcbe_cpuref = amd_fam_f_NPT_bkdg;
631 } else {
632 amd_pcbe_cpuref = amd_fam_f_rev_ae_bkdg;
633 }
634 amd_events = family_f_events;
635 amd_generic_events = opt_generic_events;
636 break;
637 }
638 case 0x10:
639 amd_pcbe_cpuref = amd_fam_10h_bkdg;
640 amd_events = family_10h_events;
641 amd_generic_events = family_10h_generic_events;
642 break;
643 case 0x11:
644 amd_pcbe_cpuref = amd_fam_11h_bkdg;
645 amd_events = family_11h_events;
646 amd_generic_events = opt_generic_events;
647 break;
648 default:
649 return (-1);
650 }
651 break;
652 case X86_UARCH_AMD_ZEN1:
653 case X86_UARCH_AMD_ZENPLUS:
654 amd_pcbe_cpuref = amd_fam_17h_zen1_reg;
655 amd_events = opteron_pcbe_f17h_zen1_events;
656 amd_generic_events = family_17h_zen1_papi_events;
657 break;
658 case X86_UARCH_AMD_ZEN2:
659 amd_pcbe_cpuref = amd_fam_17h_zen2_reg;
660 amd_events = opteron_pcbe_f17h_zen2_events;
661 amd_generic_events = family_17h_zen2_papi_events;
662 break;
663 case X86_UARCH_AMD_ZEN3:
664 amd_pcbe_cpuref = amd_fam_19h_zen3_reg;
665 amd_events = opteron_pcbe_f19h_zen3_events;
666 amd_generic_events = family_19h_zen3_papi_events;
667 break;
668 case X86_UARCH_AMD_ZEN4:
669 amd_pcbe_cpuref = amd_fam_19h_zen4_reg;
670 amd_events = opteron_pcbe_f19h_zen4_events;
671 amd_generic_events = family_19h_zen4_papi_events;
672 break;
673 default:
674 /*
675 * Different families have different meanings on events and even
676 * worse (like family 15h), different constraints around
677 * programming these values.
678 */
679 return (-1);
680 }
681
682 /*
683 * Construct event list.
684 *
685 * First pass: Calculate size needed. We'll need an additional byte
686 * for the NULL pointer during the last strcat.
687 *
688 * Second pass: Copy strings.
689 */
690 for (evp = amd_events; evp->name != NULL; evp++)
691 evlist_sz += strlen(evp->name) + 1;
692
693 for (gevp = amd_generic_events; gevp->name != NULL; gevp++)
694 evlist_sz += strlen(gevp->name) + 1;
695
696 evlist = kmem_alloc(evlist_sz + 1, KM_SLEEP);
697 evlist[0] = '\0';
698
699 for (evp = amd_events; evp->name != NULL; evp++) {
700 (void) strcat(evlist, evp->name);
701 (void) strcat(evlist, ",");
702 }
703
704 for (gevp = amd_generic_events; gevp->name != NULL; gevp++) {
705 (void) strcat(evlist, gevp->name);
706 (void) strcat(evlist, ",");
707 }
708
709 /*
710 * Remove trailing comma.
711 */
712 evlist[evlist_sz - 1] = '\0';
713
714 return (0);
715 }
716
717 static uint_t
opt_pcbe_ncounters(void)718 opt_pcbe_ncounters(void)
719 {
720 return (opd.opd_ncounters);
721 }
722
723 static const char *
opt_pcbe_impl_name(void)724 opt_pcbe_impl_name(void)
725 {
726 return (amd_pcbe_impl_name);
727 }
728
729 static const char *
opt_pcbe_cpuref(void)730 opt_pcbe_cpuref(void)
731 {
732
733 return (amd_pcbe_cpuref);
734 }
735
736 /*ARGSUSED*/
737 static char *
opt_pcbe_list_events(uint_t picnum)738 opt_pcbe_list_events(uint_t picnum)
739 {
740 return (evlist);
741 }
742
743 static char *
opt_pcbe_list_attrs(void)744 opt_pcbe_list_attrs(void)
745 {
746 return ("edge,pc,inv,cmask,umask");
747 }
748
749 static const amd_generic_event_t *
find_generic_event(char * name)750 find_generic_event(char *name)
751 {
752 const amd_generic_event_t *gevp;
753
754 for (gevp = amd_generic_events; gevp->name != NULL; gevp++)
755 if (strcmp(name, gevp->name) == 0)
756 return (gevp);
757
758 return (NULL);
759 }
760
761 static const amd_event_t *
find_event(char * name)762 find_event(char *name)
763 {
764 const amd_event_t *evp;
765
766 for (evp = amd_events; evp->name != NULL; evp++)
767 if (strcmp(name, evp->name) == 0)
768 return (evp);
769
770 return (NULL);
771 }
772
773 /*ARGSUSED*/
774 static uint64_t
opt_pcbe_event_coverage(char * event)775 opt_pcbe_event_coverage(char *event)
776 {
777 /*
778 * Check whether counter event is supported
779 */
780 if (find_event(event) == NULL && find_generic_event(event) == NULL)
781 return (0);
782
783 /*
784 * Fortunately, all counters can count all events.
785 */
786 return (opd.opd_cmask);
787 }
788
789 static uint64_t
opt_pcbe_overflow_bitmap(void)790 opt_pcbe_overflow_bitmap(void)
791 {
792 /*
793 * Unfortunately, this chip cannot detect which counter overflowed, so
794 * we must act as if they all did.
795 */
796 return (opd.opd_cmask);
797 }
798
799 /*ARGSUSED*/
800 static int
opt_pcbe_configure(uint_t picnum,char * event,uint64_t preset,uint32_t flags,uint_t nattrs,kcpc_attr_t * attrs,void ** data,void * token)801 opt_pcbe_configure(uint_t picnum, char *event, uint64_t preset, uint32_t flags,
802 uint_t nattrs, kcpc_attr_t *attrs, void **data, void *token)
803 {
804 opt_pcbe_config_t *cfg;
805 const amd_event_t *evp;
806 amd_event_t ev_raw = { "raw", 0};
807 const amd_generic_event_t *gevp;
808 int i;
809 uint64_t evsel = 0, evsel_tmp = 0;
810
811 /*
812 * If we've been handed an existing configuration, we need only preset
813 * the counter value.
814 */
815 if (*data != NULL) {
816 cfg = *data;
817 cfg->opt_rawpic = preset & MASK48;
818 return (0);
819 }
820
821 if (picnum >= opd.opd_ncounters)
822 return (CPC_INVALID_PICNUM);
823
824 if ((evp = find_event(event)) == NULL) {
825 if ((gevp = find_generic_event(event)) != NULL) {
826 evp = find_event(gevp->event);
827 ASSERT(evp != NULL);
828
829 if (nattrs > 0)
830 return (CPC_ATTRIBUTE_OUT_OF_RANGE);
831
832 evsel |= gevp->umask << OPT_PES_UMASK_SHIFT;
833 } else {
834 long tmp;
835
836 /*
837 * If ddi_strtol() likes this event, use it as a raw
838 * event code.
839 */
840 if (ddi_strtol(event, NULL, 0, &tmp) != 0)
841 return (CPC_INVALID_EVENT);
842
843 ev_raw.emask = tmp;
844 evp = &ev_raw;
845 }
846 }
847
848 /*
849 * Configuration of EventSelect register. While on some families
850 * certain bits might not be supported (e.g. Guest/Host on family
851 * 11h), setting these bits is harmless
852 */
853
854 /* Set GuestOnly bit to 0 and HostOnly bit to 1 */
855 evsel &= ~OPT_PES_HOST;
856 evsel &= ~OPT_PES_GUEST;
857
858 /* Set bits [35:32] for extended part of Event Select field */
859 evsel_tmp = evp->emask & 0x0f00;
860 evsel |= evsel_tmp << OPT_PES_EVSELHI_SHIFT;
861
862 evsel |= evp->emask & 0x00ff;
863 evsel |= evp->unit << OPT_PES_UMASK_SHIFT;
864
865 if (flags & CPC_COUNT_USER)
866 evsel |= OPT_PES_USR;
867 if (flags & CPC_COUNT_SYSTEM)
868 evsel |= OPT_PES_OS;
869 if (flags & CPC_OVF_NOTIFY_EMT)
870 evsel |= OPT_PES_INT;
871
872 for (i = 0; i < nattrs; i++) {
873 if (strcmp(attrs[i].ka_name, "edge") == 0) {
874 if (attrs[i].ka_val != 0)
875 evsel |= OPT_PES_EDGE;
876 } else if (strcmp(attrs[i].ka_name, "pc") == 0) {
877 if (attrs[i].ka_val != 0)
878 evsel |= OPT_PES_PC;
879 } else if (strcmp(attrs[i].ka_name, "inv") == 0) {
880 if (attrs[i].ka_val != 0)
881 evsel |= OPT_PES_INV;
882 } else if (strcmp(attrs[i].ka_name, "cmask") == 0) {
883 if ((attrs[i].ka_val | OPT_PES_CMASK_MASK) !=
884 OPT_PES_CMASK_MASK)
885 return (CPC_ATTRIBUTE_OUT_OF_RANGE);
886 evsel |= attrs[i].ka_val << OPT_PES_CMASK_SHIFT;
887 } else if (strcmp(attrs[i].ka_name, "umask") == 0) {
888 if ((attrs[i].ka_val | OPT_PES_UMASK_MASK) !=
889 OPT_PES_UMASK_MASK)
890 return (CPC_ATTRIBUTE_OUT_OF_RANGE);
891 evsel |= attrs[i].ka_val << OPT_PES_UMASK_SHIFT;
892 } else
893 return (CPC_INVALID_ATTRIBUTE);
894 }
895
896 cfg = kmem_alloc(sizeof (*cfg), KM_SLEEP);
897
898 cfg->opt_picno = picnum;
899 cfg->opt_evsel = evsel;
900 cfg->opt_rawpic = preset & MASK48;
901
902 *data = cfg;
903 return (0);
904 }
905
906 static void
opt_pcbe_program(void * token)907 opt_pcbe_program(void *token)
908 {
909 opt_pcbe_config_t *cfgs[OPT_PCBE_EXT_NCOUNTERS] = { &nullcfgs[0],
910 &nullcfgs[1], &nullcfgs[2],
911 &nullcfgs[3], &nullcfgs[4],
912 &nullcfgs[5] };
913 opt_pcbe_config_t *pcfg = NULL;
914 int i;
915 ulong_t curcr4 = getcr4();
916
917 /*
918 * Allow nonprivileged code to read the performance counters if desired.
919 */
920 if (kcpc_allow_nonpriv(token))
921 setcr4(curcr4 | CR4_PCE);
922 else
923 setcr4(curcr4 & ~CR4_PCE);
924
925 /*
926 * Query kernel for all configs which will be co-programmed.
927 */
928 do {
929 pcfg = (opt_pcbe_config_t *)kcpc_next_config(token, pcfg, NULL);
930
931 if (pcfg != NULL) {
932 ASSERT(pcfg->opt_picno < opd.opd_ncounters);
933 cfgs[pcfg->opt_picno] = pcfg;
934 }
935 } while (pcfg != NULL);
936
937 /*
938 * Program in two loops. The first configures and presets the counter,
939 * and the second loop enables the counters. This ensures that the
940 * counters are all enabled as closely together in time as possible.
941 */
942
943 for (i = 0; i < opd.opd_ncounters; i++) {
944 wrmsr(opd.opd_pesf(i), cfgs[i]->opt_evsel);
945 wrmsr(opd.opd_picf(i), cfgs[i]->opt_rawpic);
946 }
947
948 for (i = 0; i < opd.opd_ncounters; i++) {
949 wrmsr(opd.opd_pesf(i), cfgs[i]->opt_evsel |
950 (uint64_t)(uintptr_t)OPT_PES_ENABLE);
951 }
952 }
953
954 static void
opt_pcbe_allstop(void)955 opt_pcbe_allstop(void)
956 {
957 int i;
958
959 for (i = 0; i < opd.opd_ncounters; i++)
960 wrmsr(opd.opd_pesf(i), 0ULL);
961
962 /*
963 * Disable non-privileged access to the counter registers.
964 */
965 setcr4(getcr4() & ~CR4_PCE);
966 }
967
968 static void
opt_pcbe_sample(void * token)969 opt_pcbe_sample(void *token)
970 {
971 opt_pcbe_config_t *cfgs[OPT_PCBE_EXT_NCOUNTERS] = { NULL, NULL,
972 NULL, NULL, NULL, NULL };
973 opt_pcbe_config_t *pcfg = NULL;
974 int i;
975 uint64_t curpic[OPT_PCBE_EXT_NCOUNTERS];
976 uint64_t *addrs[OPT_PCBE_EXT_NCOUNTERS];
977 uint64_t *tmp;
978 int64_t diff;
979
980 for (i = 0; i < opd.opd_ncounters; i++)
981 curpic[i] = rdmsr(opd.opd_picf(i));
982
983 /*
984 * Query kernel for all configs which are co-programmed.
985 */
986 do {
987 pcfg = (opt_pcbe_config_t *)kcpc_next_config(token, pcfg, &tmp);
988
989 if (pcfg != NULL) {
990 ASSERT3U(pcfg->opt_picno, <, opd.opd_ncounters);
991 cfgs[pcfg->opt_picno] = pcfg;
992 addrs[pcfg->opt_picno] = tmp;
993 }
994 } while (pcfg != NULL);
995
996 for (i = 0; i < opd.opd_ncounters; i++) {
997 if (cfgs[i] == NULL)
998 continue;
999
1000 diff = (curpic[i] - cfgs[i]->opt_rawpic) & MASK48;
1001 *addrs[i] += diff;
1002 DTRACE_PROBE4(opt__pcbe__sample, int, i, uint64_t, *addrs[i],
1003 uint64_t, curpic[i], uint64_t, cfgs[i]->opt_rawpic);
1004 cfgs[i]->opt_rawpic = *addrs[i] & MASK48;
1005 }
1006 }
1007
1008 static void
opt_pcbe_free(void * config)1009 opt_pcbe_free(void *config)
1010 {
1011 kmem_free(config, sizeof (opt_pcbe_config_t));
1012 }
1013
1014
1015 static struct modlpcbe modlpcbe = {
1016 &mod_pcbeops,
1017 "AMD Performance Counters",
1018 &opt_pcbe_ops
1019 };
1020
1021 static struct modlinkage modl = {
1022 MODREV_1,
1023 &modlpcbe,
1024 };
1025
1026 int
_init(void)1027 _init(void)
1028 {
1029 int ret;
1030
1031 if (opt_pcbe_init() != 0)
1032 return (ENOTSUP);
1033
1034 if ((ret = mod_install(&modl)) != 0)
1035 kmem_free(evlist, evlist_sz + 1);
1036
1037 return (ret);
1038 }
1039
1040 int
_fini(void)1041 _fini(void)
1042 {
1043 int ret;
1044
1045 if ((ret = mod_remove(&modl)) == 0)
1046 kmem_free(evlist, evlist_sz + 1);
1047 return (ret);
1048 }
1049
1050 int
_info(struct modinfo * mi)1051 _info(struct modinfo *mi)
1052 {
1053 return (mod_info(&modl, mi));
1054 }
1055