1 /*
2 * CDDL HEADER START
3 *
4 * The contents of this file are subject to the terms of the
5 * Common Development and Distribution License, Version 1.0 only
6 * (the "License"). You may not use this file except in compliance
7 * with the License.
8 *
9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10 * or http://www.opensolaris.org/os/licensing.
11 * See the License for the specific language governing permissions
12 * and limitations under the License.
13 *
14 * When distributing Covered Code, include this CDDL HEADER in each
15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16 * If applicable, add the following below this CDDL HEADER, with the
17 * fields enclosed by brackets "[]" replaced with your own identifying
18 * information: Portions Copyright [yyyy] [name of copyright owner]
19 *
20 * CDDL HEADER END
21 */
22 /*
23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved.
24 * Use is subject to license terms.
25 */
26
27 /*
28 * dcam_reg.c
29 *
30 * dcam1394 driver. Control register access support.
31 */
32
33 #include <sys/1394/targets/dcam1394/dcam_reg.h>
34
35
36 /*
37 * dcam_reg_read
38 */
39 int
dcam_reg_read(dcam_state_t * soft_state,dcam1394_reg_io_t * arg)40 dcam_reg_read(dcam_state_t *soft_state, dcam1394_reg_io_t *arg)
41 {
42 cmd1394_cmd_t *cmdp;
43
44 if (t1394_alloc_cmd(soft_state->sl_handle, 1, &cmdp) != DDI_SUCCESS) {
45 return (-1);
46 }
47
48 cmdp->cmd_type = CMD1394_ASYNCH_RD_QUAD;
49 cmdp->cmd_addr = 0x0000FFFFF0F00000 |
50 (uint64_t)(arg->offs & 0x00000FFC);
51 cmdp->cmd_options = CMD1394_BLOCKING;
52
53 #ifdef GRAPHICS_DELAY
54 /*
55 * This delay should not be necessary, but was added for some
56 * unknown reason. Should it ever be determined that it
57 * is necessary, this delay should be reenabled.
58 */
59 delay(drv_usectohz(500));
60 #endif
61
62 if (t1394_read(soft_state->sl_handle, cmdp) != DDI_SUCCESS) {
63 (void) t1394_free_cmd(soft_state->sl_handle, 0, &cmdp);
64 return (-1);
65 }
66
67 if (cmdp->cmd_result != DDI_SUCCESS) {
68 (void) t1394_free_cmd(soft_state->sl_handle, 0, &cmdp);
69 return (-1);
70 }
71
72 /* perform endian adjustment */
73 cmdp->cmd_u.q.quadlet_data = T1394_DATA32(cmdp->cmd_u.q.quadlet_data);
74 arg->val = cmdp->cmd_u.q.quadlet_data;
75
76 (void) t1394_free_cmd(soft_state->sl_handle, 0, &cmdp);
77
78 return (0);
79 }
80
81
82 /*
83 * dcam_reg_write
84 */
85 int
dcam_reg_write(dcam_state_t * soft_state,dcam1394_reg_io_t * arg)86 dcam_reg_write(dcam_state_t *soft_state, dcam1394_reg_io_t *arg)
87 {
88 cmd1394_cmd_t *cmdp;
89
90 if (t1394_alloc_cmd(soft_state->sl_handle, 0, &cmdp) != DDI_SUCCESS) {
91 return (-1);
92 }
93
94 cmdp->cmd_type = CMD1394_ASYNCH_WR_QUAD;
95 cmdp->cmd_addr = 0x0000FFFFF0F00000 |
96 (uint64_t)(arg->offs & 0x00000FFC);
97 cmdp->cmd_options = CMD1394_BLOCKING;
98
99 /* perform endian adjustment */
100 cmdp->cmd_u.q.quadlet_data = T1394_DATA32(arg->val);
101
102 #ifdef GRAPHICS_DELAY
103 /*
104 * See the description in dcam_reg_read() above.
105 */
106 delay(drv_usectohz(500));
107 #endif
108
109 if (t1394_write(soft_state->sl_handle, cmdp) != DDI_SUCCESS) {
110 (void) t1394_free_cmd(soft_state->sl_handle, 0, &cmdp);
111 return (-1);
112 }
113
114 if (cmdp->cmd_result != DDI_SUCCESS) {
115 (void) t1394_free_cmd(soft_state->sl_handle, 0, &cmdp);
116 return (-1);
117 }
118
119 (void) t1394_free_cmd(soft_state->sl_handle, 0, &cmdp);
120
121 return (0);
122 }
123