1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _SYS_1394_ADAPTERS_HCI1394_ISOCH_H
28 #define	_SYS_1394_ADAPTERS_HCI1394_ISOCH_H
29 
30 /*
31  * hci1394_isoch.h
32  *    Function declarations for front-end functions for hci1394 isochronous
33  *    support.  Also all isochronous related soft_state structures and defs.
34  */
35 
36 #ifdef	__cplusplus
37 extern "C" {
38 #endif
39 
40 #include <sys/note.h>
41 #include <sys/1394/adapters/hci1394_def.h>
42 
43 
44 /* handle passed back from init() and used for rest of functions */
45 typedef	struct hci1394_isoch_s	*hci1394_isoch_handle_t;
46 
47 /*
48  * Isochronous structures and defs used in the hci1394 soft state.
49  * (see hci1394_state.h).
50  */
51 
52 /*
53  * control structure for allocated isochronous dma descriptor memory.
54  * when attempting to bind memory, if ddi_addr_bind_handle indicates multiple
55  * cookies, each cookie will be tracked within a separate copy of this
56  * structure. Only the last cookie's idma_desc_mem structure will contain
57  * a valid mem_handle and mem, to be used when freeing all the memory.
58  *
59  * 'used' specifies the number of bytes used for descriptors in this cookie.
60  * 'offset' is this cookie's offset relative to the beginning of the buffer.
61  */
62 typedef struct hci1394_idma_desc_mem_s {
63 	struct hci1394_idma_desc_mem_s	*dma_nextp;
64 	hci1394_buf_handle_t		mem_handle;
65 	hci1394_buf_info_t		mem;
66 	uint32_t			used;
67 	uint32_t			offset;
68 } hci1394_idma_desc_mem_t;
69 
70 _NOTE(SCHEME_PROTECTS_DATA("Single thread modifies", hci1394_idma_desc_mem_s))
71 
72 /* structure to track one isochronous context */
73 /* XXX if IR Multichan mode support is added, this must be modified */
74 typedef struct hci1394_iso_ctxt_s {
75 	int	    ctxt_index;		/* 0-31 -- which context this is */
76 	int	    ctxt_io_mode;	/* xmit, recv pkt or buf, hdrs, multi */
77 	uint32_t    ctxt_flags;		/* general context info */
78 	volatile uint32_t    intr_flags; /* flags while context is running */
79 	kmutex_t    intrprocmutex;	/* interrupt/update coordination */
80 	kcondvar_t  intr_cv;		/* interrupt completion cv */
81 	uint16_t    isospd;		/* speed of packets for context */
82 	uint16_t    isochan;		/* isochronous channel for contxt */
83 
84 	hci1394_ctxt_regs_t *ctxt_regsp; /* ctxt regs within hci1394_regs_t */
85 
86 	void	    *xcs_firstp;	/* first alloc xfer_ctl_t struct */
87 	hci1394_idma_desc_mem_t *dma_firstp; /* 1st alloc dma descriptor mem */
88 	uint32_t    dma_mem_execp;	/* exec start(bound mem w/Z bits) */
89 	uint32_t    reserved;
90 
91 	ixl1394_command_t *ixl_firstp;	/* 1st ixl cmmand in linked list */
92 	ixl1394_command_t *ixl_execp;	/* currently executing ixl cmmand */
93 	uint_t	    ixl_exec_depth;	/* curr exec ixl cmd xfer_ctl idx */
94 
95 	uint_t	    max_dma_skips;	/* max skips allowed before xmit */
96 					/* recovery required (16 => 2ms) */
97 	uint_t	    max_noadv_intrs;	/* max intrs with no dma descriptor */
98 					/* block advances (8) */
99 	uint_t	    rem_noadv_intrs;	/* remaining intrs allowed with no */
100 					/* dma advances (i.e. no status set) */
101 
102 	uint16_t    dma_last_time;	/* last completd desc blk tmestmp */
103 
104 	uint16_t    default_tag;	/* default tag value  */
105 	uint16_t    default_sync;	/* default sync value */
106 	uint16_t    default_skipmode;	/* default skip mode  */
107 
108 	ixl1394_command_t *default_skiplabelp; /* set if needed */
109 	ixl1394_command_t *default_skipxferp; /* xfercmd for default skiplabl */
110 
111 	void	    *global_callback_arg;   /* provided to IXLcallbacks */
112 	opaque_t    idma_evt_arg;	    /* provided to "stopped" callback */
113 
114 	/* target callback if dma stops */
115 	void (*isoch_dma_stopped)(struct isoch_dma_handle *idma_hdl,
116 	    opaque_t idma_evt_arg, id1394_isoch_dma_stopped_t idma_stop_args);
117 
118 } hci1394_iso_ctxt_t;
119 
120 _NOTE(SCHEME_PROTECTS_DATA("Single thread modifies", hci1394_iso_ctxt_s))
121 
122 /*
123  * defs for hci1394_iso_ctxt_t.ctxt_io_mode.
124  * overall io characteristics of the contexts, initialized during isoch init
125  * and never changed.
126  */
127 /*
128  * defs for hci1394_iso_ctxt_t.ctxt_flags
129  * These flags are protected by the context list mutex in the isoch handle
130  * (see hci1394_isoch.c for mutex definition)
131  */
132 #define	HCI1394_ISO_CTXT_INUSE	    0x00000001 /* context is in use */
133 #define	HCI1394_ISO_CTXT_RUNNING    0x00000002 /* context is running */
134 #define	HCI1394_ISO_CTXT_RECV	    0x00000004 /* isoch receive context */
135 #define	HCI1394_ISO_CTXT_CMDREG	    0x00000008 /* dev has readable dma cmdptr */
136 #define	HCI1394_ISO_CTXT_BFFILL	    0x00000010 /* on=BufFill off=Pkt IR only */
137 #define	HCI1394_ISO_CTXT_RHDRS	    0x00000020 /* recv packet hdrs into mem */
138 #define	HCI1394_ISO_CTXT_MULTI	    0x00000040 /* in multichan mode - IR only */
139 
140 /*
141  * defs for hci1394_iso_ctxt_t.intr_flags
142  * These flags are protected by the per-context mutex "intrprocmutex"
143  */
144 #define	HCI1394_ISO_CTXT_STOP	    0x00000010 /* context stopped */
145 #define	HCI1394_ISO_CTXT_INTRSET    0x00000020 /* intr flagged, not processed */
146 #define	HCI1394_ISO_CTXT_ININTR	    0x00000040 /* in intrproc, not due to int */
147 #define	HCI1394_ISO_CTXT_INUPDATE   0x00000080 /* in intrproc, not due to int */
148 #define	HCI1394_ISO_CTXT_INCALL	    0x00000100 /* intrproc is doing callback */
149 
150 /*
151  * structure used to do accounting for interrupt usage.  Specifically,
152  * used to determine when CYCLE_LOST or CYCLE_INCONSISTENT storms
153  * should cause us to disable those interrupts.
154  */
155 typedef struct hci1394_intr_thresh_s {
156 	hrtime_t	last_intr_time;
157 	hrtime_t	delta_t_thresh;
158 	int		delta_t_counter;
159 	int		counter_thresh;
160 } hci1394_intr_thresh_t;
161 
162 /* defs for the hci1394_intr_thresh_t struct */
163 #define	HCI1394_CYC_LOST_DELTA		400000;		/* 400ms */
164 #define	HCI1394_CYC_LOST_COUNT		25;
165 #define	HCI1394_CYC_INCON_DELTA		400000;		/* 400ms */
166 #define	HCI1394_CYC_INCON_COUNT		25;
167 
168 /*
169  * Structure used for tracking all transmit and receive isochronous contexts
170  * Also contains the information necessary for tracking CYCLE_LOST and
171  * CYCLE_INCONSISTENT interrupt usage.
172  * The ctxt_list mutex protects the in-use status of the contexts while
173  * searching for a free isoch context to use in hci1394_alloc_isoch_dma(),
174  * during interrupt processing, and during free_isoch_dma processing.
175  * An openHCI 1.0 hardware implementation may support up to 32 separate DMA
176  * engines each for transmit and receive, referred to as "contexts".
177  * The number of supported contexts is determined during ohci board
178  * initialization, and can be different for transmit vs. receive.
179  */
180 typedef struct hci1394_isoch_s {
181 	hci1394_intr_thresh_t	cycle_lost_thresh;
182 	hci1394_intr_thresh_t	cycle_incon_thresh;
183 	int			isoch_dma_alloc_cnt;
184 	int			unused;
185 	int			ctxt_xmit_count;
186 	int			ctxt_recv_count;
187 	hci1394_iso_ctxt_t	ctxt_xmit[HCI1394_MAX_ISOCH_CONTEXTS];
188 	hci1394_iso_ctxt_t	ctxt_recv[HCI1394_MAX_ISOCH_CONTEXTS];
189 	kmutex_t		ctxt_list_mutex;
190 } hci1394_isoch_t;
191 
192 
193 void hci1394_isoch_init(hci1394_drvinfo_t *drvinfo,  hci1394_ohci_handle_t ohci,
194     hci1394_isoch_handle_t *isoch_hdl);
195 void hci1394_isoch_fini(hci1394_isoch_handle_t *isoch_hdl);
196 void hci1394_isoch_cycle_inconsistent(hci1394_state_t *soft_statep);
197 void hci1394_isoch_cycle_lost(hci1394_state_t *soft_statep);
198 int hci1394_isoch_resume(hci1394_state_t *soft_statep);
199 void hci1394_isoch_error_ints_enable(hci1394_state_t *soft_statep);
200 
201 int hci1394_isoch_recv_count_get(hci1394_isoch_handle_t isoch_hdl);
202 hci1394_iso_ctxt_t *hci1394_isoch_recv_ctxt_get(hci1394_isoch_handle_t
203     isoch_hdl, int num);
204 int hci1394_isoch_xmit_count_get(hci1394_isoch_handle_t isoch_hdl);
205 hci1394_iso_ctxt_t *hci1394_isoch_xmit_ctxt_get(hci1394_isoch_handle_t
206     isoch_hdl, int num);
207 
208 
209 int hci1394_alloc_isoch_dma(void *hal_private, id1394_isoch_dmainfo_t *idi,
210     void **hal_idma_handle, int	*resultp);
211 void hci1394_free_isoch_dma(void *hal_private, void *hal_isoch_dma_handle);
212 int hci1394_start_isoch_dma(void *hal_private, void *hal_isoch_dma_handle,
213     id1394_isoch_dma_ctrlinfo_t *idma_ctrlinfo, uint_t flags, int *resultp);
214 int hci1394_update_isoch_dma(void *hal_private, void *hal_isoch_dma_handle,
215     id1394_isoch_dma_updateinfo_t *idma_updateinfop, uint_t flags,
216     int *resultp);
217 void hci1394_stop_isoch_dma(void *hal_private, void *hal_isoch_dma_handle,
218     int *resultp);
219 void hci1394_do_stop(hci1394_state_t *soft_statep, hci1394_iso_ctxt_t *ctxtp,
220     boolean_t do_callback, id1394_isoch_dma_stopped_t stop_args);
221 
222 #ifdef	__cplusplus
223 }
224 #endif
225 
226 #endif	/* _SYS_1394_ADAPTERS_HCI1394_ISOCH_H */
227