xref: /illumos-gate/usr/src/uts/common/sys/1394/h1394.h (revision 2d6eb4a5)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 1999-2002 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_SYS_1394_H1394_H
28 #define	_SYS_1394_H1394_H
29 
30 /*
31  * h1394.h
32  *    Contains the structure and error codes used to communicate
33  *    between the HAL and the rest of the 1394 Software Framework
34  */
35 
36 #include <sys/types.h>
37 #include <sys/modctl.h>
38 #include <sys/ddi.h>
39 #include <sys/sunddi.h>
40 #include <sys/note.h>
41 
42 #include <sys/1394/cmd1394.h>
43 #include <sys/1394/id1394.h>
44 
45 #ifdef	__cplusplus
46 extern "C" {
47 #endif
48 
49 #define	H1394_CLEANUP_LEVEL7	7
50 #define	H1394_CLEANUP_LEVEL6	6
51 #define	H1394_CLEANUP_LEVEL5	5
52 #define	H1394_CLEANUP_LEVEL4	4
53 #define	H1394_CLEANUP_LEVEL3	3
54 #define	H1394_CLEANUP_LEVEL2	2
55 #define	H1394_CLEANUP_LEVEL1	1
56 #define	H1394_CLEANUP_LEVEL0	0
57 
58 /* h1394_phy_t */
59 typedef enum {
60 	H1394_PHY_1995	= 0,
61 	H1394_PHY_1394A	= 1
62 } h1394_phy_t;
63 
64 /* h1394_error_t */
65 typedef enum {
66 	H1394_LOCK_RESP_ERR		= 1,
67 	H1394_POSTED_WR_ERR		= 2,
68 	H1394_SELF_INITIATED_SHUTDOWN	= 3,
69 	H1394_CYCLE_TOO_LONG		= 4
70 } h1394_error_t;
71 
72 /*
73  * h1394_posted_wr_err_t
74  *    The upper 16 bits contain the source id (bus/node) of the source node,
75  *    the lower 48 bits contain the address that the error occured at.
76  */
77 typedef struct h1394_posted_wr_err_s {
78 	uint64_t	addr;
79 } h1394_posted_wr_err_t;
80 
81 /*
82  * h1394_node_pwr_flags_t
83  *    Node power flags info
84  */
85 typedef enum {
86 	H1394_NODE_PWR_FLAGS_NONE	= (1 << 1),
87 	H1394_BUS_PWRD_NODES_ONE_MORE	= (1 << 2),
88 	H1394_BUS_PWRD_NODES_ONE_LESS	= (1 << 3),
89 	H1394_ACTIVE_NODES_ONE_MORE	= (1 << 4),
90 	H1394_ACTIVE_NODES_ONE_LESS	= (1 << 5)
91 } h1394_node_pwr_flags_t;
92 
93 /*
94  * h1394_addr_type_t
95  *    h1394_addr_map.addr_type
96  */
97 typedef enum {
98 	H1394_ADDR_POSTED_WRITE	= 0,
99 	H1394_ADDR_NORMAL	= 1,
100 	H1394_ADDR_CSR		= 2,
101 	H1394_ADDR_PHYSICAL	= 3,
102 	H1394_ADDR_RESERVED	= 4
103 } h1394_addr_type_t;
104 
105 /* h1394_mblk_t */
106 typedef struct h1394_mblk_s {
107 	mblk_t		*curr_mblk;
108 	unsigned char	*curr_offset;
109 	uint_t		length;
110 	mblk_t		*next_mblk;
111 	unsigned char	*next_offset;
112 } h1394_mblk_t;
113 
114 /* h1394_cmd_priv_t */
115 typedef struct h1394_cmd_priv_s {
116 	uint_t		speed;
117 	uint_t		ack_tstamp;
118 	uint_t		recv_tstamp;
119 	uint_t		bus_generation;
120 	h1394_mblk_t	mblk;
121 	void		*hal_overhead;
122 } h1394_cmd_priv_t;
123 
124 _NOTE(SCHEME_PROTECTS_DATA("Used by a single thread", h1394_cmd_priv_s \
125 	h1394_mblk_s::next_mblk h1394_mblk_s::next_offset))
126 
127 /* h1394_evts_t */
128 typedef struct h1394_evts_s {
129 	uint_t	hal_version;
130 	uint_t	reserved;
131 	void	(*shutdown)(void *hal_private);
132 	int	(*send_phy_configuration_packet)(void *hal_private,
133 		    cmd1394_cmd_t *phy_pkt, h1394_cmd_priv_t *cmd_private,
134 		    int *result);
135 	int	(*read)(void *hal_private, cmd1394_cmd_t *req,
136 		    h1394_cmd_priv_t *cmd_private, int *result);
137 	int	(*read_response)(void *hal_private, cmd1394_cmd_t *resp,
138 		    h1394_cmd_priv_t *cmd_private, int *result);
139 	int	(*write)(void *hal_private, cmd1394_cmd_t *req,
140 		    h1394_cmd_priv_t *cmd_private, int *result);
141 	int	(*write_response)(void *hal_private, cmd1394_cmd_t *resp,
142 		    h1394_cmd_priv_t *cmd_private, int *result);
143 	void	(*response_complete)(void *hal_private, cmd1394_cmd_t *resp,
144 		    h1394_cmd_priv_t *cmd_private);
145 	int	(*lock)(void *hal_private, cmd1394_cmd_t *req,
146 		    h1394_cmd_priv_t *cmd_private, int *result);
147 	int	(*lock_response)(void *hal_private, cmd1394_cmd_t *resp,
148 		    h1394_cmd_priv_t *cmd_private, int *result);
149 	int	(*alloc_isoch_dma)(void *hal_private,
150 		    id1394_isoch_dmainfo_t *idi, void **hal_idma_handle,
151 		    int *result);
152 	void	(*free_isoch_dma)(void *hal_private,
153 		    void *hal_isoch_dma_handle);
154 	int	(*start_isoch_dma)(void *hal_private,
155 		    void *hal_isoch_dma_handle,
156 		    id1394_isoch_dma_ctrlinfo_t *idma_ctrlinfo, uint_t flags,
157 		    int *result);
158 	void	(*stop_isoch_dma)(void *hal_private, void *hal_isoch_dma_handle,
159 		    int *result);
160 	int	(*update_isoch_dma)(void *hal_private,
161 		    void *hal_isoch_dma_handle,
162 		    id1394_isoch_dma_updateinfo_t *idma_updateinfo,
163 		    uint_t flags, int *result);
164 	int	(*update_config_rom)(void *hal_private, void *local_buf,
165 		    uint_t quadlet_count);
166 	int	(*bus_reset)(void *hal_private);
167 	int	(*short_bus_reset)(void *hal_private);
168 	int	(*set_contender_bit)(void *hal_private);
169 	int	(*set_root_holdoff_bit)(void *hal_private);
170 	int	(*set_gap_count)(void *hal_private, uint_t gap_count);
171 	int	(*csr_read)(void *hal_private, uint_t offset, uint32_t *data);
172 	int	(*csr_write)(void *hal_private, uint_t offset, uint32_t data);
173 	int	(*csr_cswap32)(void *hal_private, uint_t generation,
174 		    uint_t offset, uint32_t compare, uint32_t swap,
175 		    uint32_t *old);
176 	int	(*physical_arreq_enable_set)(void *hal_private, uint64_t mask,
177 		    uint_t generation);
178 	int	(*physical_arreq_enable_clr)(void *hal_private, uint64_t mask,
179 		    uint_t generation);
180 	void	(*node_power_state_change)(void *hal_private,
181 		    h1394_node_pwr_flags_t nodeflags);
182 } h1394_evts_t;
183 /* Version value for h1394_evts_t */
184 #define	H1394_EVTS_V1			1
185 
186 #define	HAL_CALL(hal)			(hal)->halinfo.hal_events
187 
188 /* Result field returned by read/write/lock requests */
189 #define	H1394_STATUS_NO_ERROR		0
190 #define	H1394_STATUS_INVALID_BUSGEN	1
191 #define	H1394_STATUS_EMPTY_TLABEL	2
192 #define	H1394_STATUS_NOMORE_SPACE	3
193 #define	H1394_STATUS_INTERNAL_ERROR	4
194 
195 /* h1394_addr_map_t */
196 typedef struct h1394_addr_map_s {
197 	uint64_t		address;
198 	uint64_t		length;
199 	h1394_addr_type_t	addr_type;
200 } h1394_addr_map_t;
201 
202 /* h1394_halinfo_t */
203 typedef struct h1394_halinfo_s {
204 	void			*hal_private;
205 	dev_info_t		*dip;
206 	h1394_evts_t		hal_events;
207 	ddi_iblock_cookie_t	hw_interrupt;
208 
209 	/* Buffer attributes */
210 	ddi_device_acc_attr_t	acc_attr;
211 	ddi_dma_attr_t		dma_attr;
212 
213 	/* Type of PHY on HAL */
214 	h1394_phy_t		phy;
215 
216 	uint_t			hal_overhead; /* in bytes */
217 	uint32_t   		bus_capabilities;
218 	uint64_t		guid;
219 	uint32_t		node_capabilities;
220 
221 	/*
222 	 * The maximum value generation can have before
223 	 * it rolls over (inclusive)
224 	 */
225 	uint_t			max_generation;
226 
227 	/* Description of the 1394 Address Space */
228 	h1394_addr_map_t	*addr_map;
229 	uint_t			addr_map_num_entries;
230 
231 	/* Description of the reserved spaces */
232 	h1394_addr_map_t	*resv_map;
233 	uint_t			resv_map_num_entries;
234 } h1394_halinfo_t;
235 
236 
237 /* Calls to Services layer during HAL driver _init() and _fini() */
238 int h1394_init(struct modlinkage  *modlp);
239 void h1394_fini(struct modlinkage  *modlp);
240 
241 
242 /* Calls to Services layer during HAL driver attach/detach */
243 int h1394_attach(h1394_halinfo_t *halinfo, ddi_attach_cmd_t cmd,
244     void **sl_private);
245 
246 int h1394_detach(void **sl_private, ddi_detach_cmd_t cmd);
247 
248 
249 /* Calls to Services layer during HW interrupt processing */
250 void h1394_cmd_is_complete(void *sl_private, cmd1394_cmd_t *command_id,
251     uint32_t cmd_type, int status);
252 /* Command types (passed to h1394_command_is_complete) */
253 #define	H1394_AT_REQ		0
254 #define	H1394_AT_RESP		1
255 /* Command statuses (passed to h1394_command_is_complete) */
256 #define	H1394_CMD_SUCCESS		0x00	/* ack_complete */
257 #define	H1394_CMD_ETIMEOUT		0x01	/* evt_missing_ack */
258 #define	H1394_CMD_EBUSRESET		0x02	/* evt_flushed */
259 #define	H1394_CMD_EDEVICE_BUSY		0x03	/* ack_busy_? */
260 #define	H1394_CMD_EDATA_ERROR		0x04	/* ack_data_error */
261 #define	H1394_CMD_ETYPE_ERROR		0x05	/* ack_type_error */
262 #define	H1394_CMD_EADDR_ERROR		0x06	/* resp_address_error */
263 #define	H1394_CMD_ERSRC_CONFLICT	0x07	/* resp_conflict_error */
264 #define	H1394_CMD_EDEVICE_POWERUP	0x08	/* ack_tardy */
265 #define	H1394_CMD_EDEVICE_ERROR		0x09	/* device error */
266 #define	H1394_CMD_EUNKNOWN_ERROR	0x0A	/* unknown error type */
267 
268 void h1394_bus_reset(void *sl_private, void **selfid_buf_addr);
269 
270 void h1394_self_ids(void *sl_private, void *selfid_buf_addr,
271     uint32_t selfid_size, uint32_t node_id, uint32_t generation_count);
272 
273 void h1394_write_request(void *sl_private, cmd1394_cmd_t *req);
274 
275 void h1394_read_request(void *sl_private, cmd1394_cmd_t *req);
276 
277 void h1394_lock_request(void *sl_private, cmd1394_cmd_t *req);
278 
279 int h1394_alloc_cmd(void *sl_private, uint_t flags, cmd1394_cmd_t **cmdp,
280     h1394_cmd_priv_t **hal_priv_ptr);
281 /* Flags for h1394_alloc_cmd() */
282 #define	H1394_ALLOC_CMD_SLEEP		0x00000000 /* can sleep allocating */
283 #define	H1394_ALLOC_CMD_NOSLEEP		0x00000001 /* don't sleep allocating */
284 
285 int h1394_free_cmd(void *sl_private, cmd1394_cmd_t **cmdp);
286 int h1394_ioctl(void *sl_private, int cmd, intptr_t arg, int mode,
287     cred_t *cred_p, int *rval_p);
288 
289 void h1394_phy_packet(void *sl_private, uint32_t *packet_data,
290     uint_t quadlet_count, uint_t timestamp);
291 
292 void h1394_error_detected(void *sl_private, h1394_error_t type, void *arg);
293 
294 #ifdef __cplusplus
295 }
296 #endif
297 
298 #endif	/* _SYS_1394_H1394_H */
299