xref: /illumos-gate/usr/src/uts/common/io/chxge/ch.h (revision 2d6eb4a5)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 /*
28  * This file is part of the Chelsio T1 Ethernet driver.
29  *
30  * Copyright (C) 2003-2005 Chelsio Communications.  All rights reserved.
31  */
32 
33 #ifndef _CHELSIO_CH_H
34 #define	_CHELSIO_CH_H
35 
36 #include <sys/debug.h>
37 
38 #ifdef __cplusplus
39 extern "C" {
40 #endif
41 
42 /*
43  * Definitions for module_info
44  */
45 
46 #define	CHIDNUM		(666)		/* module ID number */
47 #define	CHNAME		"chxge"		/* module name */
48 #define	CHMINPSZ	(0)		/* min packet size */
49 #define	CHMAXPSZ	ETHERMTU	/* max packet size */
50 #define	CHHIWAT		(32 * 1024)	/* hi-water mark */
51 #define	CHLOWAT		(1)		/* lo-water mark */
52 
53 #define	CH_NO_HWCKSUM	0x1	/* hardware should no add checksum */
54 #define	CH_NO_CPL	0x2	/* no cpl header with data */
55 #define	CH_OFFLOAD	0x4	/* do TCP/IP offload processing */
56 #define	CH_ARP		0x8	/* dummy arp packet (don't free) */
57 #define	CH_TCP_MF	0x10	/* Indicator of Fragmented TCP */
58 #define	CH_UDP_MF	0x20	/* Indicator of Fragmented UDP */
59 #define	CH_UDP		0x40	/* Indicator of regular TCP */
60 
61 #define	SZ_INUSE	64	/* # of in use counters */
62 
63 /*
64  * PCI registers
65  */
66 #define	BAR0 1
67 #define	BAR1 2
68 #define	BAR2 3
69 #define	BAR3 4
70 
71 #ifdef CONFIG_CHELSIO_T1_OFFLOAD
72 /*
73  * TOE pre-mapped buffer structure
74  */
75 typedef struct tbuf {
76 	struct tbuf	*tb_next;	/* next entry in free list */
77 	caddr_t		tb_base;	/* base of buffer */
78 	uint64_t	tb_pa;		/* physical address of buffer */
79 	ulong_t		tb_dh;		/* dma handle */
80 	ulong_t		tb_ah;		/* dma address handle */
81 	void		*tb_sa;		/* address of card ctrl struct */
82 	uint32_t	tb_debug;	/* initally 0 */
83 	uint32_t	tb_len;		/* length of data */
84 } tbuf_t;
85 #endif	/* CONFIG_CHELSIO_T1_OFFLOAD */
86 
87 /*
88  * header structures to hold pre-mapped (DMA) kernel memory buffers.
89  */
90 typedef struct ch_esb {
91 	struct ch_esb   *cs_next;	/* next entry in list */
92 	struct ch_esb   *cs_owner;	/* list of buffers owned by ch_t */
93 	void		*cs_sa;		/* card structure to get ch ptr */
94 	ulong_t		cs_dh;		/* dma handle */
95 	ulong_t		cs_ah;		/* dma address handle */
96 	caddr_t		cs_buf;		/* vaddr of buffer */
97 	uint64_t	cs_pa;		/* paddr of buffer */
98 	uint32_t	cs_index;	/* index of buffer_in_use count */
99 	uint32_t	cs_flag;	/* if set, commit suicide */
100 #ifdef FRAGMENT				/* we assume no fragments */
101 	ddi_dma_cookie_t cs_cookie[MAXFS];
102 	uint_t		cs_ncookie;
103 #endif
104 	frtn_t		cs_frtn;	/* for esballoc */
105 } ch_esb_t;
106 
107 /*
108  * structure for linked list of multicast addresses that have been
109  * assigned to the card.
110  */
111 typedef struct ch_mc {
112 	struct ch_mc *cmc_next;
113 	uint8_t cmc_mca[6];
114 } ch_mc_t;
115 
116 /*
117  * structure for linked list of pre-allocated dma handles for command Q
118  */
119 typedef struct free_dh {
120 	struct free_dh *dhe_next;
121 	ulong_t dhe_dh;
122 } free_dh_t;
123 
124 /*
125  * instance configuration
126  */
127 typedef struct ch_cfg {
128 	uint32_t cksum_enabled: 1;
129 	uint32_t burstsize_set: 1;
130 	uint32_t burstsize: 2;
131 	uint32_t transaction_cnt_set: 1;
132 	uint32_t transaction_cnt: 3;
133 	uint32_t relaxed_ordering: 1;
134 	uint32_t enable_dvma: 1;
135 } ch_cfg_t;
136 
137 /*
138  * Per-card state information
139  */
140 typedef struct ch {
141 	dev_info_t	*ch_dip;	/* device dev info */
142 	gld_mac_info_t	*ch_macp;	/* gld mac structure */
143 
144 	ch_cfg_t	ch_config;	/* instance configuration */
145 	uint_t		ch_flags;	/* state flags */
146 	uint_t		ch_state;	/* card state */
147 	uint_t		ch_blked;	/* card is blked on output */
148 	kmutex_t	ch_lock;	/* lock for ch structure */
149 
150 	caddr_t		ch_pci;		/* PCI configuration vaddr */
151 	ddi_acc_handle_t ch_hpci;	/* PCI configuration access handle */
152 	off_t		ch_pcisz;	/* size of PCI configuration space */
153 
154 	caddr_t		ch_bar0;	/* PCI BAR0 vaddr */
155 	ddi_acc_handle_t ch_hbar0;	/* PCI BAR0 access handle */
156 	off_t		ch_bar0sz;	/* size of BAR0 space */
157 
158 	ddi_iblock_cookie_t ch_icookp; /* hardware interrupt cookie ptr */
159 	kmutex_t	ch_intr;	/* lock for interrupts */
160 
161 	uint32_t	ch_maximum_mtu;	/* maximum mtu for adapter */
162 
163 	uint32_t	ch_sm_buf_sz;	/* size of sm esballoc bufs */
164 	uint32_t	ch_sm_buf_aln;	/* alignment of sm esballoc bufs */
165 	ch_esb_t	*ch_small_esb_free; /* free list sm esballoc bufs */
166 	ch_esb_t	*ch_small_owner; /* list small bufs owned by ch_t */
167 	kmutex_t	ch_small_esbl;	/* lock for ch_small_esb list */
168 	uint_t		ch_sm_index;	/* small buffer in use count index */
169 
170 	uint32_t	ch_bg_buf_sz;	/* size of bg esballoc bufs */
171 	uint32_t	ch_bg_buf_aln;	/* alignment of bg esballoc bufs */
172 	ch_esb_t	*ch_big_esb_free; /* free list of esballoc entries */
173 	ch_esb_t	*ch_big_owner;	/* list big bufs owned by ch_t */
174 	kmutex_t	ch_big_esbl;	/* lock for ch_esb list */
175 	uint_t		ch_big_index;	/* big buffer in use count index */
176 
177 	kmutex_t	ch_mc_lck;	/* lock of mulitcast list */
178 	ch_mc_t		*ch_mc;		/* list of multicast entries */
179 	uint32_t	ch_mc_cnt;	/* cnt of multicast entries */
180 
181 	/* XXX see how we can use cmdQ_ce list and get rid of lock */
182 	kmutex_t	ch_dh_lck;	/* lock for ch_dh list */
183 	free_dh_t	*ch_dh;		/* list of free dma headers for v2p */
184 
185 #if defined(__sparc)
186 	/* XXX see how we can use cmdQ_ce list and get rid of lock */
187 	free_dh_t	*ch_vdh;	/* list of free dvma headers for v2p */
188 #endif
189 
190 	uint32_t	ch_ip;		/* ip address from first arp */
191 
192 	uint32_t	ch_mtu;		/* size of device MTU (1500 default) */
193 
194 	/* XXX config_data needs cleanup */
195 	pe_config_data_t config_data;	/* card configuration vector */
196 
197 	struct pe_port_t port[4];	/* from freebsd/oschtoe.h driver */
198 	pesge		*sge;
199 	struct pemc3	*mc3;
200 	struct pemc4	*mc4;
201 	struct pemc5	*mc5;
202 	struct petp	*tp;
203 	struct pecspi	*cspi;
204 	struct peespi	*espi;
205 	struct peulp	*ulp;
206 #ifdef CONFIG_CHELSIO_T1_OFFLOAD
207 	uint32_t	open_device_map;
208 #endif
209 	struct adapter_params params;
210 	uint16_t	vendor_id;
211 	uint16_t	device_id;
212 	uint16_t	device_subid;
213 	uint16_t	chip_revision;
214 	uint16_t	chip_version;
215 	uint32_t	is_asic;
216 	uint32_t	config;
217 	uint32_t	ch_unit;
218 	uint8_t		init_counter;
219 	char		*ch_name;
220 	/* statistics per card */
221 	uint32_t	isr_intr;	/* # interrupts */
222 	uint32_t	oerr;		/* send error (no mem) */
223 	uint32_t	norcvbuf;
224 #ifdef CONFIG_CHELSIO_T1_OFFLOAD
225 	int		ch_refcnt;
226 	void		*ch_toeinst;
227 	void		(*toe_rcv)(void *, mblk_t *);
228 	void		(*toe_free)(void *, tbuf_t *);
229 	int		(*toe_tunnel)(void *, mblk_t *);
230 	kcondvar_t	*ch_tx_overflow_cv;
231 	kmutex_t	*ch_tx_overflow_mutex;
232 #endif
233 	uint32_t	slow_intr_mask;
234 #ifdef HOST_PAUSE
235 	uint32_t	txxg_cfg1;	/* Place holder for MAC cfg reg1. */
236 	int		pause_on;
237 	hrtime_t	pause_time;
238 #endif
239 	kmutex_t	mac_lock;	/* lock for MAC structure */
240 } ch_t;
241 
242 /* ch_flags */
243 #define	PEIDLE		0x00	/* chip is uninitialized */
244 #define	PERUNNING	0x01	/* chip is initialized */
245 #define	PEPROMISC	0x04	/* promiscuous mode enabled */
246 #define	PEALLMULTI	0x08	/* all multicast enabled */
247 #define	PESUSPENDED	0x20	/* suspended interface */
248 #define	PENORES		0x40	/* ran out of xmit resources */
249 #define	PESTOP		0x80	/* gldm_stop done */
250 #define	PEINITDONE	0x100	/* initialization done */
251 #define	TSO_CAPABLE	0x200	/* TSO able */
252 
253 #ifdef CONFIG_CHELSIO_T1_OFFLOAD
254 /* open_device_map flag */
255 #define	TOEDEV_DEVMAP_BIT 0x1
256 #endif
257 
258 /*
259  * DMA mapping defines
260  */
261 #define	DMA_STREAM 1	/* use DDI_DMA_STREAMING for DMA xfers */
262 #define	DMA_4KALN  2	/* align memory to 4K page boundry */
263 #define	DMA_OUT    4	/* this is a write buffer */
264 #define	DMA_SMALN  8	/* aligned at small buffer boundry */
265 #define	DMA_BGALN  16	/* aligned at big buffer boundry */
266 
267 /*
268  * Number of multicast addresses per stream
269  */
270 #define	CHMAXMC   64
271 #define	CHMCALLOC (CHMAXMC * sizeof (struct ether_addr))
272 
273 /* ----- Solaris memory - PCI - DMA mapping functions ------ */
274 
275 void *ch_alloc_dma_mem(ch_t *, int, int, int, uint64_t *, ulong_t *, ulong_t *);
276 void ch_free_dma_mem(ulong_t, ulong_t);
277 void ch_unbind_dma_handle(ch_t *, free_dh_t *);
278 
279 void ch_send_up(ch_t *, mblk_t *, uint32_t, int);
280 
281 void ch_gld_ok(ch_t *);
282 
283 uint32_t t1_read_reg_4(ch_t *obj, uint32_t reg_val);
284 void t1_write_reg_4(ch_t *obj, uint32_t reg_val, uint32_t write_val);
285 uint32_t t1_os_pci_read_config_2(ch_t *obj, uint32_t reg, uint16_t *val);
286 uint32_t t1_os_pci_read_config_4(ch_t *obj, uint32_t reg, uint32_t *val);
287 int t1_os_pci_write_config_2(ch_t *obj, uint32_t reg, uint16_t val);
288 int t1_os_pci_write_config_4(ch_t *obj, uint32_t reg, uint32_t val);
289 uint32_t le32_to_cpu(uint32_t data);
290 
291 void *t1_os_malloc_wait_zero(size_t len);
292 void t1_os_free(void *adr, size_t len);
293 int t1_num_of_ports(ch_t *obj);
294 int pe_os_mem_copy(ch_t *obj, void *dst, void *src, size_t len);
295 void *pe_os_malloc_contig_wait_zero(ch_t *, size_t, uint64_t *,
296     ulong_t *, ulong_t *, uint32_t);
297 void pe_set_mac(ch_t *sa, unsigned char *ac_enaddr);
298 unsigned char *pe_get_mac(ch_t *sa);
299 void pe_set_promiscuous(ch_t *sa, int flag);
300 int pe_get_stats(ch_t *sa, uint64_t *speed, uint32_t *intrcnt,
301     uint32_t *norcvbuf, uint32_t *oerrors, uint32_t *ierrors,
302     uint32_t *underrun, uint32_t *overrun, uint32_t *framing,
303     uint32_t *crc, uint32_t *carrier, uint32_t *collisions,
304     uint32_t *xcollisions, uint32_t *late, uint32_t *defer,
305     uint32_t *xerrs, uint32_t *rerrs, uint32_t *toolong, uint32_t *runt,
306     ulong_t *multixmt, ulong_t *multircv, ulong_t *brdcstxmt,
307     ulong_t *brdcstrcv);
308 int pe_attach(ch_t *);
309 void pe_detach(ch_t *);
310 void pe_init(void *);
311 uint_t pe_intr(ch_t *);
312 
313 #ifdef CONFIG_CHELSIO_T1_OFFLOAD
314 #define	toe_running(a) (a->open_device_map & TOEDEV_DEVMAP_BIT)
315 #endif
316 
317 int pe_start(ch_t *sa, mblk_t *mb, uint32_t flg);
318 void pe_stop(ch_t *sa);
319 void pe_ioctl(ch_t *, queue_t *, mblk_t *);
320 int pe_set_mc(ch_t *, uint8_t *, int);
321 
322 int tpi_read(ch_t *obj, u32 addr, u32 *value);
323 
324 void CH_ALERT(const char *fmt, ...);
325 void CH_WARN(const char *fmt, ...);
326 void CH_ERR(const char *fmt, ...);
327 void t1_fatal_err(ch_t *chp);
328 
329 #define	memset(s, c, n) bzero(s, n)
330 
331 extern int enable_checksum_offload;
332 
333 void pe_dma_handle_init(ch_t *, int);
334 free_dh_t *ch_get_dma_handle(ch_t *);
335 
336 void pe_free_fake_arp(void *);
337 
338 void pe_mark_freelists(ch_t *chp);
339 
340 #if defined(__sparc)
341 free_dh_t *ch_get_dvma_handle(ch_t *);
342 void ch_unbind_dvma_handle(ch_t *, free_dh_t *);
343 #endif
344 
345 #define	AMD_VENDOR_ID	0x1022
346 #define	AMD_BRIDGE	0x7450
347 #define	AMD_BRIDGE_REV	0x12
348 
349 #ifdef __cplusplus
350 }
351 #endif
352 
353 #endif	/* _CHELSIO_CH_H */
354