1 /*
2  * Copyright (c) 2014 Martin Pieuchot. All rights reserved.
3  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
4  * Copyright (c) 2018, Joyent, Inc.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 #ifndef _SYS_USB_HCD_XHCI_XHCIREG_H
29 #define	_SYS_USB_HCD_XHCI_XHCIREG_H
30 
31 /*
32  * xHCI Register and Field Definitions
33  */
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
39 /*
40  * xHCI PCI config registers
41  */
42 #define	PCI_XHCI_CBMEM		0x10	/* configuration base MEM */
43 #define	PCI_XHCI_USBREV		0x60	/* RO USB protocol revision */
44 #define	PCI_USB_REV_3_0		0x30	/* USB 3.0 */
45 #define	PCI_XHCI_FLADJ		0x61	/* RW frame length adjust */
46 
47 #define	PCI_XHCI_INTEL_XUSB2PR	0xD0	/* Intel USB2 Port Routing */
48 #define	PCI_XHCI_INTEL_USB2PRM	0xD4	/* Intel USB2 Port Routing Mask */
49 #define	PCI_XHCI_INTEL_USB3_PSSEN 0xD8	/* Intel USB3 Port SuperSpeed Enable */
50 #define	PCI_XHCI_INTEL_USB3PRM	0xDC	/* Intel USB3 Port Routing Mask */
51 
52 /*
53  * xHCI capability registers
54  */
55 #define	XHCI_CAPLENGTH		0x00	/* RO capability */
56 #define	XHCI_RESERVED		0x01	/* Reserved */
57 #define	XHCI_HCIVERSION		0x02	/* RO Interface version number */
58 #define	XHCI_HCIVERSION_0_9	0x0090	/* xHCI version 0.9 */
59 #define	XHCI_HCIVERSION_1_0	0x0100	/* xHCI version 1.0 */
60 
61 #define	XHCI_VERSION_MASK(x)	(((x) >> 16) & 0xffff)
62 
63 /*
64  * Structural Parameters 1 - xHCI 1.1 / 5.3.3
65  */
66 #define	XHCI_HCSPARAMS1		0x04
67 #define	XHCI_HCS1_DEVSLOT_MAX(x)	((x) & 0xFF)
68 #define	XHCI_HCS1_IRQ_MAX(x)	(((x) >> 8) & 0x3FF)
69 #define	XHCI_HCS1_N_PORTS(x)	(((x) >> 24) & 0xFF)
70 
71 /*
72  * Structural Parameters 2 - xHCI 1.1 / 5.3.4
73  */
74 #define	XHCI_HCSPARAMS2		0x08
75 #define	XHCI_HCS2_IST(x)	((x) & 0x7)
76 #define	XHCI_HCS2_IST_MICRO(x)	(!((x) & 0x8))
77 #define	XHCI_HCS2_ERST_MAX(x)	(((x) >> 4) & 0xF)
78 #define	XHCI_HCS2_SPR(x)	(((x) >> 24) & 0x1)
79 #define	XHCI_HCS2_SPB_MAX(x)	((((x) >> 16) & 0x3e0) | (((x) >> 27) & 0x1f))
80 
81 /*
82  * Structural Parameters 3 - xHCI 1.1 / 5.3.5
83  */
84 #define	XHCI_HCSPARAMS3		0x0C
85 #define	XHCI_HCS3_U1_DEL(x)	((x) & 0xFF)
86 #define	XHCI_HCS3_U2_DEL(x)	(((x) >> 16) & 0xFFFF)
87 
88 /*
89  * Capability Parameters 1 - xHCI 1.1 / 5.3.6
90  */
91 #define	XHCI_HCCPARAMS1		0x10
92 #define	XHCI_HCC1_FLAGS_MASK(x)	((x) & 0x7FF)
93 #define	XHCI_HCC1_PSA_SZ_MAX(x)	(((x) >> 12) & 0xF)
94 #define	XHCI_HCC1_XECP(x)	(((x) >> 16) & 0xFFFF)
95 
96 /*
97  * Capability Parameters 1 - xHCI 1.1 / 5.3.9
98  */
99 #define	XHCI_HCCPARAMS2		0x1C
100 #define	XHCI_HCC2_FLAGS_MASK(x)	((x) & 0x3F)
101 
102 #define	XHCI_DBOFF		0x14	/* RO doorbell offset */
103 #define	XHCI_RTSOFF		0x18	/* RO runtime register space offset */
104 
105 /*
106  * xHCI operational registers.
107  * Offset given by XHCI_CAPLENGTH register
108  */
109 #define	XHCI_USBCMD		0x00		/* XHCI command */
110 #define	XHCI_CMD_RS		0x00000001	/* RW Run/Stop */
111 #define	XHCI_CMD_HCRST		0x00000002	/* RW HC Reset */
112 #define	XHCI_CMD_INTE		0x00000004	/* RW Interrupter Enable */
113 #define	XHCI_CMD_HSEE		0x00000008	/* RW System Error Enable */
114 #define	XHCI_CMD_LHCRST		0x00000080	/* RW Light HC Reset */
115 #define	XHCI_CMD_CSS		0x00000100	/* RW Controller Save */
116 #define	XHCI_CMD_CRS		0x00000200	/* RW Controller Restore */
117 #define	XHCI_CMD_EWE		0x00000400	/* RW Enable Wrap Event */
118 #define	XHCI_CMD_EU3S		0x00000800	/* RW Enable U3 MFINDEX Stop */
119 
120 
121 #define	XHCI_USBSTS		0x04		/* XHCI status */
122 #define	XHCI_STS_HCH		0x00000001	/* RO - HC Halted */
123 #define	XHCI_STS_HSE		0x00000004	/* RW - Host System Error */
124 #define	XHCI_STS_EINT		0x00000008	/* RW - Event Interrupt */
125 #define	XHCI_STS_PCD		0x00000010	/* RW - Port Change Detect */
126 #define	XHCI_STS_SSS		0x00000100	/* RO - Save State Status */
127 #define	XHCI_STS_RSS		0x00000200	/* RO - Restore State Status */
128 #define	XHCI_STS_SRE		0x00000400	/* RW - Save/Restore Error */
129 #define	XHCI_STS_CNR		0x00000800	/* RO - Controller Not Ready */
130 #define	XHCI_STS_HCE		0x00001000	/* RO - HC Error */
131 
132 #define	XHCI_PAGESIZE		0x08		/* XHCI page size mask */
133 #define	XHCI_PAGESIZE_4K	0x00000001	/* 4K Page Size */
134 #define	XHCI_PAGESIZE_8K	0x00000002	/* 8K Page Size */
135 #define	XHCI_PAGESIZE_16K	0x00000004	/* 16K Page Size */
136 #define	XHCI_PAGESIZE_32K	0x00000008	/* 32K Page Size */
137 #define	XHCI_PAGESIZE_64K	0x00000010	/* 64K Page Size */
138 
139 #define	XHCI_DNCTRL		0x14	/* XHCI device notification control */
140 #define	XHCI_DNCTRL_MASK(n)	(1U << (n))
141 
142 #define	XHCI_CRCR		0x18		/* XHCI command ring control */
143 #define	XHCI_CRCR_RCS		0x00000001	/* RW - consumer cycle state */
144 #define	XHCI_CRCR_CS		0x00000002	/* RW - command stop */
145 #define	XHCI_CRCR_CA		0x00000004	/* RW - command abort */
146 #define	XHCI_CRCR_CRR		0x00000008	/* RW - command ring running */
147 #define	XHCI_CRCR_MASK		0x0000000F
148 
149 /*
150  * Device context base address pointer register.
151  */
152 #define	XHCI_DCBAAP		0x30
153 
154 #define	XHCI_CONFIG		0x38
155 #define	XHCI_CONFIG_SLOTS_MASK	0x000000FF
156 
157 /*
158  * xHCI Port Status Registers and bits. See xHCI 1.1 / 5.4.8.
159  */
160 #define	XHCI_PORTSC(n)		(0x3F0 + (0x10 * (n)))	/* XHCI port status */
161 #define	XHCI_PS_CCS	0x00000001	/* RO - current connect status */
162 #define	XHCI_PS_PED	0x00000002	/* RW - port enabled / disabled */
163 #define	XHCI_PS_OCA	0x00000008	/* RO - over current active */
164 #define	XHCI_PS_PR	0x00000010	/* RW - port reset */
165 #define	XHCI_PS_PLS_GET(x)	(((x) >> 5) & 0xF) /* RW - port link state */
166 #define	XHCI_PS_PLS_SET(x)	(((x) & 0xF) << 5) /* RW - port link state */
167 #define	XHCI_PS_PP	0x00000200	/* RW - port power */
168 #define	XHCI_PS_SPEED_GET(x)	(((x) >> 10) & 0xF) /* RO - port speed */
169 #define	XHCI_PS_PIC_GET(x)	(((x) >> 14) & 0x3) /* RW - port indicator */
170 #define	XHCI_PS_PIC_SET(x)	(((x) & 0x3) << 14) /* RW - port indicator */
171 #define	XHCI_PS_LWS	0x00010000	/* RW - port link state write strobe */
172 #define	XHCI_PS_CSC	0x00020000	/* RW - connect status change */
173 #define	XHCI_PS_PEC	0x00040000	/* RW - port enable/disable change */
174 #define	XHCI_PS_WRC	0x00080000	/* RW - warm port reset change */
175 #define	XHCI_PS_OCC	0x00100000	/* RW - over-current change */
176 #define	XHCI_PS_PRC	0x00200000	/* RW - port reset change */
177 #define	XHCI_PS_PLC	0x00400000	/* RW - port link state change */
178 #define	XHCI_PS_CEC	0x00800000	/* RW - config error change */
179 #define	XHCI_PS_CAS	0x01000000	/* RO - cold attach status */
180 #define	XHCI_PS_WCE	0x02000000	/* RW - wake on connect enable */
181 #define	XHCI_PS_WDE	0x04000000	/* RW - wake on disconnect enable */
182 #define	XHCI_PS_WOE	0x08000000	/* RW - wake on over-current enable */
183 #define	XHCI_PS_DR	0x40000000	/* RO - device removable */
184 #define	XHCI_PS_WPR	0x80000000U	/* RW - warm port reset */
185 #define	XHCI_PS_CLEAR	0x80FF01FFU	/* command bits */
186 #define	XHCI_PS_INDPORT(x)	((x) & 0xFF)
187 #define	XHCI_PS_INDVAL(x)	(((x) & 0xFF00) >> 8)
188 
189 /*
190  * xHCI Port Power Management and Control Register. See xHCI 1.1 / 5.4.9.
191  */
192 #define	XHCI_PORTPMSC(n)	(0x3F4 + (0x10 * (n)))
193 #define	XHCI_PM3_U1TO_GET(x)	(((x) >> 0) & 0xFF)	/* RW - U1 timeout */
194 #define	XHCI_PM3_U1TO_SET(x)	(((x) & 0xFF) << 0)	/* RW - U1 timeout */
195 #define	XHCI_PM3_U2TO_GET(x)	(((x) >> 8) & 0xFF)	/* RW - U2 timeout */
196 #define	XHCI_PM3_U2TO_SET(x)	(((x) & 0xFF) << 8)	/* RW - U2 timeout */
197 #define	XHCI_PM3_FLA		0x00010000	/* RW - Force Link PM Accept */
198 #define	XHCI_PM2_L1S_GET(x)	(((x) >> 0) & 0x7)	/* RO - L1 status */
199 #define	XHCI_PM2_RWE		0x00000008	/* RW - remote wakup enable */
200 /* RW - host initiated resume durations */
201 #define	XHCI_PM2_HIRD_GET(x)	(((x) >> 4) & 0xF)
202 #define	XHCI_PM2_HIRD_SET(x)	(((x) & 0xF) << 4)
203 #define	XHCI_PM2_L1SLOT_GET(x)	(((x) >> 8) & 0xFF) /* RW - L1 device slot */
204 #define	XHCI_PM2_L1SLOT_SET(x)	(((x) & 0xFF) << 8) /* RW - L1 device slot */
205 #define	XHCI_PM2_HLE		0x00010000	/* RW - hardware LPM enable */
206 #define	XHCI_PORTLI(n)		(0x3F8 + (0x10 * (n))) /* RO - port link info */
207 #define	XHCI_PLI3_ERR_GET(x)	(((x) >> 0) & 0xFFFF) /* RO - port link errs */
208 #define	XHCI_PORTRSV(n)		(0x3FC + (0x10 * (n)))	/* XHCI port reserved */
209 
210 /*
211  * xHCI runtime registers - xHCI 1.1 / 5.5.
212  * Offset given by XHCI_CAPLENGTH + XHCI_RTSOFF registers.
213  */
214 #define	XHCI_MFINDEX		0x0000		/* RO - microframe index */
215 #define	XHCI_MFINDEX_GET(x)	((x) & 0x3FFF)
216 #define	XHCI_IMAN(n)		(0x0020 + (0x20 * (n)))	/* XHCI interrupt */
217 							/* management */
218 #define	XHCI_IMAN_INTR_PEND	0x00000001	/* RW - interrupt pending */
219 #define	XHCI_IMAN_INTR_ENA	0x00000002	/* RW - interrupt enable */
220 
221 /*
222  * XHCI Interrupt moderation
223  */
224 #define	XHCI_IMOD(n)		(0x0024 + (0x20 * (n)))
225 
226 /*
227  * XHCI event ring segment table size
228  */
229 #define	XHCI_ERSTSZ(n)		(0x0028 + (0x20 * (n)))
230 #define	XHCI_ERSTS_MASK		0xffff
231 #define	XHCI_ERSTS_SET(x)	((x) & XHCI_ERSTS_MASK)
232 
233 /*
234  * XHCI event ring segment table BA
235  */
236 #define	XHCI_ERSTBA(n)		(0x0030 + (0x20 * (n)))
237 
238 /*
239  * XHCI event ring dequeue pointer
240  */
241 #define	XHCI_ERDP(n)		(0x0038 + (0x20 * (n)))
242 #define	XHCI_ERDP_SINDEX(x)	((x) & 0x7)	/* RO - dequeue segment index */
243 #define	XHCI_ERDP_BUSY		0x00000008	/* RW - event handler busy */
244 
245 /*
246  * XHCI doorbell registers - xHCI 1.1 / 5.6.
247  * Offset given by XHCI_CAPLENGTH + XHCI_DBOFF registers
248  */
249 #define	XHCI_DOORBELL(n)	(0x0000 + (4 * (n)))
250 #define	XHCI_DB_TARGET_GET(x)	((x) & 0xFF)
251 #define	XHCI_DB_TARGET_SET(x)	((x) & 0xFF)
252 #define	XHCI_DB_SID_GET(x)	(((x) >> 16) & 0xFFFF)
253 #define	XHCI_DB_SID_SET(x)	(((x) & 0xFFFF) << 16)
254 
255 /*
256  * XHCI capability IDs - xHCI 1.1 / 7 - Table 146
257  */
258 #define	XHCI_ID_XECP_DONE	0x0000
259 #define	XHCI_ID_USB_LEGACY	0x0001
260 #define	XHCI_ID_PROTOCOLS	0x0002
261 #define	XHCI_ID_POWER_MGMT	0x0003
262 #define	XHCI_ID_VIRTUALIZATION	0x0004
263 #define	XHCI_ID_MSG_IRQ		0x0005
264 #define	XHCI_ID_USB_LOCAL_MEM	0x0006
265 #define	XHCI_ID_DEBUG		0x000A
266 #define	XHCI_ID_EXT_MSG_IRQ	0x0011
267 
268 #define	XHCI_XECP_ID(x)		((x) & 0xFF)
269 #define	XHCI_XECP_NEXT(x)	(((x) >> 8) & 0xFF)
270 
271 /*
272  * xHCI USB Legacy Support Capability - xHCI 1.1 / 7.1.
273  */
274 #define	XHCI_BIOS_OWNED		(1 << 16)
275 #define	XHCI_OS_OWNED		(1 << 24)
276 
277 /*
278  * These definitions manipulate the generation of SMIs. Note that the contents
279  * of reserved registers are required to be preserved. In addition, Several of
280  * the bits require you to write one to clear.
281  */
282 #define	XHCI_XECP_LEGCTLSTS	0x04
283 #define	XHCI_XECP_SMI_MASK	(0x7 << 1) + (0xff << 5) + (0x7UL << 17)
284 #define	XHCI_XECP_CLEAR_SMI	(0x7UL << 29)
285 
286 /*
287  * xHCI Supported Protocol Capability. See xHCI 1.1 / 7.2.
288  */
289 #define	XHCI_XECP_PROT_MAJOR(x)		(((x) >> 24) & 0xff)
290 #define	XHCI_XECP_PROT_MINOR(x)		(((x) >> 16) & 0xff)
291 #define	XHCI_XECP_PROT_PCOUNT(x)	(((x) >> 8) & 0xff)
292 #define	XHCI_XECP_PROT_FPORT(x)		((x) & 0xff)
293 
294 /*
295  * xHCI Slot Context definitions - xHCI 1.1 / 6.2.2.
296  */
297 #define	XHCI_SCTX_GET_ROUTE(x)		((x) & 0xfffff)
298 #define	XHCI_SCTX_SET_ROUTE(x)		((x) & 0xfffff)
299 #define	XHCI_SCTX_GET_SPEED(x)		(((x) >> 20) & 0xf)
300 #define	XHCI_SCTX_SET_SPEED(x)		(((x) & 0xf) << 20)
301 #define	XHCI_SCTX_GET_MTT(x)		(((x) >> 25) & 0x1)
302 #define	XHCI_SCTX_SET_MTT(x)		(((x) & 0x1) << 25)
303 #define	XHCI_SCTX_GET_HUB(x)		(((x) >> 26) & 0x1)
304 #define	XHCI_SCTX_SET_HUB(x)		(((x) & 0x1) << 26)
305 #define	XHCI_SCTX_GET_DCI(x)		(((x) >> 27) & 0x1f)
306 #define	XHCI_SCTX_SET_DCI(x)		(((x) & 0x1f) << 27)
307 #define	XHCI_SCTX_DCI_MASK		(0x1fUL << 27)
308 
309 #define	XHCI_SCTX_GET_MAX_EL(x)		((x) & 0xffff)
310 #define	XHCI_SCTX_SET_MAX_EL(x)		((x) & 0xffff)
311 #define	XHCI_SCTX_GET_RHPORT(x)		(((x) >> 16) & 0xff)
312 #define	XHCI_SCTX_SET_RHPORT(x)		(((x) & 0xff) << 16)
313 #define	XHCI_SCTX_GET_NPORTS(x)		(((x) >> 24) & 0xff)
314 #define	XHCI_SCTX_SET_NPORTS(x)		(((x) & 0xff) << 24)
315 
316 #define	XHCI_SCTX_GET_TT_HUB_SID(x)	((x) & 0xff)
317 #define	XHCI_SCTX_SET_TT_HUB_SID(x)	((x) & 0xff)
318 #define	XHCI_SCTX_GET_TT_PORT_NUM(x)	(((x) >> 8) & 0xff)
319 #define	XHCI_SCTX_SET_TT_PORT_NUM(x)	(((x) & 0xff) << 8)
320 #define	XHCI_SCTX_GET_TT_THINK_TIME(x)	(((x) >> 16) & 0x3)
321 #define	XHCI_SCTX_SET_TT_THINK_TIME(x)	(((x) & 0x3) << 16)
322 #define	XHCI_SCTX_SET_IRQ_TARGET(x)	(((x) & 0x3ff) << 22)
323 #define	XHCI_SCTX_GET_IRQ_TARGET(x)	(((x) >> 22) & 0x3ff)
324 
325 #define	XHCI_SCTX_GET_DEV_ADDR(x)	((x) & 0xff)
326 #define	XHCI_SCTX_GET_SLOT_STATE(x)	(((x) >> 27) & 0x1f)
327 
328 #define	XHCI_SLOT_DIS_ENAB	0
329 #define	XHCI_SLOT_DEFAULT	1
330 #define	XHCI_SLOT_ADDRESSED	2
331 #define	XHCI_SLOT_CONFIGURED	3
332 
333 /*
334  * xHCI Slot Context definitions - xHCI 1.1 / 6.2.3.
335  */
336 #define	XHCI_EPCTX_STATE(x)		((x) & 0x7)
337 #define	XHCI_EP_DISABLED	0x0
338 #define	XHCI_EP_RUNNING		0x1
339 #define	XHCI_EP_HALTED		0x2
340 #define	XHCI_EP_STOPPED		0x3
341 #define	XHCI_EP_ERROR		0x4
342 #define	XHCI_EPCTX_SET_MULT(x)		(((x) & 0x3) << 8)
343 #define	XHCI_EPCTX_GET_MULT(x)		(((x) >> 8) & 0x3)
344 #define	XHCI_EPCTX_SET_MAXP_STREAMS(x)	(((x) & 0x1F) << 10)
345 #define	XHCI_EPCTX_GET_MAXP_STREAMS(x)	(((x) >> 10) & 0x1F)
346 #define	XHCI_EPCTX_SET_LSA(x)		(((x) & 0x1) << 15)
347 #define	XHCI_EPCTX_GET_LSA(x)		(((x) >> 15) & 0x1)
348 #define	XHCI_EPCTX_SET_IVAL(x)		(((x) & 0xff) << 16)
349 #define	XHCI_EPCTX_GET_IVAL(x)		(((x) >> 16) & 0xFF)
350 #define	XHCI_EPCTX_GET_MAX_ESIT_HI(x)	((((x) >> 24) & 0xFF) << 16)
351 #define	XHCI_EPCTX_SET_MAX_ESIT_HI(x)	((((x) >> 16) & 0xFF) << 24)
352 
353 #define	XHCI_EPCTX_GET_CERR(x)		(((x) >> 1) & 0x3)
354 #define	XHCI_EPCTX_SET_CERR(x)		(((x) & 0x3) << 1)
355 #define	XHCI_EPCTX_SET_EPTYPE(x)	(((x) & 0x7) << 3)
356 #define	XHCI_EPCTX_GET_EPTYPE(x)	(((x) >> 3) & 0x7)
357 #define	XHCI_EPCTX_SET_HID(x)		(((x) & 0x1) << 7)
358 #define	XHCI_EPCTX_GET_HID(x)		(((x) >> 7) & 0x1)
359 #define	XHCI_EPCTX_SET_MAXB(x)		(((x) & 0xff) << 8)
360 #define	XHCI_EPCTX_GET_MAXB(x)		(((x) >> 8) & 0xff)
361 #define	XHCI_EPCTX_SET_MPS(x)		(((x) & 0xffff) << 16)
362 #define	XHCI_EPCTX_GET_MPS(x)		(((x) >> 16) & 0xffff)
363 #define	XHCI_SPEED_FULL		1
364 #define	XHCI_SPEED_LOW		2
365 #define	XHCI_SPEED_HIGH		3
366 #define	XHCI_SPEED_SUPER	4
367 
368 #define	XHCI_EPCTX_TYPE_ISOCH_OUT	(1)
369 #define	XHCI_EPCTX_TYPE_BULK_OUT	(2)
370 #define	XHCI_EPCTX_TYPE_INTR_OUT	(3)
371 #define	XHCI_EPCTX_TYPE_CTRL		(4)
372 #define	XHCI_EPCTX_TYPE_ISOCH_IN	(5)
373 #define	XHCI_EPCTX_TYPE_BULK_IN		(6)
374 #define	XHCI_EPCTX_TYPE_INTR_IN		(7)
375 
376 #define	XHCI_EPCTX_AVG_TRB_LEN(x)		((x) & 0xffff)
377 #define	XHCI_EPCTX_MAX_ESIT_PAYLOAD(x)		(((x) & 0xffff) << 16)
378 #define	XHCI_EPCTX_GET_MAX_ESIT_PAYLOAD(x)	(((x) >> 16) & 0xffff)
379 
380 #define	XHCI_INCTX_MASK_DCI(n)	(0x1 << (n))
381 
382 /*
383  * Transfer Request Block definitions.
384  */
385 #define	XHCI_TRB_TYPE_MASK	0xfc00
386 #define	XHCI_TRB_TYPE(x)	(((x) & XHCI_TRB_TYPE_MASK) >> 10)
387 #define	XHCI_TRB_PORTID(x)	(((x) & (0xffUL << 24)) >> 24)	/* Port ID */
388 #define	XHCI_TRB_MAXSIZE	(64 * 1024)
389 
390 #define	XHCI_TRB_GET_CODE(x)	(((x) >> 24) & 0xff) /* Get TRB code */
391 #define	XHCI_TRB_TDREM(x)	(((x) & 0x1f) << 17) /* Set TD remaining len. */
392 #define	XHCI_TRB_GET_TDREM(x)	(((x) >> 17) & 0x1f) /* Get TD remaining len. */
393 #define	XHCI_TRB_REMAIN(x)	((x) & 0xffffff)	/* Remaining length */
394 #define	XHCI_TRB_LEN(x)		((x) & 0x1ffff)		/* Transfer length */
395 #define	XHCI_TRB_INTR(x)	(((x) & 0x3ff) << 22) /* Set MSI-X target */
396 #define	XHCI_TRB_GET_INTR(x)	(((x) >> 22) & 0x3ff) /* Get MSI-X target */
397 
398 /*
399  * TRB flags that are used between different different TRB types.
400  */
401 #define	XHCI_TRB_CYCLE		(1 << 0)	/* Enqueue point of xfer ring */
402 #define	XHCI_TRB_ENT		(1 << 1)	/* Evaluate next TRB */
403 #define	XHCI_TRB_LINKSEG	XHCI_TRB_ENT	/* Link to next segment */
404 #define	XHCI_TRB_ISP		(1 << 2)	/* Interrupt on short packet */
405 #define	XHCI_TRB_NOSNOOP	(1 << 3)	/* PCIe no snoop */
406 #define	XHCI_TRB_CHAIN		(1 << 4)	/* Chained with next TRB */
407 #define	XHCI_TRB_IOC		(1 << 5)	/* Interrupt On Completion */
408 #define	XHCI_TRB_IDT		(1 << 6)	/* Immediate Data */
409 #define	XHCI_TRB_GET_TBC(x)	(((x) >> 7) & 0x3)	/* Get/Set Transfer */
410 #define	XHCI_TRB_SET_TBC(x)	(((x) & 0x3) << 7)	/* Burst Count */
411 #define	XHCI_TRB_BSR		(1 << 9)	/* Block Set Address */
412 #define	XHCI_TRB_DCEP		(1 << 9)	/* Deconfigure endpoint */
413 #define	XHCI_TRB_TSP		(1 << 9)	/* Transfer State Preserve */
414 #define	XHCI_TRB_BEI		(1 << 9)	/* Block Event Interrupt */
415 #define	XHCI_TRB_DIR_IN		(1 << 16)
416 #define	XHCI_TRB_TRT_OUT	(2 << 16)
417 #define	XHCI_TRB_TRT_IN		(3 << 16)
418 #define	XHCI_TRB_GET_CYCLE(x)	((x) & 0x1)
419 #define	XHCI_TRB_GET_ED(x)	(((x) >> 2) & 0x1)
420 #define	XHCI_TRB_GET_FLAGS(x)	((x) & 0x1ff)
421 #define	XHCI_TRB_GET_TYPE(x)	(((x) >> 10) & 0x3f)
422 #define	XHCI_TRB_GET_EP(x)	(((x) >> 16) & 0x1f)
423 #define	XHCI_TRB_SET_EP(x)	(((x) & 0x1f) << 16)
424 #define	XHCI_TRB_GET_STYPE(x)	(((x) >> 16) & 0x1f)
425 #define	XHCI_TRB_SET_STYPE(x)	(((x) & 0x1f) << 16)
426 #define	XHCI_TRB_GET_SLOT(x)	(((x) >> 24) & 0xff)
427 #define	XHCI_TRB_SET_SLOT(x)	(((x) & 0xff) << 24)
428 
429 /*
430  * Isochronous specific fields. See xHCI 1.1 / 6.4.1.3.
431  */
432 #define	XHCI_TRB_GET_TLBPC(x)	(((x) >> 16) & 0xf)
433 #define	XHCI_TRB_SET_TLBPC(x)	(((x) & 0xf) << 16)
434 #define	XHCI_TRB_GET_FRAME(x)	(((x) >> 20) & 0x7ff)
435 #define	XHCI_TRB_SET_FRAME(x)	(((x) & 0x7ff) << 20)
436 #define	XHCI_TRB_SIA		(1UL << 31)		/* Start Isoch ASAP */
437 
438 /*
439  * TRB Types. See xHCI 1.1 / 6.4.6.
440  */
441 
442 /* Transfer Ring Types */
443 #define	XHCI_TRB_TYPE_NORMAL	(1 << 10)
444 #define	XHCI_TRB_TYPE_SETUP	(2 << 10)
445 #define	XHCI_TRB_TYPE_DATA	(3 << 10)
446 #define	XHCI_TRB_TYPE_STATUS	(4 << 10)
447 #define	XHCI_TRB_TYPE_ISOCH	(5 << 10)
448 #define	XHCI_TRB_TYPE_LINK	(6 << 10)
449 #define	XHCI_TRB_TYPE_EVENT	(7 << 10)
450 #define	XHCI_TRB_TYPE_NOOP	(8 << 10)
451 
452 /* Command ring Types */
453 #define	XHCI_CMD_ENABLE_SLOT	(9 << 10)
454 #define	XHCI_CMD_DISABLE_SLOT	(10 << 10)
455 #define	XHCI_CMD_ADDRESS_DEVICE	(11 << 10)
456 #define	XHCI_CMD_CONFIG_EP	(12 << 10)
457 #define	XHCI_CMD_EVAL_CTX	(13 << 10)
458 #define	XHCI_CMD_RESET_EP	(14 << 10)
459 #define	XHCI_CMD_STOP_EP	(15 << 10)
460 #define	XHCI_CMD_SET_TR_DEQ	(16 << 10)
461 #define	XHCI_CMD_RESET_DEV	(17 << 10)
462 #define	XHCI_CMD_FEVENT		(18 << 10)
463 #define	XHCI_CMD_NEG_BW		(19 << 10)
464 #define	XHCI_CMD_SET_LT		(20 << 10)
465 #define	XHCI_CMD_GET_BW		(21 << 10)
466 #define	XHCI_CMD_FHEADER	(22 << 10)
467 #define	XHCI_CMD_NOOP		(23 << 10)
468 
469 /* Event ring Types */
470 #define	XHCI_EVT_XFER		(32 << 10)
471 #define	XHCI_EVT_CMD_COMPLETE	(33 << 10)
472 #define	XHCI_EVT_PORT_CHANGE	(34 << 10)
473 #define	XHCI_EVT_BW_REQUEST	(35 << 10)
474 #define	XHCI_EVT_DOORBELL	(36 << 10)
475 #define	XHCI_EVT_HOST_CTRL	(37 << 10)
476 #define	XHCI_EVT_DEVICE_NOTIFY	(38 << 10)
477 #define	XHCI_EVT_MFINDEX_WRAP	(39 << 10)
478 
479 #define	XHCI_RING_TYPE_SHIFT(x)	((x) << 10)
480 
481 /*
482  * TRB Completion Codes. See xHCI 1.1 / 6.4.5.
483  */
484 #define	XHCI_CODE_INVALID	 0	/* Producer didn't update the code. */
485 #define	XHCI_CODE_SUCCESS	 1	/* Badaboum, plaf, plouf, yeepee! */
486 #define	XHCI_CODE_DATA_BUF	 2	/* Overrun or underrun */
487 #define	XHCI_CODE_BABBLE	 3	/* Device is "babbling" */
488 #define	XHCI_CODE_TXERR		 4	/* USB Transaction error */
489 #define	XHCI_CODE_TRB		 5	/* Invalid TRB  */
490 #define	XHCI_CODE_STALL		 6	/* Stall condition */
491 #define	XHCI_CODE_RESOURCE	 7	/* No resource available for the cmd */
492 #define	XHCI_CODE_BANDWIDTH	 8	/* Not enough bandwidth  for the cmd */
493 #define	XHCI_CODE_NO_SLOTS	 9	/* MaxSlots limit reached */
494 #define	XHCI_CODE_STREAM_TYPE	10	/* Stream Context Type value detected */
495 #define	XHCI_CODE_SLOT_NOT_ON	11	/* Related device slot is disabled */
496 #define	XHCI_CODE_ENDP_NOT_ON	12	/* Related enpoint is disabled */
497 #define	XHCI_CODE_SHORT_XFER	13	/* Short packet */
498 #define	XHCI_CODE_RING_UNDERRUN	14	/* Empty ring when transmitting isoc */
499 #define	XHCI_CODE_RING_OVERRUN	15	/* Empty ring when receiving isoc */
500 #define	XHCI_CODE_VF_RING_FULL	16	/* VF's event ring is full */
501 #define	XHCI_CODE_PARAMETER	17	/* Context parameter is invalid */
502 #define	XHCI_CODE_BW_OVERRUN	18	/* TD exceeds the bandwidth */
503 #define	XHCI_CODE_CONTEXT_STATE	19	/* Transition from illegal ctx state */
504 #define	XHCI_CODE_NO_PING_RESP	20	/* Unable to complete periodic xfer */
505 #define	XHCI_CODE_EV_RING_FULL	21	/* Unable to post an evt to the ring */
506 #define	XHCI_CODE_INCOMPAT_DEV	22	/* Device cannot be accessed */
507 #define	XHCI_CODE_MISSED_SRV	23	/* Unable to service isoc EP in ESIT */
508 #define	XHCI_CODE_CMD_RING_STOP	24	/* Command Stop (CS) requested */
509 #define	XHCI_CODE_CMD_ABORTED	25	/* Command Abort (CA) operation */
510 #define	XHCI_CODE_XFER_STOPPED	26	/* xfer terminated by a stop endpoint */
511 #define	XHCI_CODE_XFER_STOPINV	27	/* TRB transfer length invalid */
512 #define	XHCI_CODE_XFER_STOPSHORT	28	/* Stopped before end of TD */
513 #define	XHCI_CODE_MELAT		29	/* Max Exit Latency too large */
514 #define	XHCI_CODE_RESERVED	30
515 #define	XHCI_CODE_ISOC_OVERRUN	31	/* IN data buffer < Max ESIT Payload */
516 #define	XHCI_CODE_EVENT_LOST	32	/* Internal overrun - impl. specific */
517 #define	XHCI_CODE_UNDEFINED	33	/* Fatal error - impl. specific */
518 #define	XHCI_CODE_INVALID_SID	34	/* Invalid stream ID received */
519 #define	XHCI_CODE_SEC_BW	35	/* Cannot alloc secondary BW Domain */
520 #define	XHCI_CODE_SPLITERR	36	/* USB2 split transaction */
521 
522 #ifdef __cplusplus
523 }
524 #endif
525 
526 #endif /* _SYS_USB_HCD_XHCI_XHCIREG_H */
527