1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_AUDIOTS_H
27 #define	_AUDIOTS_H
28 
29 /*
30  * Header file for the audiots device driver.
31  */
32 
33 /*
34  * Values returned by the AUDIO_GETDEV ioctl()
35  */
36 #define	TS_DEV_NAME		"SUNW,audiots"
37 #define	TS_DEV_CONFIG		"onboard1"
38 #define	TS_DEV_VERSION_A	"a"		/* grover, sngl strming play */
39 #define	TS_DEV_VERSION_B	"b"		/* birdsnest, sngl strm play */
40 
41 /*
42  * Driver supported configuration information
43  */
44 #define	TS_NAME			"audiots"
45 #define	TS_MOD_NAME		"audiots audio driver"
46 
47 #define	TS_RATE			(48000)
48 #define	TS_STEREO		(2)		/* stereo */
49 #define	TS_FRAMESZ		(4)		/* 16-bit stereo */
50 
51 /*
52  * Misc. defines
53  */
54 #define	TS_IO_MAPPED_REGS	(1)
55 #define	TS_MEM_MAPPED_REGS	(2)
56 #define	TS_ALL_DMA_ENGINES	(0xffffffff)
57 #define	TS_ALL_DMA_OFF		(0x00000000)
58 
59 #define	TS_20MS			(20000)		/* 20,000 microseconds */
60 #define	TS_20US			(20)		/* 20 microseconds */
61 #define	TS_SRC_SHIFT		(12)
62 
63 #define	TS_NUM_PORTS		(2)
64 #define	TS_OUTPUT_PORT		(0)
65 #define	TS_INPUT_PORT		(1)
66 
67 #define	TS_MAX_HW_CHANNELS	(32)
68 
69 #define	TS_WAIT_CNT		(512)
70 #define	TS_LOOP_CNT		(10)
71 #define	TS_DELAY_CNT		(25)
72 #define	TS_CODEC_REG(r)		((r) >> 1)
73 
74 /* ALI Hacks */
75 #define	TS_READ_TRIES		(TS_WAIT_CNT/10)
76 #define	TS_RESET_TRIES		(16)
77 #define	TS_SB_RESET		(0x7fff)
78 
79 /* These are the devices we know about */
80 #define	TS_DEVICE_ALI_M5451			((0x10b9 << 16) | (0x5451))
81 #define	TS_DEVICE_TRIDENT_4DWAVEDX		((0x1023 << 16) | (0x2000))
82 #define	TS_DEVICE_TRIDENT_4DWAVENX		((0x1023 << 16) | (0x2001))
83 #define	TS_DEVICE_SIS_7018			((0x1039 << 16) | (0x7018))
84 
85 #define	TS_AD_CODEC_ID				0x4144
86 #define	TS_AD_REV_ID				0x5340
87 #define	AC_REV_ID1				0x0001
88 #define	AC_REV_ID2				0x0002
89 
90 #define	TS_CAP_PTR				0xdc
91 #define	TS_PWR_D0				0x0000
92 #define	TS_PWR_D1				0x0001
93 #define	TS_PWR_D2				0x0002
94 #define	TS_PWR_D3				0x0003
95 #define	TS_PWR_PME				0x8000
96 
97 /*
98  * audiots_aram_t	- ARAM registers
99  */
100 struct audiots_aram {
101 	uint16_t	aram_alpha_fms;			/* e0h - e1h */
102 	uint16_t	aram_cso;			/* e2h - e3h */
103 	uint32_t	aram_cptr_lba;			/* e4h - e7h */
104 	uint16_t	aram_delta;			/* e8h - e9h */
105 	uint16_t	aram_eso;			/* eah - ebh */
106 	uint32_t	aram_reserved;			/* ech - efh */
107 };
108 typedef struct audiots_aram audiots_aram_t;
109 
110 /* aram_cso_alpha_fms register defines */
111 #define	ARAM_FMS_MASK				0x000f
112 #define	ARAM_ALPHA_MASK				0xfff0
113 
114 /* aram_cptr_lba register defines */
115 #define	ARAM_LBA_MASK				0x7fffffff
116 #define	ARAM_CPTR_MASK				0x80000000
117 
118 /*
119  * audiots_eram_t	- ERAM registers
120  */
121 struct audiots_eram {
122 	uint16_t	eram_ctrl_ec;			/* f0h - f1h */
123 	uint16_t	eram_gvsel_pan_vol;		/* f2h - f3h */
124 	uint32_t	eram_ebuf1;			/* f4h - f7h */
125 	uint32_t	eram_ebuf2;			/* f8h - fbh */
126 	uint32_t	eram_reserved;			/* fch - ffh */
127 };
128 typedef struct audiots_eram audiots_eram_t;
129 
130 /* eram_ctrl_ec register defines */
131 #define	ERAM_EC_MASK				0x0fff
132 #define	ERAM_CTRL_MASK				0xf000
133 #define	ERAM_LOOP_MODE				0x1000
134 #define	ERAM_NOLOOP_MODE			0x0000
135 #define	ERAM_SIGNED_PCM				0x2000
136 #define	ERAM_UNSIGNED_PCM			0x0000
137 #define	ERAM_STEREO				0x4000
138 #define	ERAM_MONO				0x0000
139 #define	ERAM_16_BITS				0x8000
140 #define	ERAM_8_BITS				0x0000
141 
142 /* eram_gvsel_pan_vol register defines */
143 #define	ERAM_VOL_MASK				0x00ff
144 #define	ERAM_VOL_0dB				0x0000
145 #define	ERAM_VOL_DEFAULT			0x000f
146 #define	ERAM_VOL_MAX_ATTEN			0x00ff
147 #define	ERAM_PAN_MASK				0x3f00
148 #define	ERAM_PAN_0dB				0x0000
149 #define	ERAM_PAN_MAX_ATTEN			0x3f00
150 #define	ERAM_PAN_LEFT				0x0000
151 #define	ERAM_PAN_RIGHT				0x4000
152 #define	ERAM_MUSIC_VOL				0x0000
153 #define	ERAM_WAVE_VOL				0x8000
154 
155 /* eram_ebuf register defines */
156 #define	ERAM_EBUF_STILL				0x30000000
157 
158 /*
159  * audiots_processor_t	- Audio Processor registers via I/O space
160  *
161  * NOTE: Soutbridge rev 1535D+ uses a read/write register at AudioBase +40
162  * Previous SB chip revs had a seperate write register at AudioBase +40, and
163  * a read register at AudioBase +44.
164  *
165  */
166 struct audiots_processor {
167 	uint32_t	ap_dmar0_1_2_3;			/* 00h - 03h */
168 	uint32_t	ap_dmar4_5_6_7;			/* 04h - 07h */
169 	uint32_t	ap_dmar8_9_10_11;		/* 08h - 0bh */
170 	uint32_t	ap_dmar12_13_14_15;		/* 0ch - 0fh */
171 	uint32_t	ap_sbr0_1_2_3;			/* 10h - 13h */
172 	uint32_t	ap_sbr4_5_6;			/* 14h - 17h */
173 	uint32_t	ap_svbr7;			/* 18h - 1bh */
174 	uint32_t	ap_sbr8_9_10;			/* 1ch - 1fh */
175 	uint32_t	ap_mpur0_1_2_3;			/* 20h - 23h */
176 	uint32_t	ap_rsvd1[3];			/* 24h - 2fh */
177 	uint32_t	ap_gamer0_1;			/* 30h - 33h */
178 	uint32_t	ap_gamer2;			/* 34h - 37h */
179 	uint32_t	ap_gamer3;			/* 38h - 3bh */
180 	uint32_t	ap_rsvd2;			/* 3ch - 3fh */
181 	uint16_t	ap_acrdwr_reg;			/* 40h - 41h */
182 	uint16_t	ap_acrdwr_data;			/* 42h - 43h */
183 	uint16_t	ap_acrd_35D_reg;		/* 44h - 45h */
184 	uint16_t	ap_acrd_35D_data;		/* 46h - 47h */
185 	uint32_t	ap_sctrl;			/* 48h - 4bh */
186 	uint32_t	ap_acgpio;			/* 4ch - 4fh */
187 	uint32_t	ap_asr0;			/* 50h - 53h */
188 	uint32_t	ap_asr1_2;			/* 54h - 57h */
189 	uint32_t	ap_asr3;			/* 58h - 5bh */
190 	uint32_t	ap_asr4_5_6;			/* 5ch - 5fh */
191 	uint32_t	ap_aoplsr0;			/* 60h - 63h */
192 	uint32_t	ap_rsvd3[6];			/* 64h - 7bh */
193 	uint32_t	ap_gp;				/* 7ch - 7fh */
194 	uint32_t	ap_start;			/* 80h - 83h */
195 	uint32_t	ap_stop;			/* 84h - 87h */
196 	uint32_t	ap_delay;			/* 88h - 8bh */
197 	uint32_t	ap_sign_cso;			/* 8ch - 8fh */
198 	uint32_t	ap_cspf;			/* 90h - 93h */
199 	uint32_t	ap_cebc;			/* 94h - 97h */
200 	uint32_t	ap_aint;			/* 98h - 9bh */
201 	uint32_t	ap_eint;			/* 9ch - 9fh */
202 	uint32_t	ap_cir_gc;			/* a0h - a3h */
203 	uint32_t	ap_ainten;			/* a4h - a7h */
204 	uint32_t	ap_volume;			/* a8h - abh */
205 	uint32_t	ap_sbdelta;			/* ach - afh */
206 	uint32_t	ap_miscint;			/* b0h - b3h */
207 	uint32_t	ap_rsvd4[3];			/* b4h - bfh */
208 	uint32_t	ap_sbdm;			/* c0h - c3h */
209 	uint32_t	ap_sb;				/* c4h - c7h */
210 	uint32_t	ap_stimer;			/* c8h - cbh */
211 	uint32_t	ap_lfo_i2s_delta;		/* cch - cfh */
212 	uint32_t	ap_st_target;			/* d0h - d3h */
213 	uint32_t	ap_global_control;		/* d4h - d7h */
214 	uint32_t	ap_rsvd5[2];			/* d8h - dfh */
215 	audiots_aram_t	ap_aram;			/* e0h - efh */
216 	audiots_eram_t	ap_eram;			/* f0h - ffh */
217 };
218 typedef struct audiots_processor audiots_processor_t;
219 
220 /* ap_acwr_reg register defines (40h - 41h) */
221 #define	AP_ACWR_INDEX_MASK			0x007f
222 #define	AP_ACWR_W_PRIMARY_CODEC			0x0000
223 #define	AP_ACWR_W_SECONDARY_CODEC		0x0080
224 #define	AP_ACWR_W_WRITE_MIXER_REG		0x8000
225 #define	AP_ACWR_W_SELECT_WRITE			0x0100
226 #define	AP_ACWR_R_PRIMARY_CODEC			0x0000
227 #define	AP_ACWR_R_SECONDARY_CODEC		0x0080
228 #define	AP_ACWR_R_WRITE_BUSY			0x8000
229 
230 /* ap_acrd_reg register defines (44h - 45h) */
231 #define	AP_ACRD_INDEX_MASK			0x007f
232 #define	AP_ACRD_W_PRIMARY_CODEC			0x0000
233 #define	AP_ACRD_W_SECONDARY_CODEC		0x0080
234 #define	AP_ACRD_W_MODEM_READ_REQ		0x2000
235 #define	AP_ACRD_W_AUDIO_READ_REQ		0x4000
236 #define	AP_ACRD_W_READ_MIXER_REG		0x8000
237 #define	AP_ACRD_R_PRIMARY_CODEC			0x0000
238 #define	AP_ACRD_R_SECONDARY_CODEC		0x0080
239 #define	AP_ACRD_R_MODEM_READ_REQ		0x2000
240 #define	AP_ACRD_R_AUDIO_READ_REQ		0x4000
241 #define	AP_ACRD_R_READ_BUSY			0x8000
242 
243 /* ap_sctrl register defines (48h - 4bh) */
244 #define	AP_SCTRL_WRST_CODEC			0x00000001
245 #define	AP_SCTRL_CRST_CODEC			0x00000002
246 #define	AP_SCTRL_12288K_CLOCK			0x00000000
247 #define	AP_SCTRL_6144K_CLOCK			0x00000004
248 #define	AP_SCTRL_PCM_TO_PRIMARY			0x00000000
249 #define	AP_SCTRL_PCM_TO_SECONDARY		0x00000008
250 #define	AP_SCTRL_DOUPLE_RATE_DISABLE		0x00000000
251 #define	AP_SCTRL_DOUPLE_RATE_ENABLE		0x00000010
252 #define	AP_SCTRL_I2S_DISABLE			0x00000000
253 #define	AP_SCTRL_I2S_ENABLE			0x00000080
254 #define	AP_SCTRL_PCMIN_SEL_PRIMARY_CODEC	0x00000000
255 #define	AP_SCTRL_PCMIN_SEL_SECONDARY_CODEC	0x00000100
256 #define	AP_SCTRL_LINE1IN_SEL_PRIMARY_CODEC	0x00000000
257 #define	AP_SCTRL_LINE1IN_SEL_SECONDARY_CODEC	0x00000200
258 #define	AP_SCTRL_MICIN_SEL_PRIMARY_CODEC	0x00000000
259 #define	AP_SCTRL_MICIN_SEL_SECONDARY_CODEC	0x00000400
260 #define	AP_SCTRL_LINE2IN_SEL_PRIMARY_CODEC	0x00000000
261 #define	AP_SCTRL_LINE2IN_SEL_SECONDARY_CODEC	0x00000800
262 #define	AP_SCTRL_HSETIN_SEL_PRIMARY_CODEC	0x00000000
263 #define	AP_SCTRL_HSETIN_SEL_SECONDARY_CODEC	0x00001000
264 #define	AP_SCTRL_GPIOIN_SEL_PRIMARY_CODEC	0x00000000
265 #define	AP_SCTRL_GPIOIN_SEL_SECONDARY_CODEC	0x00002000
266 #define	AP_SCTRL_SECONDARY_CODEC_MASK		0x0000c000
267 #define	AP_SCTRL_SECONDARY_CODEC_DEFAULT	0x00004000
268 #define	AP_SCTRL_PCMOUT_EN			0x00010000
269 #define	AP_SCTRL_SURROUT_EN			0x00020000
270 #define	AP_SCTRL_CENTEROUT_EN			0x00040000
271 #define	AP_SCTRL_LFEOUT_EN			0x00080000
272 #define	AP_SCTRL_LINE1OUT_EN			0x00100000
273 #define	AP_SCTRL_LINE2OUT_EN			0x00200000
274 #define	AP_SCTRL_HSETOUT_EN			0x00400000
275 #define	AP_SCTRL_GPIOOUT_EN			0x00800000
276 #define	AP_SCTRL_CODECA_RDY			0x01000000	/* primary */
277 #define	AP_SCTRL_CODECB_RDY			0x02000000	/* secondary */
278 #define	AP_SCTRL_CODEC_PD			0x04000000
279 
280 /* ap_acgpio resister defines (4ch - 4fh) */
281 #define	AP_ACGPIO_IRQ1				0x00000002	/* primary */
282 #define	AP_ACGPIO_IRQ2				0x00000004	/* secondary */
283 #define	AP_ACGPIO_INT1_ENABLE			0x00000008
284 #define	AP_ACGPIO_INT1_DISABLE			0x00000000
285 #define	AP_ACGPIO_INT2_ENABLE			0x00000010
286 #define	AP_ACGPIO_INT2_DISABLE			0x00000000
287 #define	AP_ACGPIO_WRITE_SLOT_12			0x00008000
288 #define	AP_ACGPIO_R_SLOT_12_BUSY		0x00008000
289 #define	AP_ACGPIO_DATA_MASK			0xffff0000
290 
291 /* ap_asr0 resgister defines (50h - 53h) */
292 #define	AP_ASR0_CODEC_READY			0x00008000
293 
294 /* ap_asr4_5_6 register defines (5ch - 5fh) */
295 #define	AP_ASR4_REV_A				0x00000080
296 #define	AP_ASR4_REV_BC				0x00000049
297 #define	AP_ASR5_ESP_VERSION			0x00040000
298 #define	AP_ASR6_ESP_VERSION			0x02000000
299 
300 /* ap_ain register defines (98h - 9bh) */
301 #define	AP_AIN_RESET_ALL			0xffffffff
302 
303 /* ap_eain register defines (9ch - 9fh) */
304 #define	AP_EAIN_RESET_ALL			0xffffffff
305 
306 /* ap_cir_gc register defines (a0h - a3h) */
307 #define	AP_CIR_GC_CHANNEL_INDEX_MASK		0x0000001f
308 #define	AP_CIR_GC_RST_STIMER			0x00000100
309 #define	AP_CIR_GC_PAUSE				0x00000200
310 #define	AP_CIR_GC_OVERUN_IE			0x00000400
311 #define	AP_CIR_GC_UNDERUN_IE			0x00000800
312 #define	AP_CIR_GC_ENDLP_IE			0x00001000
313 #define	AP_CIR_GC_MIDLP_IE			0x00002000
314 #define	AP_CIR_GC_ETOG_IE			0x00004000
315 #define	AP_CIR_GC_EDROP_IE			0x00008000
316 #define	AP_CIR_GC_SYS_MEM_4G_ENABLE		0x00010000
317 #define	AP_CIR_GC_PCM_FIFO			0x00000000
318 #define	AP_CIR_GC_MMC_BUFFER			0x00100000
319 #define	AP_CIR_GC_NORMAL_MODE			0x00000000
320 #define	AP_CIR_GC_EXPROM_DUMP_MODE_ENABLE	0x00800000
321 #define	AP_CIR_GC_EXPROM_DEBUG_MODE		0x04000000
322 #define	AP_CIR_GC_TEST_LOOPBACK_ON		0x08000000
323 
324 /* ap_ainten register defines (a4h - a7h) */
325 #define	AP_AINTEN_DISABLE_ALL			0x00000000
326 
327 /* ap_volume regsiter defines (a8h - abh) */
328 #define	AP_VOLUME_WAVE_LEFT_MASK		0x000000ff
329 #define	AP_VOLUME_WAVE_LEFT_MUTE		0x000000ff
330 #define	AP_VOLUME_WAVE_LEFT_FULL		0x00000000
331 #define	AP_VOLUME_WAVE_LEFT_SHIFT		0
332 #define	AP_VOLUME_WAVE_RIGHT_MASK		0x0000ff00
333 #define	AP_VOLUME_WAVE_RIGHT_MUTE		0x0000ff00
334 #define	AP_VOLUME_WAVE_RIGHT_FULL		0x00000000
335 #define	AP_VOLUME_WAVE_RIGHT_SHIFT		8
336 #define	AP_VOLUME_MUSIC_LEFT_MASK		0x00ff0000
337 #define	AP_VOLUME_MUSIC_LEFT_MUTE		0x00ff0000
338 #define	AP_VOLUME_MUSIC_LEFT_FULL		0x00000000
339 #define	AP_VOLUME_MUSIC_LEFT_SHIFT		16
340 #define	AP_VOLUME_MUSIC_RIGHT_MASK		0xff000000
341 #define	AP_VOLUME_MUSIC_RIGHT_MUTE		0xff000000
342 #define	AP_VOLUME_MUSIC_RIGHT_FULL		0x00000000
343 #define	AP_VOLUME_MUSIC_RIGHT_SHIFT		24
344 
345 /* ap_miscint register defines (b0h - b3h) */
346 #define	AP_MISCINT_PB_UNDERUN_IRQ		0x00000001
347 #define	AP_MISCINT_REC_OVERRUN_IRQ		0x00000002
348 #define	AP_MISCINT_SB_IRQ			0x00000004
349 #define	AP_MISCINT_MPU401_IRQ			0x00000008
350 #define	AP_MISCINT_OPL3_IRQ			0x00000010
351 #define	AP_MISCINT_ADDRESS_IRQ			0x00000020
352 #define	AP_MISCINT_ENVELOPE_IRQ			0x00000040
353 #define	AP_MISCINT_ST_IRQ			0x00000080
354 #define	AP_MISCINT_PB_UNDERUN			0x00000100
355 #define	AP_MISCINT_REC_OVERUN			0x00000200
356 #define	AP_MISCINT_MIXER_UNDERFLOW_FLAG		0x00000400
357 #define	AP_MISCINT_MIXER_OVERFLOW_FLAG		0x00000800
358 #define	AP_MISCINT_ST_TARGET_REACHED		0x00008000
359 #define	AP_MISCINT_PB_24K_MODE			0x00010000
360 #define	AP_MISCINT_OPLTIMER_IE			0x00020000
361 #define	AP_MISCINT_GPIO_IE			0x00040000
362 #define	AP_MISCINT_ST_IRQ_EN			0x00800000
363 #define	AP_MISCINT_ACGPIO_IRQ			0x01000000
364 #define	AP_MISCINT_GPIO_IRQ			0x02000000
365 
366 /* ap_lfo_i2s_delta register defines (cch - cfh) */
367 #define	AP_I2S_DELTA_MASK			0x00001fff
368 #define	AP_LFO_INIT_MASK			0x00ff0000
369 #define	AP_LFO_48KHZ				0x00000000
370 #define	AP_LFO_48KHZ_BY_4			0x01000000
371 #define	AP_LFO_48KHZ_BY_16			0x02000000
372 #define	AP_LFO_48KHZ_BY_64			0x03000000
373 #define	AP_LFO_ENABLE				0x04000000
374 
375 /* ap_global_control register defines (d4h - d7h) */
376 #define	AP_GLOBAL_CTRL_ENABLE_HW_VOLUME		0x00000001
377 #define	AP_CLOGAL_CTRL_PCM_OUT_AC97		0x00000000
378 #define	AP_CLOGAL_CTRL_PCM_OUT_I2S		0x00000080
379 #define	AP_CLOGAL_CTRL_I2SIN_TO_SYS_MEMORY	0x00000000
380 #define	AP_CLOGAL_CTRL_I2SIN_TO_AC97		0x00001000
381 #define	AP_CLOGAL_CTRL_I2SIN_TO_SYS_MEMORY_AC97	0x00002000
382 #define	AP_CLOGAL_CTRL_MMC_FROM_MIXER		0x00000000
383 #define	AP_CLOGAL_CTRL_MMC_FROM_PCM_OUT		0x00004000
384 #define	AP_CLOGAL_CTRL_PCM_OUT_TO_AC97		0x00000000
385 #define	AP_CLOGAL_CTRL_PCM_OUT_TO_I2S		0x00008000
386 #define	AP_CLOGAL_CTRL_E_HSETOUT_CH16		0x00010000
387 #define	AP_CLOGAL_CTRL_E_HSETIN_CH17		0x00020000
388 #define	AP_CLOGAL_CTRL_E_LINE2OUT_CH18		0x00040000
389 #define	AP_CLOGAL_CTRL_E_LINE2IN_CH19		0x00080000
390 #define	AP_CLOGAL_CTRL_E_LINE1OUT_CH20		0x00100000
391 #define	AP_CLOGAL_CTRL_E_LINE1IN_CH21		0x00200000
392 #define	AP_CLOGAL_CTRL_E_MIC_CH22		0x00400000
393 #define	AP_CLOGAL_CTRL_E_LFE_CH23		0x00800000
394 #define	AP_CLOGAL_CTRL_E_CENTER_CH24		0x01000000
395 #define	AP_CLOGAL_CTRL_E_SURR_R_CH25		0x02000000
396 #define	AP_CLOGAL_CTRL_E_SURR_L_CH26		0x04000000
397 #define	AP_CLOGAL_CTRL_E_PCMOUT_R_CH27		0x08000000
398 #define	AP_CLOGAL_CTRL_E_PCMOUT_L_CH28		0x10000000
399 #define	AP_CLOGAL_CTRL_E_I2SIN_CH29		0x20000000
400 #define	AP_CLOGAL_CTRL_E_MMC_CH30		0x40000000
401 #define	AP_CLOGAL_CTRL_E_PCMIN_CH31		0x80000000
402 
403 /*
404  * audiots_regs_t	- Audio processor registers via memory space.
405  */
406 struct audiots_regs {
407 	audiots_processor_t	aud_regs;
408 	uint32_t		aud_rsvd1[64];
409 	uint32_t		aud_oplram[128];
410 	uint32_t		aud_rsvd2[256];
411 	struct {
412 		audiots_aram_t	aram;
413 		audiots_eram_t	eram;
414 	} aud_ram[TS_MAX_HW_CHANNELS];	/* 32 channels */
415 	struct {
416 		audiots_aram_t	aram;
417 		audiots_eram_t	eram;
418 	} aud_rsvd3[TS_MAX_HW_CHANNELS]; /* another 32 chs not implemented */
419 };
420 typedef struct audiots_regs audiots_regs_t;
421 
422 /*
423  * audiots_save_regs_t	- Saved audio controller registers.
424  */
425 
426 struct audiots_port {
427 	struct audiots_state	*tp_state;
428 	int			tp_num;
429 	int			tp_dma_stream;
430 
431 	uint32_t		tp_dma_mask;
432 
433 	boolean_t		tp_started;
434 	unsigned		tp_nframes;
435 	unsigned		tp_rate;
436 	uint64_t		tp_count;
437 	size_t			tp_size;
438 	caddr_t			tp_kaddr;
439 	uint32_t		tp_paddr;
440 	ddi_dma_handle_t	tp_dmah;
441 	ddi_acc_handle_t	tp_acch;
442 	unsigned		tp_sync_dir;
443 
444 	audio_engine_t		*tp_engine;
445 	/* counting cso */
446 	uint16_t		tp_cso;
447 };
448 typedef struct audiots_port audiots_port_t;
449 
450 /*
451  * audiots_state_t	- per instance state and operation data
452  */
453 struct audiots_state {
454 	uint_t			ts_flags;	/* flags */
455 	dev_info_t		*ts_dip;	/* used by ts_getinfo() */
456 	audio_dev_t		*ts_adev;	/* audio device handle */
457 	ac97_t			*ts_ac97;	/* ac97 common handle */
458 	audiots_regs_t		*ts_regs;	/* memory mapped registers */
459 	audiots_port_t		*ts_ports[TS_NUM_PORTS];
460 						/* hardware engines */
461 
462 	ddi_acc_handle_t	ts_pcih;	/* handle to config regs */
463 	ddi_acc_handle_t	ts_acch;	/* handle to mapped regs */
464 
465 	uint32_t		ts_devid;
466 	uint8_t			ts_revid;	/* SB Chip Revision ID */
467 
468 };
469 typedef struct audiots_state audiots_state_t;
470 
471 /* audiots_state.ts_flags defines */
472 #define	TS_AUDIO_READ_FAILED		0x0020u /* reading the AC97 register */
473 						/* has stopped working */
474 #define	TS_READ_FAILURE_PRINTED		0x0040u /* Flag to avoid flooding the */
475 						/* console with AC97 failure */
476 						/* messages */
477 
478 /*
479  * Read and write the AC-97 Codec's registers
480  */
481 #define	AC97_RETRIES		1000
482 #define	AC97_WAIT		1
483 
484 /*
485  * Useful bit twiddlers
486  */
487 #define	OR_SET_BYTE(handle, addr, val)					\
488 	ddi_put8((handle), (uint8_t *)(addr),				\
489 		(ddi_get8((handle), (uint8_t *)(addr)) | (uint8_t)(val)));
490 
491 #define	OR_SET_SHORT(handle, addr, val)					\
492 	ddi_put16((handle), (uint16_t *)(addr),				\
493 		(ddi_get16((handle), (uint16_t *)(addr)) | (uint16_t)(val)));
494 
495 #define	OR_SET_WORD(handle, addr, val)					\
496 	ddi_put32((handle), (uint32_t *)(addr),				\
497 		(ddi_get32((handle), (uint32_t *)(addr)) | (uint32_t)(val)));
498 
499 #define	AND_SET_BYTE(handle, addr, val)					\
500 	ddi_put8((handle), (uint8_t *)(addr),				\
501 		(ddi_get8((handle), (uint8_t *)(addr)) & (uint8_t)(val)));
502 
503 #define	AND_SET_SHORT(handle, addr, val)				\
504 	ddi_put16((handle), (uint16_t *)(addr),				\
505 		(ddi_get16((handle), (uint16_t *)(addr)) & (uint16_t)(val)));
506 
507 #define	AND_SET_WORD(handle, addr, val)					\
508 	ddi_put32((handle), (uint32_t *)(addr),				\
509 		(ddi_get32((handle), (uint32_t *)(addr)) & (uint32_t)(val)));
510 
511 #endif	/* _AUDIOTS_H */
512