1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  *
21  *
22  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 /*
26  * PMC 8x6G Message Passing Interface Definitions
27  */
28 #ifndef	_PMCS_MPI_H
29 #define	_PMCS_MPI_H
30 #ifdef	__cplusplus
31 extern "C" {
32 #endif
33 
34 #define	PMCS_DWRD(x)	(x << 2)
35 
36 /*
37  * MPI Configuration Table Offsets
38  */
39 #define	PMCS_MPI_AS	PMCS_DWRD(0)	/* ASCII Signature */
40 #define	PMCS_SIGNATURE	0x53434D50
41 
42 #define	PMCS_MPI_IR	PMCS_DWRD(1)	/* Interface Revision */
43 #define	PMCS_MPI_REVISION1	1
44 
45 #define	PMCS_MPI_FW	PMCS_DWRD(2)	/* Firmware Version */
46 #define	PMCS_FW_TYPE(hwp)		(hwp->fw & 0xf)
47 #define		PMCS_FW_TYPE_RELEASED		0
48 #define		PMCS_FW_TYPE_DEVELOPMENT	1
49 #define		PMCS_FW_TYPE_ALPHA		2
50 #define		PMCS_FW_TYPE_BETA		3
51 #define	PMCS_FW_VARIANT(hwp)		((hwp->fw >> 4) & 0xf)
52 #define	PMCS_FW_MAJOR(hwp)		((hwp->fw >> 24) & 0xff)
53 #define	PMCS_FW_MINOR(hwp)		((hwp->fw >> 16) & 0xff)
54 #define	PMCS_FW_MICRO(hwp)		((hwp->fw >>  8) & 0xff)
55 #define	PMCS_FW_REV(hwp)		((hwp->fw >> 8) & 0xffffff)
56 #define	PMCS_FW_VERSION(maj, min, mic)	((maj << 16)|(min << 8)|mic)
57 
58 #define	PMCS_MPI_MOIO	PMCS_DWRD(3)	/* Maximum # of outstandiong I/Os */
59 #define	PMCS_MPI_INFO0	PMCS_DWRD(4)	/* Maximum S/G Elem, Max Dev Handle */
60 #define	PMCS_MSGL(x)	(x & 0xffff)
61 #define	PMCS_MD(x)	((x >> 16) & 0xffff)
62 
63 #define	PMCS_MPI_INFO1	PMCS_DWRD(5)	/* Info #0 */
64 
65 #define	PMCS_MNIQ(x)	(x & 0xff)		/* Max # of Inbound Queues */
66 #define	PMCS_MNOQ(x)	((x >> 8) & 0xff)	/* Max # of Outbound Queues */
67 #define	PMCS_HPIQ(x)	((x >> 16) & 0x1)	/* High Pri Queue Supported */
68 #define	PMCS_ICS(x)	((x >> 18) & 0x1)	/* Interrupt Coalescing */
69 #define	PMCS_NPHY(x)	((x >> 19) & 0x3f)	/* Numbers of PHYs */
70 #define	PMCS_SASREV(x)	((x >> 25) & 0x7)	/* SAS Revision Specification */
71 
72 #define	PMCS_MPI_GSTO	PMCS_DWRD(6)	/* General Status Table Offset */
73 #define	PMCS_MPI_IQCTO	PMCS_DWRD(7)	/* Inbound Queue Config Table Offset */
74 #define	PMCS_MPI_OQCTO	PMCS_DWRD(8)	/* Outbound Queue Config Table Offset */
75 
76 #define	PMCS_MPI_INFO2	PMCS_DWRD(9)	/* Info #1 */
77 
78 #define	IQ_NORMAL_PRI_DEPTH_SHIFT	0
79 #define	IQ_NORMAL_PRI_DEPTH_MASK	0xff
80 #define	IQ_HIPRI_PRI_DEPTH_SHIFT	8
81 #define	IQ_HIPRI_PRI_DEPTH_MASK		0xff00
82 #define	GENERAL_EVENT_OQ_SHIFT		16
83 #define	GENERAL_EVENT_OQ_MASK		0xff0000
84 #define	DEVICE_HANDLE_REMOVED_SHIFT	24
85 #define	DEVICE_HANDLE_REMOVED_MASK	0xff000000ul
86 
87 #define	PMCS_MPI_EVQS	PMCS_DWRD(0xA)	/* SAS Event Queues */
88 #define	PMCS_MPI_EVQSET(pwp, oq, phy)	{				\
89 	uint32_t woff = phy / 4;					\
90 	uint32_t shf = (phy % 4) * 8;					\
91 	uint32_t tmp = pmcs_rd_mpi_tbl(pwp, PMCS_MPI_EVQS + (woff << 2)); \
92 	tmp &= ~(0xff << shf);						\
93 	tmp |= ((oq & 0xff) << shf);					\
94 	pmcs_wr_mpi_tbl(pwp, PMCS_MPI_EVQS + (woff << 2), tmp);		\
95 }
96 
97 #define	PMCS_MPI_SNCQ	PMCS_DWRD(0xC)	/* Sata NCQ Notification Queues */
98 #define	PMCS_MPI_NCQSET(pwp, oq, phy)	{				\
99 	uint32_t woff = phy / 4;					\
100 	uint32_t shf = (phy % 4) * 8;					\
101 	uint32_t tmp = pmcs_rd_mpi_tbl(pwp, PMCS_MPI_SNCQ + (woff << 2)); \
102 	tmp &= ~(0xff << shf);						\
103 	tmp |= ((oq & 0xff) << shf);					\
104 	pmcs_wr_mpi_tbl(pwp, PMCS_MPI_SNCQ + (woff << 2), tmp);		\
105 }
106 
107 /*
108  * I_T Nexus Target Event Notification Queue
109  */
110 #define	PMCS_MPI_IT_NTENQ	PMCS_DWRD(0xE)
111 
112 /*
113  * SSP Target Event Notification Queue
114  */
115 #define	PMCS_MPI_SSP_TENQ	PMCS_DWRD(0x10)
116 
117 /*
118  * I/O Abort Delay
119  */
120 #define	PMCS_MPI_IOABTDLY	PMCS_DWRD(0x12)
121 
122 /*
123  * Customization Setting
124  */
125 #define	PMCS_MPI_CUSTSET	PMCS_DWRD(0x13)
126 
127 #define	PMCS_MPI_CUST_HW_RSC_BSY_ALT	0x1	/* Bit 0 */
128 #define	PMCS_MPI_CUST_ABORT_ITNL	0x2	/* Bit 1 */
129 
130 /*
131  * This specifies a log buffer in host memory for the MSGU.
132  */
133 #define	PMCS_MPI_MELBAH	PMCS_DWRD(0x14)	/* MSGU Log Buffer high 32 bits */
134 #define	PMCS_MPI_MELBAL	PMCS_DWRD(0x15)	/* MSGU Log Buffer low 32 bits */
135 #define	PMCS_MPI_MELBS	PMCS_DWRD(0x16)	/* size in bytes of MSGU log buffer */
136 #define	PMCS_MPI_MELSEV	PMCS_DWRD(0x17)	/* Log Severity */
137 
138 /*
139  * This specifies a log buffer in host memory for the IOP.
140  */
141 #define	PMCS_MPI_IELBAH	PMCS_DWRD(0x18)	/* IOP Log Buffer high 32 bits */
142 #define	PMCS_MPI_IELBAL	PMCS_DWRD(0x19)	/* IOP Log Buffer low 32 bits */
143 #define	PMCS_MPI_IELBS	PMCS_DWRD(0x1A)	/* size in bytes of IOP log buffer */
144 #define	PMCS_MPI_IELSEV	PMCS_DWRD(0x1B)	/* Log Severity */
145 
146 /*
147  * Fatal Error Handling
148  */
149 #define	PMCS_MPI_FERR		PMCS_DWRD(0x1C)
150 #define	PMCS_FERRIE		0x1	/* Fatal Err Interrupt Enable */
151 #define	PMCS_PCAD64		0x2	/* PI/CI addresses are 64-bit */
152 #define	PMCS_FERIV_MASK		0xff00	/* Fatal Err Interrupt Mask */
153 #define	PMCS_FERIV_SHIFT	8	/* Fatal Err Interrupt Shift */
154 
155 #define	PMCS_MPI_IRAE		0x20000	/* Interrupt Reassertion Enable */
156 #define	PMCS_MPI_IRAU		0x40000	/* Interrupt Reassertion Unit */
157 #define	PMCS_MPI_IRAD_MASK	0xfff80000 /* Reassertion Delay Mask */
158 
159 #define	PMCS_FERDOMSGU		PMCS_DWRD(0x1D)
160 #define	PMCS_FERDLMSGU		PMCS_DWRD(0x1E)
161 #define	PMCS_FERDOIOP		PMCS_DWRD(0x1F)
162 #define	PMCS_FERDLIOP		PMCS_DWRD(0x20)
163 
164 /*
165  * MPI GST Table Offsets
166  */
167 
168 #define	PMCS_GST_BASE		0
169 #define	PMCS_GST_IQFRZ0		(PMCS_GST_BASE + PMCS_DWRD(1))
170 #define	PMCS_GST_IQFRZ1		(PMCS_GST_BASE + PMCS_DWRD(2))
171 #define	PMCS_GST_MSGU_TICK	(PMCS_GST_BASE + PMCS_DWRD(3))
172 #define	PMCS_GST_IOP_TICK	(PMCS_GST_BASE + PMCS_DWRD(4))
173 #define	PMCS_GST_PHY_INFO(x)	(PMCS_GST_BASE + PMCS_DWRD(0x6) + PMCS_DWRD(x))
174 #define	PMCS_GST_RERR_BASE	(PMCS_GST_BASE + PMCS_DWRD(0x11))
175 #define	PMCS_GST_RERR_INFO(x)	(PMCS_GST_RERR_BASE + PMCS_DWRD(x))
176 
177 #define	PMCS_MPI_S(x)		((x) & 0x7)
178 #define	PMCS_QF(x)		(((x) >> 3) & 0x1)
179 #define	PMCS_GSTLEN(x)		(((x) >> 4) & 0x3fff)
180 #define	PMCS_HMI_ERR(x)		(((x) >> 16) & 0xffff)
181 
182 #define	PMCS_MPI_STATE_NIL	0
183 #define	PMCS_MPI_STATE_INIT	1
184 #define	PMCS_MPI_STATE_DEINIT	2
185 #define	PMCS_MPI_STATE_ERR	3
186 
187 /*
188  * MPI Inbound Queue Configuration Table Offsets
189  *
190  * Each Inbound Queue configuration area consumes 8 DWORDS (32 bit words),
191  * or 32 bytes.
192  */
193 #define	PMCS_IQC_PARMX(x)	((x) << 5)
194 #define	PMCS_IQBAHX(x)		(((x) << 5) + 4)
195 #define	PMCS_IQBALX(x)		(((x) << 5) + 8)
196 #define	PMCS_IQCIBAHX(x)	(((x) << 5) + 12)
197 #define	PMCS_IQCIBALX(x)	(((x) << 5) + 16)
198 #define	PMCS_IQPIBARX(x)	(((x) << 5) + 20)
199 #define	PMCS_IQPIOFFX(x)	(((x) << 5) + 24)
200 #define	PMCS_IQDX(x)		((x) & 0xffff)
201 #define	PMCS_IQESX(x)		(((x) >> 16) & 0x3fff)
202 #define	PMCS_IQPX(x)		(((x) >> 30) & 0x3)
203 
204 /*
205  * MPI Outbound Queue Configuration Table Offsets
206  *
207  * Each Outbound Queue configuration area consumes 9 DWORDS (32 bit words),
208  * or 36 bytes.
209  */
210 #define	PMCS_OQC_PARMX(x)	(x * 36)
211 #define	PMCS_OQBAHX(x)		((x * 36) + 4)
212 #define	PMCS_OQBALX(x)		((x * 36) + 8)
213 #define	PMCS_OQPIBAHX(x)	((x * 36) + 12)
214 #define	PMCS_OQPIBALX(x)	((x * 36) + 16)
215 #define	PMCS_OQCIBARX(x)	((x * 36) + 20)
216 #define	PMCS_OQCIOFFX(x)	((x * 36) + 24)
217 #define	PMCS_OQIPARM(x)		((x * 36) + 28)
218 #define	PMCS_OQDICX(x)		((x * 36) + 32)
219 
220 #define	PMCS_OQDX(x)		((x) & 0xffff)
221 #define	PMCS_OQESX(x)		(((x) >> 16) & 0x3fff)
222 #define	PMCS_OQICT(x)		((x) & 0xffff)
223 #define	PMCS_OQICC(x)		(((x) >> 16) & 0xff)
224 #define	PMCS_OQIV(x)		(((x) >> 24) & 0xff)
225 
226 #define	OQIEX			(1 << 30)
227 
228 #ifdef	__cplusplus
229 }
230 #endif
231 #endif	/* _PMCS_MPI_H */
232