xref: /illumos-gate/usr/src/uts/common/io/hxge/hxge_defs.h (revision a512c5d1)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2008 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_HXGE_HXGE_DEFS_H
27 #define	_SYS_HXGE_HXGE_DEFS_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 #if	!defined(_BIG_ENDIAN) && !defined(_LITTLE_ENDIAN) && \
34 		!defined(__BIG_ENDIAN) && !defined(__LITTLE_ENDIAN)
35 #error	Host endianness not defined
36 #endif
37 
38 #if	!defined(_BIT_FIELDS_HTOL) && !defined(_BIT_FIELDS_LTOH) && \
39 		!defined(__BIT_FIELDS_HTOL) && !defined(__BIT_FIELDS_LTOH)
40 #error	Bit ordering not defined
41 #endif
42 
43 /* RDC/TDC CSR size */
44 #define	DMA_CSR_SIZE		2048
45 
46 /*
47  * Define the Default RBR, RCR
48  */
49 #define	RBR_DEFAULT_MAX_BLKS	4096	/* each entry (16 blockaddr/64B) */
50 #define	RBR_NBLK_PER_LINE	16	/* 16 block addresses per 64 B line */
51 #define	RBR_DEFAULT_MAX_LEN	65472	/* 2^16 - 64 */
52 #define	RBR_DEFAULT_MIN_LEN	64	/* multiple of 64 */
53 
54 #define	SW_OFFSET_NO_OFFSET	0
55 #define	SW_OFFSET_64		1	/* 64 bytes */
56 #define	SW_OFFSET_128		2	/* 128 bytes */
57 #define	SW_OFFSET_INVALID	3
58 
59 /*
60  * RBR block descriptor is 32 bits (bits [43:12]
61  */
62 #define	RBR_BKADDR_SHIFT	12
63 #define	RCR_DEFAULT_MAX_BLKS	4096	/* each entry (8 blockaddr/64B) */
64 #define	RCR_NBLK_PER_LINE	8	/* 8 block addresses per 64 B line */
65 #define	RCR_DEFAULT_MAX_LEN	(RCR_DEFAULT_MAX_BLKS)
66 #define	RCR_DEFAULT_MIN_LEN	32
67 
68 /*  DMA Channels.  */
69 #define	HXGE_MAX_DMCS		(HXGE_MAX_RDCS + HXGE_MAX_TDCS)
70 #define	HXGE_MAX_RDCS		4
71 #define	HXGE_MAX_TDCS		4
72 
73 #define	VLAN_ETHERTYPE			(0x8100)
74 
75 /* 256 total, each blade gets 42 */
76 #define	TCAM_HXGE_TCAM_MAX_ENTRY	42
77 
78 /*
79  * Locate the DMA channel start offset (PIO_VADDR)
80  * (DMA virtual address space of the PIO block)
81  */
82 /* TX_RNG_CFIG is not used since we are not using VADDR. */
83 #define	TX_RNG_CFIG			0x1000000
84 #define	TDMC_PIOVADDR_OFFSET(channel)	(2 * DMA_CSR_SIZE * channel)
85 #define	RDMC_PIOVADDR_OFFSET(channel)	(TDMC_OFFSET(channel) + DMA_CSR_SIZE)
86 
87 /*
88  * PIO access using the DMC block directly (DMC)
89  */
90 #define	DMC_OFFSET(channel)		(DMA_CSR_SIZE * channel)
91 #define	TDMC_OFFSET(channel)		(TX_RNG_CFIG + DMA_CSR_SIZE * channel)
92 
93 #ifdef	SOLARIS
94 #ifndef	i386
95 #define	_BIT_FIELDS_BIG_ENDIAN		_BIT_FIELDS_HTOL
96 #else
97 #define	_BIT_FIELDS_LITTLE_ENDIAN	_BIT_FIELDS_LTOH
98 #endif
99 #else
100 #define	_BIT_FIELDS_LITTLE_ENDIAN	_LITTLE_ENDIAN_BITFIELD
101 #endif
102 
103 /*
104  * The following macros expect unsigned input values.
105  */
106 #define	TXDMA_CHANNEL_VALID(cn)		(cn < HXGE_MAX_TDCS)
107 
108 /*
109  * Logical device definitions.
110  */
111 #define	HXGE_INT_MAX_LD		32
112 #define	HXGE_INT_MAX_LDG	32
113 
114 #define	HXGE_RDMA_LD_START	0	/* 0 - 3 with 4 - 7 reserved */
115 #define	HXGE_TDMA_LD_START	8	/* 8 - 11 with 12 - 15 reserved */
116 #define	HXGE_VMAC_LD		16
117 #define	HXGE_PFC_LD		17
118 #define	HXGE_NMAC_LD		18
119 #define	HXGE_MBOX_LD_START	20	/* 20 - 23  for SW Mbox */
120 #define	HXGE_SYS_ERROR_LD	31
121 
122 #define	LDG_VALID(n)		(n < HXGE_INT_MAX_LDG)
123 #define	LD_VALID(n)		(n < HXGE_INT_MAX_LD)
124 #define	LD_RXDMA_LD_VALID(n)	(n < HXGE_MAX_RDCS)
125 #define	LD_TXDMA_LD_VALID(n)	(n >= HXGE_MAX_RDCS && \
126 					((n - HXGE_MAX_RDCS) < HXGE_MAX_TDCS)))
127 
128 #define	LD_TIMER_MAX		0x3f
129 #define	LD_INTTIMER_VALID(n)	(n <= LD_TIMER_MAX)
130 
131 /* System Interrupt Data */
132 #define	SID_VECTOR_MAX		0x1f
133 #define	SID_VECTOR_VALID(n)	(n <= SID_VECTOR_MAX)
134 
135 #define	LD_IM_MASK		0x00000003ULL
136 #define	LDGTITMRES_RES_MASK	0x000FFFFFULL
137 
138 #define	MIN_FRAME_SIZE		106	/* 68 byte min MTU + 38 byte header */
139 #define	MAX_FRAME_SIZE		9216
140 #define	STD_FRAME_SIZE		1522	/* 1518 + 4 = 5EE + 4 */
141 #define	HXGE_DEFAULT_MTU	1500
142 /*
143  * sizeof (struct ether_header) + ETHERFCSL + 4 + TX_PKT_HEADER_SIZE
144  * 12 + 6 + 4 + 16
145  */
146 #define	MTU_TO_FRAME_SIZE	38
147 
148 #ifdef	__cplusplus
149 }
150 #endif
151 
152 #endif	/* _SYS_HXGE_HXGE_DEFS_H */
153