xref: /illumos-gate/usr/src/uts/intel/sys/controlregs.h (revision 651a12cb)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved.
23  * Copyright 2018, Joyent, Inc.
24  * Copyright 2022 Tintri by DDN, Inc. All rights reserved.
25  * Copyright 2023 Oxide Computer Company
26  */
27 
28 #ifndef	_SYS_CONTROLREGS_H
29 #define	_SYS_CONTROLREGS_H
30 
31 #ifndef _ASM
32 #include <sys/types.h>
33 #endif
34 
35 #ifdef __cplusplus
36 extern "C" {
37 #endif
38 
39 /*
40  * This file describes the x86 architecture control registers which
41  * are part of the privileged architecture.
42  *
43  * Many of these definitions are shared between IA-32-style and
44  * AMD64-style processors.
45  */
46 
47 /* CR0 Register */
48 
49 #define	CR0_PG	0x80000000		/* paging enabled	*/
50 #define	CR0_CD	0x40000000		/* cache disable	*/
51 #define	CR0_NW	0x20000000		/* not writethrough	*/
52 #define	CR0_AM	0x00040000		/* alignment mask	*/
53 #define	CR0_WP	0x00010000		/* write protect	*/
54 #define	CR0_NE	0x00000020		/* numeric error	*/
55 #define	CR0_ET	0x00000010		/* extension type	*/
56 #define	CR0_TS	0x00000008		/* task switch		*/
57 #define	CR0_EM	0x00000004		/* emulation		*/
58 #define	CR0_MP	0x00000002		/* monitor coprocessor	*/
59 #define	CR0_PE	0x00000001		/* protection enabled	*/
60 
61 /* XX64 eliminate these compatibility defines */
62 
63 #define	CR0_CE	CR0_CD
64 #define	CR0_WT	CR0_NW
65 
66 #define	FMT_CR0	\
67 	"\20\40pg\37cd\36nw\35am\21wp\6ne\5et\4ts\3em\2mp\1pe"
68 
69 /*
70  * Set the FPU-related control bits to explain to the processor that
71  * we're managing FPU state:
72  * - set monitor coprocessor (allow TS bit to control FPU)
73  * - set numeric exception (disable IGNNE# mechanism)
74  * - set task switch (#nm on first fp instruction)
75  * - clear emulate math bit (cause we're not emulating!)
76  */
77 #define	CR0_ENABLE_FPU_FLAGS(cr)	\
78 	(((cr) | CR0_MP | CR0_NE | CR0_TS) & (uint32_t)~CR0_EM)
79 
80 /*
81  * Set the FPU-related control bits to explain to the processor that
82  * we're -not- managing FPU state:
83  * - set emulate (all fp instructions cause #nm)
84  * - clear monitor coprocessor (so fwait/wait doesn't #nm)
85  */
86 #define	CR0_DISABLE_FPU_FLAGS(cr)	\
87 	(((cr) | CR0_EM) & (uint32_t)~CR0_MP)
88 
89 /* CR3 Register */
90 
91 #define	CR3_PCD	0x00000010		/* cache disable		*/
92 #define	CR3_PWT 0x00000008		/* write through		*/
93 #if defined(_ASM)
94 #define	CR3_NOINVL_BIT	0x8000000000000000
95 #else
96 #define	CR3_NOINVL_BIT	0x8000000000000000ULL /* no invalidation	*/
97 #endif
98 #define	PCID_NONE	0x000		/* generic PCID			*/
99 #define	PCID_KERNEL	0x000		/* kernel's PCID		*/
100 #define	PCID_USER	0x001		/* user-space PCID		*/
101 
102 /* CR4 Register */
103 
104 #define	CR4_VME		0x0001		/* virtual-8086 mode extensions	*/
105 #define	CR4_PVI		0x0002		/* protected-mode virtual interrupts */
106 #define	CR4_TSD		0x0004		/* time stamp disable		*/
107 #define	CR4_DE		0x0008		/* debugging extensions		*/
108 #define	CR4_PSE		0x0010		/* page size extensions		*/
109 #define	CR4_PAE		0x0020		/* physical address extension	*/
110 #define	CR4_MCE		0x0040		/* machine check enable		*/
111 #define	CR4_PGE		0x0080		/* page global enable		*/
112 #define	CR4_PCE		0x0100		/* perf-monitoring counter enable */
113 #define	CR4_OSFXSR	0x0200		/* OS fxsave/fxrstor support	*/
114 #define	CR4_OSXMMEXCPT	0x0400		/* OS unmasked exception support */
115 #define	CR4_UMIP	0x0800		/* user-mode instruction prevention */
116 #define	CR4_LA57	0x1000		/* enable 57 bit Logical addressing */
117 #define	CR4_VMXE	0x2000		/* VMX enable */
118 #define	CR4_SMXE	0x4000		/* SMX enable */
119 					/* 0x8000 reserved */
120 #define	CR4_FSGSBASE	0x10000		/* FSGSBASE enable */
121 #define	CR4_PCIDE	0x20000		/* PCID enable */
122 #define	CR4_OSXSAVE	0x40000		/* OS xsave/xrestore support	*/
123 #define	CR4_SMEP	0x100000	/* NX for user pages in kernel */
124 #define	CR4_SMAP	0x200000	/* kernel can't access user pages */
125 #define	CR4_PKE		0x400000	/* protection key enable */
126 
127 #define	FMT_CR4						\
128 	"\20\27pke\26smap\25smep\23osxsav"		\
129 	"\22pcide\21fsgsbase\17smxe\16vmxe"		\
130 	"\15la57\14umip\13xmme\12fxsr\11pce\10pge"	\
131 	"\7mce\6pae\5pse\4de\3tsd\2pvi\1vme"
132 
133 /*
134  * Enable the SSE-related control bits to explain to the processor that
135  * we're managing XMM state and exceptions
136  */
137 #define	CR4_ENABLE_SSE_FLAGS(cr)	\
138 	((cr) | CR4_OSFXSR | CR4_OSXMMEXCPT)
139 
140 /*
141  * Disable the SSE-related control bits to explain to the processor
142  * that we're NOT managing XMM state
143  */
144 #define	CR4_DISABLE_SSE_FLAGS(cr)	\
145 	((cr) & ~(uint32_t)(CR4_OSFXSR | CR4_OSXMMEXCPT))
146 
147 /* Intel's SYSENTER configuration registers */
148 
149 #define	MSR_INTC_SEP_CS	0x174		/* kernel code selector MSR */
150 #define	MSR_INTC_SEP_ESP 0x175		/* kernel esp MSR */
151 #define	MSR_INTC_SEP_EIP 0x176		/* kernel eip MSR */
152 
153 /* Intel's microcode registers */
154 #define	MSR_INTC_UCODE_WRITE		0x79	/* microcode write */
155 #define	MSR_INTC_UCODE_REV		0x8b	/* microcode revision */
156 #define	INTC_UCODE_REV_SHIFT		32	/* Bits 63:32 */
157 
158 /* Intel's platform identification */
159 #define	MSR_INTC_PLATFORM_ID		0x17
160 #define	INTC_PLATFORM_ID_SHIFT		50	/* Bit 52:50 */
161 #define	INTC_PLATFORM_ID_MASK		0x7
162 
163 /* AMD's EFER register */
164 
165 #define	MSR_AMD_EFER	0xc0000080	/* extended feature enable MSR */
166 
167 #define	AMD_EFER_AIBRSE	0x200000	/* Automatic IBRS Enable */
168 #define	AMD_EFER_UAIE	0x100000	/* upper address ignore enable */
169 #define	AMD_EFER_INTWB	0x040000	/* interruptible wbinvd / wbnoinvd */
170 #define	AMD_EFER_MCOMMIT	0x020000 /* enable mcommit instr */
171 #define	AMD_EFER_TCE	0x008000	/* translation cache extension */
172 #define	AMD_EFER_FFXSR	0x004000	/* fast fxsave/fxrstor		*/
173 #define	AMD_EFER_LMSLE	0x002000	/* long mode segment limit enable */
174 #define	AMD_EFER_SVME	0x001000	/* svm enable			*/
175 #define	AMD_EFER_NXE	0x000800	/* no-execute enable		*/
176 #define	AMD_EFER_LMA	0x000400	/* long mode active (read-only)	*/
177 #define	AMD_EFER_LME	0x000100	/* long mode enable		*/
178 #define	AMD_EFER_SCE	0x000001	/* system call extensions	*/
179 
180 /* AMD's SYSCFG register */
181 
182 #define	MSR_AMD_SYSCFG	0xc0000010	/* system configuration MSR */
183 
184 #define	AMD_SYSCFG_TOM2	0x200000	/* MtrrTom2En */
185 #define	AMD_SYSCFG_MVDM	0x100000	/* MtrrVarDramEn */
186 #define	AMD_SYSCFG_MFDM	0x080000	/* MtrrFixDramModEn */
187 #define	AMD_SYSCFG_MFDE	0x040000	/* MtrrFixDramEn */
188 
189 #define	FMT_AMD_SYSCFG \
190 	"\20\26tom2\25mvdm\24mfdm\23mfde"
191 
192 /* AMD's syscall/sysret MSRs */
193 
194 #define	MSR_AMD_STAR	0xc0000081	/* %cs:%ss:%cs:%ss:%eip for syscall */
195 #define	MSR_AMD_LSTAR	0xc0000082	/* target %rip of 64-bit syscall */
196 #define	MSR_AMD_CSTAR	0xc0000083	/* target %rip of 32-bit syscall */
197 #define	MSR_AMD_SFMASK	0xc0000084	/* syscall flag mask */
198 
199 /* AMD's FS.base and GS.base MSRs */
200 
201 #define	MSR_AMD_FSBASE	0xc0000100	/* 64-bit base address for %fs */
202 #define	MSR_AMD_GSBASE	0xc0000101	/* 64-bit base address for %gs */
203 #define	MSR_AMD_KGSBASE	0xc0000102	/* swapgs swaps this with gsbase */
204 #define	MSR_AMD_TSCAUX	0xc0000103	/* %ecx value on rdtscp insn */
205 
206 
207 /* AMD's SVM MSRs */
208 
209 #define	MSR_AMD_VM_CR		0xc0010114 /* SVM global control */
210 #define	MSR_AMD_VM_HSAVE_PA	0xc0010117 /* SVM host save area address */
211 
212 #define	AMD_VM_CR_DPD		(1 << 0)
213 #define	AMD_VM_CR_R_INIT	(1 << 1)
214 #define	AMD_VM_CR_DIS_A20M	(1 << 2)
215 #define	AMD_VM_CR_LOCK		(1 << 3)
216 #define	AMD_VM_CR_SVMDIS	(1 << 4)
217 
218 /* AMD's configuration MSRs, weakly documented in the revision guide */
219 
220 #define	MSR_AMD_DC_CFG	0xc0011022
221 
222 #define	AMD_DC_CFG_DIS_CNV_WC_SSO	(UINT64_C(1) << 3)
223 #define	AMD_DC_CFG_DIS_SMC_CHK_BUF	(UINT64_C(1) << 10)
224 
225 /* AMD's HWCR MSR */
226 
227 #define	MSR_AMD_HWCR	0xc0010015
228 
229 #define	AMD_HWCR_TLBCACHEDIS		(UINT64_C(1) << 3)
230 #define	AMD_HWCR_FFDIS			0x00040	/* disable TLB Flush Filter */
231 #define	AMD_HWCR_MCI_STATUS_WREN	0x40000	/* enable write of MCi_STATUS */
232 
233 /* AMD's NorthBridge Config MSR, SHOULD ONLY BE WRITTEN TO BY BIOS */
234 
235 #define	MSR_AMD_NB_CFG	0xc001001f
236 
237 #define	AMD_NB_CFG_SRQ_HEARTBEAT	(UINT64_C(1) << 20)
238 #define	AMD_NB_CFG_SRQ_SPR		(UINT64_C(1) << 32)
239 
240 #define	MSR_AMD_BU_CFG	0xc0011023
241 
242 #define	AMD_BU_CFG_E298			(UINT64_C(1) << 1)
243 
244 /*
245  * This MSR exists on families, 10h, 12h+ for AMD. This controls instruction
246  * decoding. Most notably, for the AMD variant of retpolines, we must improve
247  * the serializability of lfence for the lfence based method to work.
248  */
249 #define	MSR_AMD_DE_CFG	0xc0011029
250 
251 #define	AMD_DE_CFG_E721			(1UL << 0)
252 #define	AMD_DE_CFG_LFENCE_DISPATCH	(1UL << 1)
253 
254 /* AMD's osvw MSRs */
255 #define	MSR_AMD_OSVW_ID_LEN		0xc0010140
256 #define	MSR_AMD_OSVW_STATUS		0xc0010141
257 
258 
259 #define	OSVW_ID_LEN_MASK		0xffffULL
260 #define	OSVW_ID_CNT_PER_MSR		64
261 
262 /*
263  * Enable PCI Extended Configuration Space (ECS) on Greyhound
264  */
265 #define	AMD_GH_NB_CFG_EN_ECS		(UINT64_C(1) << 46)
266 
267 /* AMD microcode patch loader */
268 #define	MSR_AMD_PATCHLEVEL	0x8b
269 #define	MSR_AMD_PATCHLOADER	0xc0010020
270 
271 #ifdef __cplusplus
272 }
273 #endif
274 
275 #endif	/* !_SYS_CONTROLREGS_H */
276