xref: /illumos-gate/usr/src/uts/common/io/mr_sas/mr_sas.h (revision 0bb3cf0b)
1 /*
2  * mr_sas.h: header for mr_sas
3  *
4  * Solaris MegaRAID driver for SAS2.0 controllers
5  * Copyright (c) 2008-2012, LSI Logic Corporation.
6  * All rights reserved.
7  *
8  * Version:
9  * Author:
10  *		Swaminathan K S
11  *		Arun Chandrashekhar
12  *		Manju R
13  *		Rasheed
14  *		Shakeel Bukhari
15  *
16  * Redistribution and use in source and binary forms, with or without
17  * modification, are permitted provided that the following conditions are met:
18  *
19  * 1. Redistributions of source code must retain the above copyright notice,
20  *    this list of conditions and the following disclaimer.
21  *
22  * 2. Redistributions in binary form must reproduce the above copyright notice,
23  *    this list of conditions and the following disclaimer in the documentation
24  *    and/or other materials provided with the distribution.
25  *
26  * 3. Neither the name of the author nor the names of its contributors may be
27  *    used to endorse or promote products derived from this software without
28  *    specific prior written permission.
29  *
30  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
31  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
32  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
33  * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
34  * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
35  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
36  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
37  * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
38  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
39  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
40  * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
41  * DAMAGE.
42  */
43 
44 /*
45  * Copyright (c) 2009, 2010, Oracle and/or its affiliates. All rights reserved.
46  * Copyright 2013 Nexenta Systems, Inc.  All rights reserved.
47  * Copyright 2015 Garrett D'Amore <garrett@damore.org>
48  * Copyright 2017 Citrus IT Limited. All rights reserved.
49  */
50 
51 #ifndef	_MR_SAS_H_
52 #define	_MR_SAS_H_
53 
54 #ifdef	__cplusplus
55 extern "C" {
56 #endif
57 
58 #include <sys/scsi/scsi.h>
59 #include "mr_sas_list.h"
60 #include "ld_pd_map.h"
61 
62 /*
63  * MegaRAID SAS2.0 Driver meta data
64  */
65 #define	MRSAS_VERSION				"6.503.00.00ILLUMOS-20170524"
66 #define	MRSAS_RELDATE				"May 24, 2017"
67 
68 #define	MRSAS_TRUE				1
69 #define	MRSAS_FALSE				0
70 
71 #define	ADAPTER_RESET_NOT_REQUIRED		0
72 #define	ADAPTER_RESET_REQUIRED			1
73 
74 /*
75  * MegaRAID SAS2.0 device id conversion definitions.
76  */
77 #define	INST2LSIRDCTL(x)		((x) << INST_MINOR_SHIFT)
78 #define	MRSAS_GET_BOUNDARY_ALIGNED_LEN(len, new_len, boundary_len)  { \
79 	int rem; \
80 	rem = (len / boundary_len); \
81 	if ((rem * boundary_len) != len) { \
82 		new_len = len + ((rem + 1) * boundary_len - len); \
83 	} else { \
84 		new_len = len; \
85 	} \
86 }
87 
88 
89 /*
90  * MegaRAID SAS2.0 supported controllers
91  */
92 
93 /* Skinny */
94 #define	PCI_DEVICE_ID_LSI_SKINNY		0x0071
95 #define	PCI_DEVICE_ID_LSI_SKINNY_NEW		0x0073
96 /* Liberator series (Gen2) */
97 #define	PCI_DEVICE_ID_LSI_2108VDE		0x0078
98 #define	PCI_DEVICE_ID_LSI_2108V			0x0079
99 /* Thunderbolt series */
100 #define	PCI_DEVICE_ID_LSI_TBOLT			0x005b
101 /* Invader series (Gen3) */
102 #define	PCI_DEVICE_ID_LSI_INVADER		0x005d
103 #define	PCI_DEVICE_ID_LSI_FURY			0x005f
104 #define	PCI_DEVICE_ID_LSI_INTRUDER		0x00ce
105 #define	PCI_DEVICE_ID_LSI_INTRUDER_24		0x00cf
106 #define	PCI_DEVICE_ID_LSI_CUTLASS_52		0x0052
107 #define	PCI_DEVICE_ID_LSI_CUTLASS_53		0x0053
108 /* Ventura series not yet supported */
109 
110 /*
111  * Register Index for 2108 Controllers.
112  */
113 #define	REGISTER_SET_IO_2108			(2)
114 
115 #define	MRSAS_MAX_SGE_CNT			0x50
116 #define	MRSAS_APP_RESERVED_CMDS			32
117 #define	MRSAS_APP_MIN_RESERVED_CMDS		4
118 
119 #define	MRSAS_IOCTL_DRIVER			0x12341234
120 #define	MRSAS_IOCTL_FIRMWARE			0x12345678
121 #define	MRSAS_IOCTL_AEN				0x87654321
122 
123 #define	MRSAS_1_SECOND				1000000
124 
125 #define	UNCONFIGURED_GOOD			0x0
126 #define	PD_SYSTEM				0x40
127 #define	MR_EVT_PD_STATE_CHANGE			0x0072
128 #define	MR_EVT_PD_REMOVED_EXT		0x00f8
129 #define	MR_EVT_PD_INSERTED_EXT		0x00f7
130 #define	MR_DCMD_PD_GET_INFO			0x02020000
131 #define	MRSAS_TBOLT_PD_LUN		1
132 #define	MRSAS_TBOLT_PD_TGT_MAX	255
133 #define	MRSAS_TBOLT_GET_PD_MAX(s)	((s)->mr_tbolt_pd_max)
134 
135 /* Raid Context Flags */
136 #define	MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_SHIFT 0x4
137 #define	MR_RAID_CTX_RAID_FLAGS_IO_SUB_TYPE_MASK 0x30
138 typedef enum MR_RAID_FLAGS_IO_SUB_TYPE {
139 	MR_RAID_FLAGS_IO_SUB_TYPE_NONE = 0,
140 	MR_RAID_FLAGS_IO_SUB_TYPE_SYSTEM_PD = 1
141 } MR_RAID_FLAGS_IO_SUB_TYPE;
142 
143 /* Dynamic Enumeration Flags */
144 #define	MRSAS_LD_LUN		0
145 #define	WWN_STRLEN		17
146 #define	LD_SYNC_BIT	1
147 #define	LD_SYNC_SHIFT	14
148 /* ThunderBolt (TB) specific */
149 #define	MRSAS_THUNDERBOLT_MSG_SIZE		256
150 #define	MRSAS_THUNDERBOLT_MAX_COMMANDS		1024
151 #define	MRSAS_THUNDERBOLT_MAX_REPLY_COUNT	1024
152 #define	MRSAS_THUNDERBOLT_REPLY_SIZE		8
153 #define	MRSAS_THUNDERBOLT_MAX_CHAIN_COUNT	1
154 
155 #define	MPI2_FUNCTION_PASSTHRU_IO_REQUEST	0xF0
156 #define	MPI2_FUNCTION_LD_IO_REQUEST		0xF1
157 
158 #define	MR_EVT_LD_FAST_PATH_IO_STATUS_CHANGED	(0xFFFF)
159 
160 #define	MR_INTERNAL_MFI_FRAMES_SMID		1
161 #define	MR_CTRL_EVENT_WAIT_SMID			2
162 #define	MR_INTERNAL_DRIVER_RESET_SMID		3
163 
164 
165 /*
166  * =====================================
167  * MegaRAID SAS2.0 MFI firmware definitions
168  * =====================================
169  */
170 /*
171  * MFI stands for  MegaRAID SAS2.0 FW Interface. This is just a moniker for
172  * protocol between the software and firmware. Commands are issued using
173  * "message frames"
174  */
175 
176 /*
177  * FW posts its state in upper 4 bits of outbound_msg_0 register
178  */
179 #define	MFI_STATE_MASK				0xF0000000
180 #define	MFI_STATE_UNDEFINED			0x00000000
181 #define	MFI_STATE_BB_INIT			0x10000000
182 #define	MFI_STATE_FW_INIT			0x40000000
183 #define	MFI_STATE_WAIT_HANDSHAKE		0x60000000
184 #define	MFI_STATE_FW_INIT_2			0x70000000
185 #define	MFI_STATE_DEVICE_SCAN			0x80000000
186 #define	MFI_STATE_BOOT_MESSAGE_PENDING		0x90000000
187 #define	MFI_STATE_FLUSH_CACHE			0xA0000000
188 #define	MFI_STATE_READY				0xB0000000
189 #define	MFI_STATE_OPERATIONAL			0xC0000000
190 #define	MFI_STATE_FAULT				0xF0000000
191 
192 #define	MRMFI_FRAME_SIZE			64
193 
194 /*
195  * During FW init, clear pending cmds & reset state using inbound_msg_0
196  *
197  * ABORT	: Abort all pending cmds
198  * READY	: Move from OPERATIONAL to READY state; discard queue info
199  * MFIMODE	: Discard (possible) low MFA posted in 64-bit mode (??)
200  * CLR_HANDSHAKE: FW is waiting for HANDSHAKE from BIOS or Driver
201  */
202 #define	MFI_INIT_ABORT				0x00000001
203 #define	MFI_INIT_READY				0x00000002
204 #define	MFI_INIT_MFIMODE			0x00000004
205 #define	MFI_INIT_CLEAR_HANDSHAKE		0x00000008
206 #define	MFI_INIT_HOTPLUG			0x00000010
207 #define	MFI_STOP_ADP				0x00000020
208 #define	MFI_RESET_FLAGS		MFI_INIT_READY|MFI_INIT_MFIMODE|MFI_INIT_ABORT
209 
210 /*
211  * MFI frame flags
212  */
213 #define	MFI_FRAME_POST_IN_REPLY_QUEUE		0x0000
214 #define	MFI_FRAME_DONT_POST_IN_REPLY_QUEUE	0x0001
215 #define	MFI_FRAME_SGL32				0x0000
216 #define	MFI_FRAME_SGL64				0x0002
217 #define	MFI_FRAME_SENSE32			0x0000
218 #define	MFI_FRAME_SENSE64			0x0004
219 #define	MFI_FRAME_DIR_NONE			0x0000
220 #define	MFI_FRAME_DIR_WRITE			0x0008
221 #define	MFI_FRAME_DIR_READ			0x0010
222 #define	MFI_FRAME_DIR_BOTH			0x0018
223 #define	MFI_FRAME_IEEE				0x0020
224 
225 /*
226  * Definition for cmd_status
227  */
228 #define	MFI_CMD_STATUS_POLL_MODE		0xFF
229 #define	MFI_CMD_STATUS_SYNC_MODE		0xFF
230 
231 /*
232  * MFI command opcodes
233  */
234 #define	MFI_CMD_OP_INIT				0x00
235 #define	MFI_CMD_OP_LD_READ			0x01
236 #define	MFI_CMD_OP_LD_WRITE			0x02
237 #define	MFI_CMD_OP_LD_SCSI			0x03
238 #define	MFI_CMD_OP_PD_SCSI			0x04
239 #define	MFI_CMD_OP_DCMD				0x05
240 #define	MFI_CMD_OP_ABORT			0x06
241 #define	MFI_CMD_OP_SMP				0x07
242 #define	MFI_CMD_OP_STP				0x08
243 
244 #define	MR_DCMD_CTRL_GET_INFO			0x01010000
245 
246 #define	MR_DCMD_CTRL_CACHE_FLUSH		0x01101000
247 #define	MR_FLUSH_CTRL_CACHE			0x01
248 #define	MR_FLUSH_DISK_CACHE			0x02
249 
250 #define	MR_DCMD_CTRL_SHUTDOWN			0x01050000
251 #define	MRSAS_ENABLE_DRIVE_SPINDOWN		0x01
252 
253 #define	MR_DCMD_CTRL_EVENT_GET_INFO		0x01040100
254 #define	MR_DCMD_CTRL_EVENT_GET			0x01040300
255 #define	MR_DCMD_CTRL_EVENT_WAIT			0x01040500
256 #define	MR_DCMD_LD_GET_PROPERTIES		0x03030000
257 
258 /*
259  * Solaris Specific MAX values
260  */
261 #define	MAX_SGL					24
262 
263 /*
264  * MFI command completion codes
265  */
266 enum MFI_STAT {
267 	MFI_STAT_OK				= 0x00,
268 	MFI_STAT_INVALID_CMD			= 0x01,
269 	MFI_STAT_INVALID_DCMD			= 0x02,
270 	MFI_STAT_INVALID_PARAMETER		= 0x03,
271 	MFI_STAT_INVALID_SEQUENCE_NUMBER	= 0x04,
272 	MFI_STAT_ABORT_NOT_POSSIBLE		= 0x05,
273 	MFI_STAT_APP_HOST_CODE_NOT_FOUND	= 0x06,
274 	MFI_STAT_APP_IN_USE			= 0x07,
275 	MFI_STAT_APP_NOT_INITIALIZED		= 0x08,
276 	MFI_STAT_ARRAY_INDEX_INVALID		= 0x09,
277 	MFI_STAT_ARRAY_ROW_NOT_EMPTY		= 0x0a,
278 	MFI_STAT_CONFIG_RESOURCE_CONFLICT	= 0x0b,
279 	MFI_STAT_DEVICE_NOT_FOUND		= 0x0c,
280 	MFI_STAT_DRIVE_TOO_SMALL		= 0x0d,
281 	MFI_STAT_FLASH_ALLOC_FAIL		= 0x0e,
282 	MFI_STAT_FLASH_BUSY			= 0x0f,
283 	MFI_STAT_FLASH_ERROR			= 0x10,
284 	MFI_STAT_FLASH_IMAGE_BAD		= 0x11,
285 	MFI_STAT_FLASH_IMAGE_INCOMPLETE		= 0x12,
286 	MFI_STAT_FLASH_NOT_OPEN			= 0x13,
287 	MFI_STAT_FLASH_NOT_STARTED		= 0x14,
288 	MFI_STAT_FLUSH_FAILED			= 0x15,
289 	MFI_STAT_HOST_CODE_NOT_FOUNT		= 0x16,
290 	MFI_STAT_LD_CC_IN_PROGRESS		= 0x17,
291 	MFI_STAT_LD_INIT_IN_PROGRESS		= 0x18,
292 	MFI_STAT_LD_LBA_OUT_OF_RANGE		= 0x19,
293 	MFI_STAT_LD_MAX_CONFIGURED		= 0x1a,
294 	MFI_STAT_LD_NOT_OPTIMAL			= 0x1b,
295 	MFI_STAT_LD_RBLD_IN_PROGRESS		= 0x1c,
296 	MFI_STAT_LD_RECON_IN_PROGRESS		= 0x1d,
297 	MFI_STAT_LD_WRONG_RAID_LEVEL		= 0x1e,
298 	MFI_STAT_MAX_SPARES_EXCEEDED		= 0x1f,
299 	MFI_STAT_MEMORY_NOT_AVAILABLE		= 0x20,
300 	MFI_STAT_MFC_HW_ERROR			= 0x21,
301 	MFI_STAT_NO_HW_PRESENT			= 0x22,
302 	MFI_STAT_NOT_FOUND			= 0x23,
303 	MFI_STAT_NOT_IN_ENCL			= 0x24,
304 	MFI_STAT_PD_CLEAR_IN_PROGRESS		= 0x25,
305 	MFI_STAT_PD_TYPE_WRONG			= 0x26,
306 	MFI_STAT_PR_DISABLED			= 0x27,
307 	MFI_STAT_ROW_INDEX_INVALID		= 0x28,
308 	MFI_STAT_SAS_CONFIG_INVALID_ACTION	= 0x29,
309 	MFI_STAT_SAS_CONFIG_INVALID_DATA	= 0x2a,
310 	MFI_STAT_SAS_CONFIG_INVALID_PAGE	= 0x2b,
311 	MFI_STAT_SAS_CONFIG_INVALID_TYPE	= 0x2c,
312 	MFI_STAT_SCSI_DONE_WITH_ERROR		= 0x2d,
313 	MFI_STAT_SCSI_IO_FAILED			= 0x2e,
314 	MFI_STAT_SCSI_RESERVATION_CONFLICT	= 0x2f,
315 	MFI_STAT_SHUTDOWN_FAILED		= 0x30,
316 	MFI_STAT_TIME_NOT_SET			= 0x31,
317 	MFI_STAT_WRONG_STATE			= 0x32,
318 	MFI_STAT_LD_OFFLINE			= 0x33,
319 	MFI_STAT_INVALID_STATUS			= 0xFF
320 };
321 
322 enum MR_EVT_CLASS {
323 	MR_EVT_CLASS_DEBUG		= -2,
324 	MR_EVT_CLASS_PROGRESS		= -1,
325 	MR_EVT_CLASS_INFO		=  0,
326 	MR_EVT_CLASS_WARNING		=  1,
327 	MR_EVT_CLASS_CRITICAL		=  2,
328 	MR_EVT_CLASS_FATAL		=  3,
329 	MR_EVT_CLASS_DEAD		=  4
330 };
331 
332 enum MR_EVT_LOCALE {
333 	MR_EVT_LOCALE_LD		= 0x0001,
334 	MR_EVT_LOCALE_PD		= 0x0002,
335 	MR_EVT_LOCALE_ENCL		= 0x0004,
336 	MR_EVT_LOCALE_BBU		= 0x0008,
337 	MR_EVT_LOCALE_SAS		= 0x0010,
338 	MR_EVT_LOCALE_CTRL		= 0x0020,
339 	MR_EVT_LOCALE_CONFIG		= 0x0040,
340 	MR_EVT_LOCALE_CLUSTER		= 0x0080,
341 	MR_EVT_LOCALE_ALL		= 0xffff
342 };
343 
344 enum MR_EVT_ARGS {
345 	MR_EVT_ARGS_NONE,
346 	MR_EVT_ARGS_CDB_SENSE,
347 	MR_EVT_ARGS_LD,
348 	MR_EVT_ARGS_LD_COUNT,
349 	MR_EVT_ARGS_LD_LBA,
350 	MR_EVT_ARGS_LD_OWNER,
351 	MR_EVT_ARGS_LD_LBA_PD_LBA,
352 	MR_EVT_ARGS_LD_PROG,
353 	MR_EVT_ARGS_LD_STATE,
354 	MR_EVT_ARGS_LD_STRIP,
355 	MR_EVT_ARGS_PD,
356 	MR_EVT_ARGS_PD_ERR,
357 	MR_EVT_ARGS_PD_LBA,
358 	MR_EVT_ARGS_PD_LBA_LD,
359 	MR_EVT_ARGS_PD_PROG,
360 	MR_EVT_ARGS_PD_STATE,
361 	MR_EVT_ARGS_PCI,
362 	MR_EVT_ARGS_RATE,
363 	MR_EVT_ARGS_STR,
364 	MR_EVT_ARGS_TIME,
365 	MR_EVT_ARGS_ECC
366 };
367 
368 #define	MR_EVT_CFG_CLEARED		0x0004
369 #define	MR_EVT_LD_CREATED		0x008a
370 #define	MR_EVT_LD_DELETED		0x008b
371 #define	MR_EVT_CFG_FP_CHANGE		0x017B
372 
373 enum LD_STATE {
374 	LD_OFFLINE		= 0,
375 	LD_PARTIALLY_DEGRADED	= 1,
376 	LD_DEGRADED		= 2,
377 	LD_OPTIMAL		= 3,
378 	LD_INVALID		= 0xFF
379 };
380 
381 enum MRSAS_EVT {
382 	MRSAS_EVT_CONFIG_TGT	= 0,
383 	MRSAS_EVT_UNCONFIG_TGT	= 1,
384 	MRSAS_EVT_UNCONFIG_SMP	= 2
385 };
386 
387 #define	DMA_OBJ_ALLOCATED	1
388 #define	DMA_OBJ_REALLOCATED	2
389 #define	DMA_OBJ_FREED		3
390 
391 /*
392  * dma_obj_t	- Our DMA object
393  * @param buffer	: kernel virtual address
394  * @param size		: size of the data to be allocated
395  * @param acc_handle	: access handle
396  * @param dma_handle	: dma handle
397  * @param dma_cookie	: scatter-gather list
398  * @param dma_attr	: dma attributes for this buffer
399  *
400  * Our DMA object. The caller must initialize the size and dma attributes
401  * (dma_attr) fields before allocating the resources.
402  */
403 typedef struct {
404 	caddr_t			buffer;
405 	uint32_t		size;
406 	ddi_acc_handle_t	acc_handle;
407 	ddi_dma_handle_t	dma_handle;
408 	ddi_dma_cookie_t	dma_cookie[MRSAS_MAX_SGE_CNT];
409 	ddi_dma_attr_t		dma_attr;
410 	uint8_t			status;
411 	uint8_t			reserved[3];
412 } dma_obj_t;
413 
414 struct mrsas_eventinfo {
415 	struct mrsas_instance	*instance;
416 	int 			tgt;
417 	int 			lun;
418 	int 			event;
419 	uint64_t		wwn;
420 };
421 
422 struct mrsas_ld {
423 	dev_info_t		*dip;
424 	uint8_t 		lun_type;
425 	uint8_t			flag;
426 	uint8_t 		reserved[2];
427 };
428 
429 
430 struct mrsas_tbolt_pd {
431 	dev_info_t		*dip;
432 	uint8_t 		lun_type;
433 	uint8_t 		dev_id;
434 	uint8_t 		flag;
435 	uint8_t 		reserved;
436 };
437 struct mrsas_tbolt_pd_info {
438 	uint16_t	deviceId;
439 	uint16_t	seqNum;
440 	uint8_t		inquiryData[96];
441 	uint8_t		vpdPage83[64];
442 	uint8_t		notSupported;
443 	uint8_t		scsiDevType;
444 	uint8_t		a;
445 	uint8_t		device_speed;
446 	uint32_t	mediaerrcnt;
447 	uint32_t	other;
448 	uint32_t	pred;
449 	uint32_t	lastpred;
450 	uint16_t	fwState;
451 	uint8_t		disabled;
452 	uint8_t		linkspwwd;
453 	uint32_t	ddfType;
454 	struct {
455 		uint8_t	count;
456 		uint8_t	isPathBroken;
457 		uint8_t	connectorIndex[2];
458 		uint8_t	reserved[4];
459 		uint64_t sasAddr[2];
460 		uint8_t	reserved2[16];
461 	} pathInfo;
462 };
463 
464 typedef struct mrsas_instance {
465 	uint32_t	*producer;
466 	uint32_t	*consumer;
467 
468 	uint32_t	*reply_queue;
469 	dma_obj_t	mfi_internal_dma_obj;
470 	uint16_t	adapterresetinprogress;
471 	uint16_t	deadadapter;
472 	/* ThunderBolt (TB) specific */
473 	dma_obj_t	mpi2_frame_pool_dma_obj;
474 	dma_obj_t	request_desc_dma_obj;
475 	dma_obj_t	reply_desc_dma_obj;
476 	dma_obj_t	ld_map_obj[2];
477 
478 	uint8_t		init_id;
479 	uint8_t		flag_ieee;
480 	uint8_t		disable_online_ctrl_reset;
481 	uint8_t		fw_fault_count_after_ocr;
482 
483 	uint16_t	max_num_sge;
484 	uint16_t	max_fw_cmds;
485 	uint32_t	max_sectors_per_req;
486 
487 	struct mrsas_cmd **cmd_list;
488 
489 	mlist_t		cmd_pool_list;
490 	kmutex_t	cmd_pool_mtx;
491 	kmutex_t	sync_map_mtx;
492 
493 	mlist_t		app_cmd_pool_list;
494 	kmutex_t	app_cmd_pool_mtx;
495 	mlist_t		cmd_app_pool_list;
496 	kmutex_t	cmd_app_pool_mtx;
497 
498 
499 	mlist_t		cmd_pend_list;
500 	kmutex_t	cmd_pend_mtx;
501 
502 	dma_obj_t	mfi_evt_detail_obj;
503 	struct mrsas_cmd *aen_cmd;
504 
505 	uint32_t	aen_seq_num;
506 	uint32_t	aen_class_locale_word;
507 
508 	scsi_hba_tran_t		*tran;
509 
510 	kcondvar_t	int_cmd_cv;
511 	kmutex_t	int_cmd_mtx;
512 
513 	kcondvar_t	aen_cmd_cv;
514 	kmutex_t	aen_cmd_mtx;
515 
516 	kcondvar_t	abort_cmd_cv;
517 	kmutex_t	abort_cmd_mtx;
518 
519 	kmutex_t	reg_write_mtx;
520 	kmutex_t	chip_mtx;
521 
522 	dev_info_t		*dip;
523 	ddi_acc_handle_t	pci_handle;
524 
525 	timeout_id_t	timeout_id;
526 	uint32_t	unique_id;
527 	uint16_t	fw_outstanding;
528 	caddr_t		regmap;
529 	ddi_acc_handle_t	regmap_handle;
530 	uint8_t		isr_level;
531 	ddi_iblock_cookie_t	iblock_cookie;
532 	ddi_iblock_cookie_t	soft_iblock_cookie;
533 	ddi_softintr_t		soft_intr_id;
534 	uint8_t		softint_running;
535 	uint8_t		tbolt_softint_running;
536 	kmutex_t	completed_pool_mtx;
537 	mlist_t		completed_pool_list;
538 
539 	caddr_t		internal_buf;
540 	uint32_t	internal_buf_dmac_add;
541 	uint32_t	internal_buf_size;
542 
543 	uint16_t	vendor_id;
544 	uint16_t	device_id;
545 	uint16_t	subsysvid;
546 	uint16_t	subsysid;
547 	int		instance;
548 	int		baseaddress;
549 	char		iocnode[16];
550 
551 	int		fm_capabilities;
552 	/*
553 	 * Driver resources unroll flags.  The flag is set for resources that
554 	 * are needed to be free'd at detach() time.
555 	 */
556 	struct _unroll {
557 		uint8_t softs;		/* The software state was allocated. */
558 		uint8_t regs;		/* Controller registers mapped. */
559 		uint8_t intr;		/* Interrupt handler added. */
560 		uint8_t reqs;		/* Request structs allocated. */
561 		uint8_t mutexs;		/* Mutex's allocated. */
562 		uint8_t taskq;		/* Task q's created. */
563 		uint8_t tran;		/* Tran struct allocated */
564 		uint8_t tranSetup;	/* Tran attached to the ddi. */
565 		uint8_t devctl;		/* Device nodes for cfgadm created. */
566 		uint8_t scsictl;	/* Device nodes for cfgadm created. */
567 		uint8_t ioctl;		/* Device nodes for ioctl's created. */
568 		uint8_t timer;		/* Timer started. */
569 		uint8_t aenPend;	/* AEN cmd pending f/w. */
570 		uint8_t mapUpdate_pend; /* LD MAP update cmd pending f/w. */
571 		uint8_t soft_isr;	/* Soft interrupt handler allocated. */
572 		uint8_t ldlist_buff;	/* Logical disk list allocated. */
573 		uint8_t pdlist_buff;	/* Physical disk list allocated. */
574 		uint8_t syncCmd;	/* Sync map command allocated. */
575 		uint8_t verBuff;	/* 2108 MFI buffer allocated. */
576 		uint8_t alloc_space_mfi;  /* Allocated space for 2108 MFI. */
577 		uint8_t alloc_space_mpi2; /* Allocated space for 2208 MPI2. */
578 	} unroll;
579 
580 
581 	/* function template pointer */
582 	struct mrsas_function_template *func_ptr;
583 
584 
585 	/* MSI interrupts specific */
586 	ddi_intr_handle_t *intr_htable;		/* Interrupt handle array */
587 	size_t		intr_htable_size;	/* Int. handle array size */
588 	int		intr_type;
589 	int		intr_cnt;
590 	uint_t		intr_pri;
591 	int		intr_cap;
592 
593 	ddi_taskq_t	*taskq;
594 	struct mrsas_ld	*mr_ld_list;
595 	kmutex_t	config_dev_mtx;
596 	/* ThunderBolt (TB) specific */
597 	ddi_softintr_t	tbolt_soft_intr_id;
598 
599 	uint32_t	mr_tbolt_pd_max;
600 	struct mrsas_tbolt_pd *mr_tbolt_pd_list;
601 
602 	uint8_t		fast_path_io;
603 
604 	uint8_t		skinny;
605 	uint8_t		tbolt;
606 	uint8_t		gen3;
607 	uint16_t	reply_read_index;
608 	uint16_t	reply_size; 		/* Single Reply struct size */
609 	uint16_t	raid_io_msg_size; 	/* Single message size */
610 	uint32_t	io_request_frames_phy;
611 	uint8_t 	*io_request_frames;
612 	/* Virtual address of request desc frame pool */
613 	MRSAS_REQUEST_DESCRIPTOR_UNION	*request_message_pool;
614 	/* Physical address of request desc frame pool */
615 	uint32_t	request_message_pool_phy;
616 	/* Virtual address of reply Frame */
617 	MPI2_REPLY_DESCRIPTORS_UNION	*reply_frame_pool;
618 	/* Physical address of reply Frame */
619 	uint32_t	reply_frame_pool_phy;
620 	uint8_t		*reply_pool_limit;	/* Last reply frame address */
621 	/* Physical address of Last reply frame */
622 	uint32_t	reply_pool_limit_phy;
623 	uint32_t	reply_q_depth;		/* Reply Queue Depth */
624 	uint8_t		max_sge_in_main_msg;
625 	uint8_t		max_sge_in_chain;
626 	uint8_t    	chain_offset_io_req;
627 	uint8_t		chain_offset_mpt_msg;
628 	MR_FW_RAID_MAP_ALL *ld_map[2];
629 	uint32_t 	ld_map_phy[2];
630 	uint32_t	size_map_info;
631 	uint64_t 	map_id;
632 	LD_LOAD_BALANCE_INFO load_balance_info[MAX_LOGICAL_DRIVES];
633 	struct mrsas_cmd *map_update_cmd;
634 	uint32_t	SyncRequired;
635 	kmutex_t	ocr_flags_mtx;
636 	dma_obj_t	drv_ver_dma_obj;
637 } mrsas_t;
638 
639 
640 /*
641  * Function templates for various controller specific functions
642  */
643 struct mrsas_function_template {
644 	uint32_t (*read_fw_status_reg)(struct mrsas_instance *);
645 	void (*issue_cmd)(struct mrsas_cmd *, struct mrsas_instance *);
646 	int (*issue_cmd_in_sync_mode)(struct mrsas_instance *,
647 	    struct mrsas_cmd *);
648 	int (*issue_cmd_in_poll_mode)(struct mrsas_instance *,
649 	    struct mrsas_cmd *);
650 	void (*enable_intr)(struct mrsas_instance *);
651 	void (*disable_intr)(struct mrsas_instance *);
652 	int (*intr_ack)(struct mrsas_instance *);
653 	int (*init_adapter)(struct mrsas_instance *);
654 /*	int (*reset_adapter)(struct mrsas_instance *); */
655 };
656 
657 /*
658  * ### Helper routines ###
659  */
660 
661 /*
662  * con_log() - console log routine
663  * @param level		: indicates the severity of the message.
664  * @fparam mt		: format string
665  *
666  * con_log displays the error messages on the console based on the current
667  * debug level. Also it attaches the appropriate kernel severity level with
668  * the message.
669  *
670  *
671  * console messages debug levels
672  */
673 #define	CL_NONE		0	/* No debug information */
674 #define	CL_ANN		1	/* print unconditionally, announcements */
675 #define	CL_ANN1		2	/* No-op  */
676 #define	CL_DLEVEL1	3	/* debug level 1, informative */
677 #define	CL_DLEVEL2	4	/* debug level 2, verbose */
678 #define	CL_DLEVEL3	5	/* debug level 3, very verbose */
679 
680 #ifdef __SUNPRO_C
681 #define	__func__ ""
682 #endif
683 
684 #define	con_log(level, fmt) { if (debug_level_g >= level) cmn_err fmt; }
685 
686 /*
687  * ### SCSA definitions ###
688  */
689 #define	PKT2TGT(pkt)	((pkt)->pkt_address.a_target)
690 #define	PKT2LUN(pkt)	((pkt)->pkt_address.a_lun)
691 #define	PKT2TRAN(pkt)	((pkt)->pkt_adress.a_hba_tran)
692 #define	ADDR2TRAN(ap)	((ap)->a_hba_tran)
693 
694 #define	TRAN2MR(tran)	(struct mrsas_instance *)(tran)->tran_hba_private)
695 #define	ADDR2MR(ap)	(TRAN2MR(ADDR2TRAN(ap))
696 
697 #define	PKT2CMD(pkt)	((struct scsa_cmd *)(pkt)->pkt_ha_private)
698 #define	CMD2PKT(sp)	((sp)->cmd_pkt)
699 #define	PKT2REQ(pkt)	(&(PKT2CMD(pkt)->request))
700 
701 #define	CMD2ADDR(cmd)	(&CMD2PKT(cmd)->pkt_address)
702 #define	CMD2TRAN(cmd)	(CMD2PKT(cmd)->pkt_address.a_hba_tran)
703 #define	CMD2MR(cmd)	(TRAN2MR(CMD2TRAN(cmd)))
704 
705 #define	CFLAG_DMAVALID		0x0001	/* requires a dma operation */
706 #define	CFLAG_DMASEND		0x0002	/* Transfer from the device */
707 #define	CFLAG_CONSISTENT	0x0040	/* consistent data transfer */
708 
709 /*
710  * ### Data structures for ioctl inteface and internal commands ###
711  */
712 
713 /*
714  * Data direction flags
715  */
716 #define	UIOC_RD		0x00001
717 #define	UIOC_WR		0x00002
718 
719 #define	SCP2HOST(scp)		(scp)->device->host	/* to host */
720 #define	SCP2HOSTDATA(scp)	SCP2HOST(scp)->hostdata	/* to soft state */
721 #define	SCP2CHANNEL(scp)	(scp)->device->channel	/* to channel */
722 #define	SCP2TARGET(scp)		(scp)->device->id	/* to target */
723 #define	SCP2LUN(scp)		(scp)->device->lun	/* to LUN */
724 
725 #define	SCSIHOST2ADAP(host)	(((caddr_t *)(host->hostdata))[0])
726 #define	SCP2ADAPTER(scp)				\
727 	(struct mrsas_instance *)SCSIHOST2ADAP(SCP2HOST(scp))
728 
729 #define	MRDRV_IS_LOGICAL_SCSA(instance, acmd)		\
730 	(acmd->device_id < MRDRV_MAX_LD) ? 1 : 0
731 #define	MRDRV_IS_LOGICAL(ap)				\
732 	((ap->a_target < MRDRV_MAX_LD) && (ap->a_lun == 0)) ? 1 : 0
733 #define	MAP_DEVICE_ID(instance, ap)			\
734 	(ap->a_target)
735 
736 #define	HIGH_LEVEL_INTR			1
737 #define	NORMAL_LEVEL_INTR		0
738 
739 #define		IO_TIMEOUT_VAL		0
740 #define		IO_RETRY_COUNT		3
741 #define		MAX_FW_RESET_COUNT	3
742 /*
743  * scsa_cmd  - Per-command mr private data
744  * @param cmd_dmahandle		:  dma handle
745  * @param cmd_dmacookies	:  current dma cookies
746  * @param cmd_pkt		:  scsi_pkt reference
747  * @param cmd_dmacount		:  dma count
748  * @param cmd_cookie		:  next cookie
749  * @param cmd_ncookies		:  cookies per window
750  * @param cmd_cookiecnt		:  cookies per sub-win
751  * @param cmd_nwin		:  number of dma windows
752  * @param cmd_curwin		:  current dma window
753  * @param cmd_dma_offset	:  current window offset
754  * @param cmd_dma_len		:  current window length
755  * @param cmd_flags		:  private flags
756  * @param cmd_cdblen		:  length of cdb
757  * @param cmd_scblen		:  length of scb
758  * @param cmd_buf		:  command buffer
759  * @param channel		:  channel for scsi sub-system
760  * @param target		:  target for scsi sub-system
761  * @param lun			:  LUN for scsi sub-system
762  *
763  * - Allocated at same time as scsi_pkt by scsi_hba_pkt_alloc(9E)
764  * - Pointed to by pkt_ha_private field in scsi_pkt
765  */
766 struct scsa_cmd {
767 	ddi_dma_handle_t	cmd_dmahandle;
768 	ddi_dma_cookie_t	cmd_dmacookies[MRSAS_MAX_SGE_CNT];
769 	struct scsi_pkt		*cmd_pkt;
770 	ulong_t			cmd_dmacount;
771 	uint_t			cmd_cookie;
772 	uint_t			cmd_ncookies;
773 	uint_t			cmd_cookiecnt;
774 	uint_t			cmd_nwin;
775 	uint_t			cmd_curwin;
776 	off_t			cmd_dma_offset;
777 	ulong_t			cmd_dma_len;
778 	ulong_t			cmd_flags;
779 	uint_t			cmd_cdblen;
780 	uint_t			cmd_scblen;
781 	struct buf		*cmd_buf;
782 	ushort_t		device_id;
783 	uchar_t			islogical;
784 	uchar_t			lun;
785 	struct mrsas_device	*mrsas_dev;
786 };
787 
788 
789 struct mrsas_cmd {
790 	/*
791 	 * ThunderBolt(TB) We would be needing to have a placeholder
792 	 * for RAID_MSG_IO_REQUEST inside this structure. We are
793 	 * supposed to embed the mr_frame inside the RAID_MSG and post
794 	 * it down to the firmware.
795 	 */
796 	union mrsas_frame	*frame;
797 	uint32_t		frame_phys_addr;
798 	uint8_t			*sense;
799 	uint8_t			*sense1;
800 	uint32_t		sense_phys_addr;
801 	uint32_t		sense_phys_addr1;
802 	dma_obj_t		frame_dma_obj;
803 	uint8_t			frame_dma_obj_status;
804 	uint32_t		index;
805 	uint8_t			sync_cmd;
806 	uint8_t			cmd_status;
807 	uint16_t		abort_aen;
808 	mlist_t			list;
809 	uint32_t		frame_count;
810 	struct scsa_cmd		*cmd;
811 	struct scsi_pkt		*pkt;
812 	Mpi2RaidSCSIIORequest_t *scsi_io_request;
813 	Mpi2SGEIOUnion_t	*sgl;
814 	uint32_t		sgl_phys_addr;
815 	uint32_t		scsi_io_request_phys_addr;
816 	MRSAS_REQUEST_DESCRIPTOR_UNION	*request_desc;
817 	uint16_t		SMID;
818 	uint16_t		retry_count_for_ocr;
819 	uint16_t		drv_pkt_time;
820 	uint16_t		load_balance_flag;
821 
822 };
823 
824 #define	MAX_MGMT_ADAPTERS			1024
825 #define	IOC_SIGNATURE				"MR-SAS"
826 
827 #define	IOC_CMD_FIRMWARE			0x0
828 #define	MRSAS_DRIVER_IOCTL_COMMON		0xF0010000
829 #define	MRSAS_DRIVER_IOCTL_DRIVER_VERSION	0xF0010100
830 #define	MRSAS_DRIVER_IOCTL_PCI_INFORMATION	0xF0010200
831 #define	MRSAS_DRIVER_IOCTL_MRRAID_STATISTICS	0xF0010300
832 
833 
834 #define	MRSAS_MAX_SENSE_LENGTH			32
835 
836 struct mrsas_mgmt_info {
837 
838 	uint16_t			count;
839 	struct mrsas_instance		*instance[MAX_MGMT_ADAPTERS];
840 	uint16_t			map[MAX_MGMT_ADAPTERS];
841 	int				max_index;
842 };
843 
844 
845 #pragma pack(1)
846 /*
847  * SAS controller properties
848  */
849 struct mrsas_ctrl_prop {
850 	uint16_t	seq_num;
851 	uint16_t	pred_fail_poll_interval;
852 	uint16_t	intr_throttle_count;
853 	uint16_t	intr_throttle_timeouts;
854 
855 	uint8_t		rebuild_rate;
856 	uint8_t		patrol_read_rate;
857 	uint8_t		bgi_rate;
858 	uint8_t		cc_rate;
859 	uint8_t		recon_rate;
860 
861 	uint8_t		cache_flush_interval;
862 
863 	uint8_t		spinup_drv_count;
864 	uint8_t		spinup_delay;
865 
866 	uint8_t		cluster_enable;
867 	uint8_t		coercion_mode;
868 	uint8_t		alarm_enable;
869 
870 	uint8_t		reserved_1[13];
871 	uint32_t	on_off_properties;
872 	uint8_t		reserved_4[28];
873 };
874 
875 
876 /*
877  * SAS controller information
878  */
879 struct mrsas_ctrl_info {
880 	/* PCI device information */
881 	struct {
882 		uint16_t	vendor_id;
883 		uint16_t	device_id;
884 		uint16_t	sub_vendor_id;
885 		uint16_t	sub_device_id;
886 		uint8_t	reserved[24];
887 	} pci;
888 
889 	/* Host interface information */
890 	struct {
891 		uint8_t	PCIX		: 1;
892 		uint8_t	PCIE		: 1;
893 		uint8_t	iSCSI		: 1;
894 		uint8_t	SAS_3G		: 1;
895 		uint8_t	reserved_0	: 4;
896 		uint8_t	reserved_1[6];
897 		uint8_t	port_count;
898 		uint64_t	port_addr[8];
899 	} host_interface;
900 
901 	/* Device (backend) interface information */
902 	struct {
903 		uint8_t	SPI		: 1;
904 		uint8_t	SAS_3G		: 1;
905 		uint8_t	SATA_1_5G	: 1;
906 		uint8_t	SATA_3G		: 1;
907 		uint8_t	reserved_0	: 4;
908 		uint8_t	reserved_1[6];
909 		uint8_t	port_count;
910 		uint64_t	port_addr[8];
911 	} device_interface;
912 
913 	/* List of components residing in flash. All str are null terminated */
914 	uint32_t	image_check_word;
915 	uint32_t	image_component_count;
916 
917 	struct {
918 		char	name[8];
919 		char	version[32];
920 		char	build_date[16];
921 		char	built_time[16];
922 	} image_component[8];
923 
924 	/*
925 	 * List of flash components that have been flashed on the card, but
926 	 * are not in use, pending reset of the adapter. This list will be
927 	 * empty if a flash operation has not occurred. All stings are null
928 	 * terminated
929 	 */
930 	uint32_t	pending_image_component_count;
931 
932 	struct {
933 		char	name[8];
934 		char	version[32];
935 		char	build_date[16];
936 		char	build_time[16];
937 	} pending_image_component[8];
938 
939 	uint8_t		max_arms;
940 	uint8_t		max_spans;
941 	uint8_t		max_arrays;
942 	uint8_t		max_lds;
943 
944 	char		product_name[80];
945 	char		serial_no[32];
946 
947 	/*
948 	 * Other physical/controller/operation information. Indicates the
949 	 * presence of the hardware
950 	 */
951 	struct {
952 		uint32_t	bbu		: 1;
953 		uint32_t	alarm		: 1;
954 		uint32_t	nvram		: 1;
955 		uint32_t	uart		: 1;
956 		uint32_t	reserved	: 28;
957 	} hw_present;
958 
959 	uint32_t	current_fw_time;
960 
961 	/* Maximum data transfer sizes */
962 	uint16_t		max_concurrent_cmds;
963 	uint16_t		max_sge_count;
964 	uint32_t		max_request_size;
965 
966 	/* Logical and physical device counts */
967 	uint16_t		ld_present_count;
968 	uint16_t		ld_degraded_count;
969 	uint16_t		ld_offline_count;
970 
971 	uint16_t		pd_present_count;
972 	uint16_t		pd_disk_present_count;
973 	uint16_t		pd_disk_pred_failure_count;
974 	uint16_t		pd_disk_failed_count;
975 
976 	/* Memory size information */
977 	uint16_t		nvram_size;
978 	uint16_t		memory_size;
979 	uint16_t		flash_size;
980 
981 	/* Error counters */
982 	uint16_t		mem_correctable_error_count;
983 	uint16_t		mem_uncorrectable_error_count;
984 
985 	/* Cluster information */
986 	uint8_t		cluster_permitted;
987 	uint8_t		cluster_active;
988 	uint8_t		reserved_1[2];
989 
990 	/* Controller capabilities structures */
991 	struct {
992 		uint32_t	raid_level_0	: 1;
993 		uint32_t	raid_level_1	: 1;
994 		uint32_t	raid_level_5	: 1;
995 		uint32_t	raid_level_1E	: 1;
996 		uint32_t	reserved	: 28;
997 	} raid_levels;
998 
999 	struct {
1000 		uint32_t	rbld_rate		: 1;
1001 		uint32_t	cc_rate			: 1;
1002 		uint32_t	bgi_rate		: 1;
1003 		uint32_t	recon_rate		: 1;
1004 		uint32_t	patrol_rate		: 1;
1005 		uint32_t	alarm_control		: 1;
1006 		uint32_t	cluster_supported	: 1;
1007 		uint32_t	bbu			: 1;
1008 		uint32_t	spanning_allowed	: 1;
1009 		uint32_t	dedicated_hotspares	: 1;
1010 		uint32_t	revertible_hotspares	: 1;
1011 		uint32_t	foreign_config_import	: 1;
1012 		uint32_t	self_diagnostic		: 1;
1013 		uint32_t	reserved		: 19;
1014 	} adapter_operations;
1015 
1016 	struct {
1017 		uint32_t	read_policy	: 1;
1018 		uint32_t	write_policy	: 1;
1019 		uint32_t	io_policy	: 1;
1020 		uint32_t	access_policy	: 1;
1021 		uint32_t	reserved	: 28;
1022 	} ld_operations;
1023 
1024 	struct {
1025 		uint8_t	min;
1026 		uint8_t	max;
1027 		uint8_t	reserved[2];
1028 	} stripe_size_operations;
1029 
1030 	struct {
1031 		uint32_t	force_online	: 1;
1032 		uint32_t	force_offline	: 1;
1033 		uint32_t	force_rebuild	: 1;
1034 		uint32_t	reserved	: 29;
1035 	} pd_operations;
1036 
1037 	struct {
1038 		uint32_t	ctrl_supports_sas	: 1;
1039 		uint32_t	ctrl_supports_sata	: 1;
1040 		uint32_t	allow_mix_in_encl	: 1;
1041 		uint32_t	allow_mix_in_ld		: 1;
1042 		uint32_t	allow_sata_in_cluster	: 1;
1043 		uint32_t	reserved		: 27;
1044 	} pd_mix_support;
1045 
1046 	/* Include the controller properties (changeable items) */
1047 	uint8_t				reserved_2[12];
1048 	struct mrsas_ctrl_prop		properties;
1049 
1050 	uint8_t				pad[0x800 - 0x640];
1051 };
1052 
1053 /*
1054  * ==================================
1055  * MegaRAID SAS2.0 driver definitions
1056  * ==================================
1057  */
1058 #define	MRDRV_MAX_NUM_CMD			1024
1059 
1060 #define	MRDRV_MAX_PD_CHANNELS			2
1061 #define	MRDRV_MAX_LD_CHANNELS			2
1062 #define	MRDRV_MAX_CHANNELS			(MRDRV_MAX_PD_CHANNELS + \
1063 						MRDRV_MAX_LD_CHANNELS)
1064 #define	MRDRV_MAX_DEV_PER_CHANNEL		128
1065 #define	MRDRV_DEFAULT_INIT_ID			-1
1066 #define	MRDRV_MAX_CMD_PER_LUN			1000
1067 #define	MRDRV_MAX_LUN				1
1068 #define	MRDRV_MAX_LD				64
1069 
1070 #define	MRDRV_RESET_WAIT_TIME			300
1071 #define	MRDRV_RESET_NOTICE_INTERVAL		5
1072 
1073 #define	MRSAS_IOCTL_CMD				0
1074 
1075 #define	MRDRV_TGT_VALID				1
1076 
1077 /*
1078  * FW can accept both 32 and 64 bit SGLs. We want to allocate 32/64 bit
1079  * SGLs based on the size of dma_addr_t
1080  */
1081 #define	IS_DMA64		(sizeof (dma_addr_t) == 8)
1082 
1083 #define	RESERVED0_REGISTER		0x00	/* XScale */
1084 #define	IB_MSG_0_OFF			0x10	/* XScale */
1085 #define	OB_MSG_0_OFF			0x18	/* XScale */
1086 #define	IB_DOORBELL_OFF			0x20	/* XScale & ROC */
1087 #define	OB_INTR_STATUS_OFF		0x30	/* XScale & ROC */
1088 #define	OB_INTR_MASK_OFF		0x34	/* XScale & ROC */
1089 #define	IB_QPORT_OFF			0x40	/* XScale & ROC */
1090 #define	OB_DOORBELL_CLEAR_OFF		0xA0	/* ROC */
1091 #define	OB_SCRATCH_PAD_0_OFF		0xB0	/* ROC */
1092 #define	OB_INTR_MASK			0xFFFFFFFF
1093 #define	OB_DOORBELL_CLEAR_MASK		0xFFFFFFFF
1094 #define	SYSTOIOP_INTERRUPT_MASK		0x80000000
1095 #define	OB_SCRATCH_PAD_2_OFF		0xB4
1096 #define	WRITE_TBOLT_SEQ_OFF		0x00000004
1097 #define	DIAG_TBOLT_RESET_ADAPTER	0x00000004
1098 #define	HOST_TBOLT_DIAG_OFF		0x00000008
1099 #define	RESET_TBOLT_STATUS_OFF		0x000003C3
1100 #define	WRITE_SEQ_OFF			0x000000FC
1101 #define	HOST_DIAG_OFF			0x000000F8
1102 #define	DIAG_RESET_ADAPTER		0x00000004
1103 #define	DIAG_WRITE_ENABLE		0x00000080
1104 #define	SYSTOIOP_INTERRUPT_MASK		0x80000000
1105 
1106 #define	WR_IB_WRITE_SEQ(v, instance) 	ddi_put32((instance)->regmap_handle, \
1107 	(uint32_t *)((uintptr_t)(instance)->regmap + WRITE_SEQ_OFF), (v))
1108 
1109 #define	RD_OB_DRWE(instance) 		ddi_get32((instance)->regmap_handle, \
1110 	(uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF))
1111 
1112 #define	WR_IB_DRWE(v, instance) 	ddi_put32((instance)->regmap_handle, \
1113 	(uint32_t *)((uintptr_t)(instance)->regmap + HOST_DIAG_OFF), (v))
1114 
1115 #define	IB_LOW_QPORT			0xC0
1116 #define	IB_HIGH_QPORT			0xC4
1117 #define	OB_DOORBELL_REGISTER		0x9C	/* 1078 implementation */
1118 
1119 /*
1120  * All MFI register set macros accept mrsas_register_set*
1121  */
1122 #define	WR_IB_MSG_0(v, instance) 	ddi_put32((instance)->regmap_handle, \
1123 	(uint32_t *)((uintptr_t)(instance)->regmap + IB_MSG_0_OFF), (v))
1124 
1125 #define	RD_OB_MSG_0(instance) 		ddi_get32((instance)->regmap_handle, \
1126 	(uint32_t *)((uintptr_t)(instance)->regmap + OB_MSG_0_OFF))
1127 
1128 #define	WR_IB_DOORBELL(v, instance)	ddi_put32((instance)->regmap_handle, \
1129 	(uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF), (v))
1130 
1131 #define	RD_IB_DOORBELL(instance)	ddi_get32((instance)->regmap_handle, \
1132 	(uint32_t *)((uintptr_t)(instance)->regmap + IB_DOORBELL_OFF))
1133 
1134 #define	WR_OB_INTR_STATUS(v, instance) 	ddi_put32((instance)->regmap_handle, \
1135 	(uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF), (v))
1136 
1137 #define	RD_OB_INTR_STATUS(instance) 	ddi_get32((instance)->regmap_handle, \
1138 	(uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_STATUS_OFF))
1139 
1140 #define	WR_OB_INTR_MASK(v, instance) 	ddi_put32((instance)->regmap_handle, \
1141 	(uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), (v))
1142 
1143 #define	RD_OB_INTR_MASK(instance) 	ddi_get32((instance)->regmap_handle, \
1144 	(uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF))
1145 
1146 #define	WR_IB_QPORT(v, instance) 	ddi_put32((instance)->regmap_handle, \
1147 	(uint32_t *)((uintptr_t)(instance)->regmap + IB_QPORT_OFF), (v))
1148 
1149 #define	WR_OB_DOORBELL_CLEAR(v, instance) ddi_put32((instance)->regmap_handle, \
1150 	(uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_CLEAR_OFF), \
1151 	(v))
1152 
1153 #define	RD_OB_SCRATCH_PAD_0(instance) 	ddi_get32((instance)->regmap_handle, \
1154 	(uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_0_OFF))
1155 
1156 /* Thunderbolt specific registers */
1157 #define	RD_OB_SCRATCH_PAD_2(instance)	ddi_get32((instance)->regmap_handle, \
1158 	(uint32_t *)((uintptr_t)(instance)->regmap + OB_SCRATCH_PAD_2_OFF))
1159 
1160 #define	WR_TBOLT_IB_WRITE_SEQ(v, instance) \
1161 	ddi_put32((instance)->regmap_handle, \
1162 	(uint32_t *)((uintptr_t)(instance)->regmap + WRITE_TBOLT_SEQ_OFF), (v))
1163 
1164 #define	RD_TBOLT_HOST_DIAG(instance)	ddi_get32((instance)->regmap_handle, \
1165 	(uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF))
1166 
1167 #define	WR_TBOLT_HOST_DIAG(v, instance)	ddi_put32((instance)->regmap_handle, \
1168 	(uint32_t *)((uintptr_t)(instance)->regmap + HOST_TBOLT_DIAG_OFF), (v))
1169 
1170 #define	RD_TBOLT_RESET_STAT(instance)	ddi_get32((instance)->regmap_handle, \
1171 	(uint32_t *)((uintptr_t)(instance)->regmap + RESET_TBOLT_STATUS_OFF))
1172 
1173 
1174 #define	WR_MPI2_REPLY_POST_INDEX(v, instance)\
1175 	ddi_put32((instance)->regmap_handle,\
1176 	(uint32_t *)\
1177 	((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET),\
1178 	(v))
1179 
1180 
1181 #define	RD_MPI2_REPLY_POST_INDEX(instance)\
1182 	ddi_get32((instance)->regmap_handle,\
1183 	(uint32_t *)\
1184 	((uintptr_t)(instance)->regmap + MPI2_REPLY_POST_HOST_INDEX_OFFSET))
1185 
1186 #define	WR_IB_LOW_QPORT(v, instance) 	ddi_put32((instance)->regmap_handle, \
1187 	(uint32_t *)((uintptr_t)(instance)->regmap + IB_LOW_QPORT), (v))
1188 
1189 #define	WR_IB_HIGH_QPORT(v, instance) 	ddi_put32((instance)->regmap_handle, \
1190 	(uint32_t *)((uintptr_t)(instance)->regmap + IB_HIGH_QPORT), (v))
1191 
1192 #define	WR_OB_DOORBELL_REGISTER_CLEAR(v, instance)\
1193 	ddi_put32((instance)->regmap_handle,\
1194 	(uint32_t *)((uintptr_t)(instance)->regmap + OB_DOORBELL_REGISTER), \
1195 	(v))
1196 
1197 #define	WR_RESERVED0_REGISTER(v, instance) ddi_put32((instance)->regmap_handle,\
1198 	(uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER), \
1199 	(v))
1200 
1201 #define	RD_RESERVED0_REGISTER(instance) ddi_get32((instance)->regmap_handle, \
1202 	(uint32_t *)((uintptr_t)(instance)->regmap + RESERVED0_REGISTER))
1203 
1204 
1205 
1206 /*
1207  * When FW is in MFI_STATE_READY or MFI_STATE_OPERATIONAL, the state data
1208  * of Outbound Msg Reg 0 indicates max concurrent cmds supported, max SGEs
1209  * supported per cmd and if 64-bit MFAs (M64) is enabled or disabled.
1210  */
1211 #define	MFI_OB_INTR_STATUS_MASK		0x00000002
1212 
1213 /*
1214  * This MFI_REPLY_2108_MESSAGE_INTR flag is used also
1215  * in enable_intr_ppc also. Hence bit 2, i.e. 0x4 has
1216  * been set in this flag along with bit 1.
1217  */
1218 #define	MFI_REPLY_2108_MESSAGE_INTR		0x00000001
1219 #define	MFI_REPLY_2108_MESSAGE_INTR_MASK	0x00000005
1220 
1221 /* Fusion interrupt mask */
1222 #define	MFI_FUSION_ENABLE_INTERRUPT_MASK	(0x00000008)
1223 
1224 #define	MFI_POLL_TIMEOUT_SECS		60
1225 
1226 #define	MFI_ENABLE_INTR(instance)  ddi_put32((instance)->regmap_handle, \
1227 	(uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF), 1)
1228 #define	MFI_DISABLE_INTR(instance)					\
1229 {									\
1230 	uint32_t disable = 1;						\
1231 	uint32_t mask =  ddi_get32((instance)->regmap_handle, 		\
1232 	    (uint32_t *)((uintptr_t)(instance)->regmap + OB_INTR_MASK_OFF));\
1233 	mask &= ~disable;						\
1234 	ddi_put32((instance)->regmap_handle, (uint32_t *)		\
1235 	    (uintptr_t)((instance)->regmap + OB_INTR_MASK_OFF), mask);	\
1236 }
1237 
1238 /* By default, the firmware programs for 8 Kbytes of memory */
1239 #define	DEFAULT_MFI_MEM_SZ	8192
1240 #define	MINIMUM_MFI_MEM_SZ	4096
1241 
1242 /* DCMD Message Frame MAILBOX0-11 */
1243 #define	DCMD_MBOX_SZ		12
1244 
1245 /*
1246  * on_off_property of mrsas_ctrl_prop
1247  * bit0-9, 11-31 are reserved
1248  */
1249 #define	DISABLE_OCR_PROP_FLAG   0x00000400 /* bit 10 */
1250 
1251 struct mrsas_register_set {
1252 	uint32_t	reserved_0[4];			/* 0000h */
1253 
1254 	uint32_t	inbound_msg_0;			/* 0010h */
1255 	uint32_t	inbound_msg_1;			/* 0014h */
1256 	uint32_t	outbound_msg_0;			/* 0018h */
1257 	uint32_t	outbound_msg_1;			/* 001Ch */
1258 
1259 	uint32_t	inbound_doorbell;		/* 0020h */
1260 	uint32_t	inbound_intr_status;		/* 0024h */
1261 	uint32_t	inbound_intr_mask;		/* 0028h */
1262 
1263 	uint32_t	outbound_doorbell;		/* 002Ch */
1264 	uint32_t	outbound_intr_status;		/* 0030h */
1265 	uint32_t	outbound_intr_mask;		/* 0034h */
1266 
1267 	uint32_t	reserved_1[2];			/* 0038h */
1268 
1269 	uint32_t	inbound_queue_port;		/* 0040h */
1270 	uint32_t	outbound_queue_port;		/* 0044h */
1271 
1272 	uint32_t 	reserved_2[22];			/* 0048h */
1273 
1274 	uint32_t 	outbound_doorbell_clear;	/* 00A0h */
1275 
1276 	uint32_t 	reserved_3[3];			/* 00A4h */
1277 
1278 	uint32_t 	outbound_scratch_pad;		/* 00B0h */
1279 
1280 	uint32_t 	reserved_4[3];			/* 00B4h */
1281 
1282 	uint32_t 	inbound_low_queue_port;		/* 00C0h */
1283 
1284 	uint32_t 	inbound_high_queue_port;	/* 00C4h */
1285 
1286 	uint32_t 	reserved_5;			/* 00C8h */
1287 	uint32_t 	index_registers[820];		/* 00CCh */
1288 };
1289 
1290 struct mrsas_sge32 {
1291 	uint32_t	phys_addr;
1292 	uint32_t	length;
1293 };
1294 
1295 struct mrsas_sge64 {
1296 	uint64_t	phys_addr;
1297 	uint32_t	length;
1298 };
1299 
1300 struct mrsas_sge_ieee {
1301 	uint64_t 	phys_addr;
1302 	uint32_t	length;
1303 	uint32_t	flag;
1304 };
1305 
1306 union mrsas_sgl {
1307 	struct mrsas_sge32	sge32[1];
1308 	struct mrsas_sge64	sge64[1];
1309 	struct mrsas_sge_ieee	sge_ieee[1];
1310 };
1311 
1312 struct mrsas_header {
1313 	uint8_t		cmd;				/* 00h */
1314 	uint8_t		sense_len;			/* 01h */
1315 	uint8_t		cmd_status;			/* 02h */
1316 	uint8_t		scsi_status;			/* 03h */
1317 
1318 	uint8_t		target_id;			/* 04h */
1319 	uint8_t		lun;				/* 05h */
1320 	uint8_t		cdb_len;			/* 06h */
1321 	uint8_t		sge_count;			/* 07h */
1322 
1323 	uint32_t	context;			/* 08h */
1324 	uint8_t		req_id;				/* 0Ch */
1325 	uint8_t		msgvector;			/* 0Dh */
1326 	uint16_t	pad_0;				/* 0Eh */
1327 
1328 	uint16_t	flags;				/* 10h */
1329 	uint16_t	timeout;			/* 12h */
1330 	uint32_t	data_xferlen;			/* 14h */
1331 };
1332 
1333 union mrsas_sgl_frame {
1334 	struct mrsas_sge32	sge32[8];
1335 	struct mrsas_sge64	sge64[5];
1336 };
1337 
1338 struct mrsas_init_frame {
1339 	uint8_t		cmd;				/* 00h */
1340 	uint8_t		reserved_0;			/* 01h */
1341 	uint8_t		cmd_status;			/* 02h */
1342 
1343 	uint8_t		reserved_1;			/* 03h */
1344 	uint32_t	reserved_2;			/* 04h */
1345 
1346 	uint32_t	context;			/* 08h */
1347 	uint8_t		req_id;				/* 0Ch */
1348 	uint8_t		msgvector;			/* 0Dh */
1349 	uint16_t	pad_0;				/* 0Eh */
1350 
1351 	uint16_t	flags;				/* 10h */
1352 	uint16_t	reserved_3;			/* 12h */
1353 	uint32_t	data_xfer_len;			/* 14h */
1354 
1355 	uint32_t	queue_info_new_phys_addr_lo;	/* 18h */
1356 	uint32_t	queue_info_new_phys_addr_hi;	/* 1Ch */
1357 	uint32_t	queue_info_old_phys_addr_lo;	/* 20h */
1358 	uint32_t	queue_info_old_phys_addr_hi;	/* 24h */
1359 	uint64_t 	driverversion;			/* 28h */
1360 	uint32_t	reserved_4[4];			/* 30h */
1361 };
1362 
1363 struct mrsas_init_queue_info {
1364 	uint32_t		init_flags;			/* 00h */
1365 	uint32_t		reply_queue_entries;		/* 04h */
1366 
1367 	uint32_t		reply_queue_start_phys_addr_lo;	/* 08h */
1368 	uint32_t		reply_queue_start_phys_addr_hi;	/* 0Ch */
1369 	uint32_t		producer_index_phys_addr_lo;	/* 10h */
1370 	uint32_t		producer_index_phys_addr_hi;	/* 14h */
1371 	uint32_t		consumer_index_phys_addr_lo;	/* 18h */
1372 	uint32_t		consumer_index_phys_addr_hi;	/* 1Ch */
1373 };
1374 
1375 struct mrsas_io_frame {
1376 	uint8_t			cmd;			/* 00h */
1377 	uint8_t			sense_len;		/* 01h */
1378 	uint8_t			cmd_status;		/* 02h */
1379 	uint8_t			scsi_status;		/* 03h */
1380 
1381 	uint8_t			target_id;		/* 04h */
1382 	uint8_t			access_byte;		/* 05h */
1383 	uint8_t			reserved_0;		/* 06h */
1384 	uint8_t			sge_count;		/* 07h */
1385 
1386 	uint32_t		context;		/* 08h */
1387 	uint8_t			req_id;			/* 0Ch */
1388 	uint8_t			msgvector;		/* 0Dh */
1389 	uint16_t		pad_0;			/* 0Eh */
1390 
1391 	uint16_t		flags;			/* 10h */
1392 	uint16_t		timeout;		/* 12h */
1393 	uint32_t		lba_count;		/* 14h */
1394 
1395 	uint32_t		sense_buf_phys_addr_lo;	/* 18h */
1396 	uint32_t		sense_buf_phys_addr_hi;	/* 1Ch */
1397 
1398 	uint32_t		start_lba_lo;		/* 20h */
1399 	uint32_t		start_lba_hi;		/* 24h */
1400 
1401 	union mrsas_sgl		sgl;			/* 28h */
1402 };
1403 
1404 struct mrsas_pthru_frame {
1405 	uint8_t			cmd;			/* 00h */
1406 	uint8_t			sense_len;		/* 01h */
1407 	uint8_t			cmd_status;		/* 02h */
1408 	uint8_t			scsi_status;		/* 03h */
1409 
1410 	uint8_t			target_id;		/* 04h */
1411 	uint8_t			lun;			/* 05h */
1412 	uint8_t			cdb_len;		/* 06h */
1413 	uint8_t			sge_count;		/* 07h */
1414 
1415 	uint32_t		context;		/* 08h */
1416 	uint8_t			req_id;			/* 0Ch */
1417 	uint8_t			msgvector;		/* 0Dh */
1418 	uint16_t		pad_0;			/* 0Eh */
1419 
1420 	uint16_t		flags;			/* 10h */
1421 	uint16_t		timeout;		/* 12h */
1422 	uint32_t		data_xfer_len;		/* 14h */
1423 
1424 	uint32_t		sense_buf_phys_addr_lo;	/* 18h */
1425 	uint32_t		sense_buf_phys_addr_hi;	/* 1Ch */
1426 
1427 	uint8_t			cdb[16];		/* 20h */
1428 	union mrsas_sgl		sgl;			/* 30h */
1429 };
1430 
1431 struct mrsas_dcmd_frame {
1432 	uint8_t			cmd;			/* 00h */
1433 	uint8_t			reserved_0;		/* 01h */
1434 	uint8_t			cmd_status;		/* 02h */
1435 	uint8_t			reserved_1[4];		/* 03h */
1436 	uint8_t			sge_count;		/* 07h */
1437 
1438 	uint32_t		context;		/* 08h */
1439 	uint8_t			req_id;			/* 0Ch */
1440 	uint8_t			msgvector;		/* 0Dh */
1441 	uint16_t		pad_0;			/* 0Eh */
1442 
1443 	uint16_t		flags;			/* 10h */
1444 	uint16_t		timeout;		/* 12h */
1445 
1446 	uint32_t		data_xfer_len;		/* 14h */
1447 	uint32_t		opcode;			/* 18h */
1448 
1449 	/* uint8_t		mbox[DCMD_MBOX_SZ]; */	/* 1Ch */
1450 	union {						/* 1Ch */
1451 		uint8_t b[DCMD_MBOX_SZ];
1452 		uint16_t s[6];
1453 		uint32_t w[3];
1454 	} mbox;
1455 
1456 	union mrsas_sgl		sgl;			/* 28h */
1457 };
1458 
1459 struct mrsas_abort_frame {
1460 	uint8_t		cmd;				/* 00h */
1461 	uint8_t		reserved_0;			/* 01h */
1462 	uint8_t		cmd_status;			/* 02h */
1463 
1464 	uint8_t		reserved_1;			/* 03h */
1465 	uint32_t	reserved_2;			/* 04h */
1466 
1467 	uint32_t	context;			/* 08h */
1468 	uint8_t		req_id;				/* 0Ch */
1469 	uint8_t		msgvector;			/* 0Dh */
1470 	uint16_t	pad_0;				/* 0Eh */
1471 
1472 	uint16_t	flags;				/* 10h */
1473 	uint16_t	reserved_3;			/* 12h */
1474 	uint32_t	reserved_4;			/* 14h */
1475 
1476 	uint32_t	abort_context;			/* 18h */
1477 	uint32_t	pad_1;				/* 1Ch */
1478 
1479 	uint32_t	abort_mfi_phys_addr_lo;		/* 20h */
1480 	uint32_t	abort_mfi_phys_addr_hi;		/* 24h */
1481 
1482 	uint32_t	reserved_5[6];			/* 28h */
1483 };
1484 
1485 struct mrsas_smp_frame {
1486 	uint8_t		cmd;				/* 00h */
1487 	uint8_t		reserved_1;			/* 01h */
1488 	uint8_t		cmd_status;			/* 02h */
1489 	uint8_t		connection_status;		/* 03h */
1490 
1491 	uint8_t		reserved_2[3];			/* 04h */
1492 	uint8_t		sge_count;			/* 07h */
1493 
1494 	uint32_t	context;			/* 08h */
1495 	uint8_t		req_id;				/* 0Ch */
1496 	uint8_t		msgvector;			/* 0Dh */
1497 	uint16_t	pad_0;				/* 0Eh */
1498 
1499 	uint16_t	flags;				/* 10h */
1500 	uint16_t	timeout;			/* 12h */
1501 
1502 	uint32_t	data_xfer_len;			/* 14h */
1503 
1504 	uint64_t	sas_addr;			/* 20h */
1505 
1506 	union mrsas_sgl	sgl[2];				/* 28h */
1507 };
1508 
1509 struct mrsas_stp_frame {
1510 	uint8_t		cmd;				/* 00h */
1511 	uint8_t		reserved_1;			/* 01h */
1512 	uint8_t		cmd_status;			/* 02h */
1513 	uint8_t		connection_status;		/* 03h */
1514 
1515 	uint8_t		target_id;			/* 04h */
1516 	uint8_t		reserved_2[2];			/* 04h */
1517 	uint8_t		sge_count;			/* 07h */
1518 
1519 	uint32_t	context;			/* 08h */
1520 	uint8_t		req_id;				/* 0Ch */
1521 	uint8_t		msgvector;			/* 0Dh */
1522 	uint16_t	pad_0;				/* 0Eh */
1523 
1524 	uint16_t	flags;				/* 10h */
1525 	uint16_t	timeout;			/* 12h */
1526 
1527 	uint32_t	data_xfer_len;			/* 14h */
1528 
1529 	uint16_t	fis[10];			/* 28h */
1530 	uint32_t	stp_flags;			/* 3C */
1531 	union mrsas_sgl	sgl;				/* 40 */
1532 };
1533 
1534 union mrsas_frame {
1535 	struct mrsas_header		hdr;
1536 	struct mrsas_init_frame		init;
1537 	struct mrsas_io_frame		io;
1538 	struct mrsas_pthru_frame	pthru;
1539 	struct mrsas_dcmd_frame		dcmd;
1540 	struct mrsas_abort_frame	abort;
1541 	struct mrsas_smp_frame		smp;
1542 	struct mrsas_stp_frame		stp;
1543 
1544 	uint8_t			raw_bytes[64];
1545 };
1546 
1547 typedef struct mrsas_pd_address {
1548 	uint16_t	device_id;
1549 	uint16_t	encl_id;
1550 
1551 	union {
1552 		struct {
1553 			uint8_t encl_index;
1554 			uint8_t slot_number;
1555 		} pd_address;
1556 		struct {
1557 			uint8_t	encl_position;
1558 			uint8_t	encl_connector_index;
1559 		} encl_address;
1560 	}address;
1561 
1562 	uint8_t	scsi_dev_type;
1563 
1564 	union {
1565 		uint8_t		port_bitmap;
1566 		uint8_t		port_numbers;
1567 	} connected;
1568 
1569 	uint64_t		sas_addr[2];
1570 } mrsas_pd_address_t;
1571 
1572 union mrsas_evt_class_locale {
1573 	struct {
1574 		uint16_t	locale;
1575 		uint8_t		reserved;
1576 		int8_t		class;
1577 	} members;
1578 
1579 	uint32_t	word;
1580 };
1581 
1582 struct mrsas_evt_log_info {
1583 	uint32_t	newest_seq_num;
1584 	uint32_t	oldest_seq_num;
1585 	uint32_t	clear_seq_num;
1586 	uint32_t	shutdown_seq_num;
1587 	uint32_t	boot_seq_num;
1588 };
1589 
1590 struct mrsas_progress {
1591 	uint16_t	progress;
1592 	uint16_t	elapsed_seconds;
1593 };
1594 
1595 struct mrsas_evtarg_ld {
1596 	uint16_t	target_id;
1597 	uint8_t		ld_index;
1598 	uint8_t		reserved;
1599 };
1600 
1601 struct mrsas_evtarg_pd {
1602 	uint16_t	device_id;
1603 	uint8_t		encl_index;
1604 	uint8_t		slot_number;
1605 };
1606 
1607 struct mrsas_evt_detail {
1608 	uint32_t	seq_num;
1609 	uint32_t	time_stamp;
1610 	uint32_t	code;
1611 	union mrsas_evt_class_locale	cl;
1612 	uint8_t		arg_type;
1613 	uint8_t		reserved1[15];
1614 
1615 	union {
1616 		struct {
1617 			struct mrsas_evtarg_pd	pd;
1618 			uint8_t			cdb_length;
1619 			uint8_t			sense_length;
1620 			uint8_t			reserved[2];
1621 			uint8_t			cdb[16];
1622 			uint8_t			sense[64];
1623 		} cdbSense;
1624 
1625 		struct mrsas_evtarg_ld		ld;
1626 
1627 		struct {
1628 			struct mrsas_evtarg_ld	ld;
1629 			uint64_t		count;
1630 		} ld_count;
1631 
1632 		struct {
1633 			uint64_t		lba;
1634 			struct mrsas_evtarg_ld	ld;
1635 		} ld_lba;
1636 
1637 		struct {
1638 			struct mrsas_evtarg_ld	ld;
1639 			uint32_t		prevOwner;
1640 			uint32_t		newOwner;
1641 		} ld_owner;
1642 
1643 		struct {
1644 			uint64_t		ld_lba;
1645 			uint64_t		pd_lba;
1646 			struct mrsas_evtarg_ld	ld;
1647 			struct mrsas_evtarg_pd	pd;
1648 		} ld_lba_pd_lba;
1649 
1650 		struct {
1651 			struct mrsas_evtarg_ld	ld;
1652 			struct mrsas_progress	prog;
1653 		} ld_prog;
1654 
1655 		struct {
1656 			struct mrsas_evtarg_ld	ld;
1657 			uint32_t		prev_state;
1658 			uint32_t		new_state;
1659 		} ld_state;
1660 
1661 		struct {
1662 			uint64_t		strip;
1663 			struct mrsas_evtarg_ld	ld;
1664 		} ld_strip;
1665 
1666 		struct mrsas_evtarg_pd		pd;
1667 
1668 		struct {
1669 			struct mrsas_evtarg_pd	pd;
1670 			uint32_t		err;
1671 		} pd_err;
1672 
1673 		struct {
1674 			uint64_t		lba;
1675 			struct mrsas_evtarg_pd	pd;
1676 		} pd_lba;
1677 
1678 		struct {
1679 			uint64_t		lba;
1680 			struct mrsas_evtarg_pd	pd;
1681 			struct mrsas_evtarg_ld	ld;
1682 		} pd_lba_ld;
1683 
1684 		struct {
1685 			struct mrsas_evtarg_pd	pd;
1686 			struct mrsas_progress	prog;
1687 		} pd_prog;
1688 
1689 		struct {
1690 			struct mrsas_evtarg_pd	pd;
1691 			uint32_t		prevState;
1692 			uint32_t		newState;
1693 		} pd_state;
1694 
1695 		struct {
1696 			uint16_t	vendorId;
1697 			uint16_t	deviceId;
1698 			uint16_t	subVendorId;
1699 			uint16_t	subDeviceId;
1700 		} pci;
1701 
1702 		uint32_t	rate;
1703 		char		str[96];
1704 
1705 		struct {
1706 			uint32_t	rtc;
1707 			uint32_t	elapsedSeconds;
1708 		} time;
1709 
1710 		struct {
1711 			uint32_t	ecar;
1712 			uint32_t	elog;
1713 			char		str[64];
1714 		} ecc;
1715 
1716 		mrsas_pd_address_t	pd_addr;
1717 
1718 		uint8_t		b[96];
1719 		uint16_t	s[48];
1720 		uint32_t	w[24];
1721 		uint64_t	d[12];
1722 	} args;
1723 
1724 	char	description[128];
1725 
1726 };
1727 
1728 /* only 63 are usable by the application */
1729 #define	MAX_LOGICAL_DRIVES			64
1730 /* only 255 physical devices may be used */
1731 #define	MAX_PHYSICAL_DEVICES			256
1732 #define	MAX_PD_PER_ENCLOSURE			64
1733 /* maximum disks per array */
1734 #define	MAX_ROW_SIZE				32
1735 /* maximum spans per logical drive */
1736 #define	MAX_SPAN_DEPTH				8
1737 /* maximum number of arrays a hot spare may be dedicated to */
1738 #define	MAX_ARRAYS_DEDICATED			16
1739 /* maximum number of arrays which may exist */
1740 #define	MAX_ARRAYS				128
1741 /* maximum number of foreign configs that may ha managed at once */
1742 #define	MAX_FOREIGN_CONFIGS			8
1743 /* maximum spares (global and dedicated combined) */
1744 #define	MAX_SPARES_FOR_THE_CONTROLLER		MAX_PHYSICAL_DEVICES
1745 /* maximum possible Target IDs (i.e. 0 to 63) */
1746 #define	MAX_TARGET_ID				63
1747 /* maximum number of supported enclosures */
1748 #define	MAX_ENCLOSURES				32
1749 /* maximum number of PHYs per controller */
1750 #define	MAX_PHYS_PER_CONTROLLER			16
1751 /* maximum number of LDs per array (due to DDF limitations) */
1752 #define	MAX_LDS_PER_ARRAY			16
1753 
1754 /*
1755  * -----------------------------------------------------------------------------
1756  * -----------------------------------------------------------------------------
1757  *
1758  * Logical Drive commands
1759  *
1760  * -----------------------------------------------------------------------------
1761  * -----------------------------------------------------------------------------
1762  */
1763 #define	MR_DCMD_LD	0x03000000,	/* Logical Device (LD) opcodes */
1764 
1765 /*
1766  * Input:	dcmd.opcode	- MR_DCMD_LD_GET_LIST
1767  *		dcmd.mbox	- reserved
1768  *		dcmd.sge IN	- ptr to returned MR_LD_LIST structure
1769  * Desc:	Return the logical drive list structure
1770  * Status:	No error
1771  */
1772 
1773 /*
1774  * defines the logical drive reference structure
1775  */
1776 typedef	union _MR_LD_REF {	/* LD reference structure */
1777 	struct {
1778 		uint8_t	targetId; /* LD target id (0 to MAX_TARGET_ID) */
1779 		uint8_t	reserved; /* reserved for in line with MR_PD_REF */
1780 		uint16_t seqNum;  /* Sequence Number */
1781 	} ld_ref;
1782 	uint32_t ref;		/* shorthand reference to full 32-bits */
1783 } MR_LD_REF;			/* 4 bytes */
1784 
1785 /*
1786  * defines the logical drive list structure
1787  */
1788 typedef struct _MR_LD_LIST {
1789 	uint32_t	ldCount;	/* number of LDs */
1790 	uint32_t	reserved;	/* pad to 8-byte boundary */
1791 	struct {
1792 		MR_LD_REF ref;	/* LD reference */
1793 		uint8_t	state;		/* current LD state (MR_LD_STATE) */
1794 		uint8_t	reserved[3];	/* pad to 8-byte boundary */
1795 		uint64_t size;		/* LD size */
1796 	} ldList[MAX_LOGICAL_DRIVES];
1797 } MR_LD_LIST;
1798 
1799 struct mrsas_drv_ver {
1800 	uint8_t	signature[12];
1801 	uint8_t	os_name[16];
1802 	uint8_t	os_ver[12];
1803 	uint8_t	drv_name[20];
1804 	uint8_t	drv_ver[32];
1805 	uint8_t	drv_rel_date[20];
1806 };
1807 
1808 #define	PCI_TYPE0_ADDRESSES		6
1809 #define	PCI_TYPE1_ADDRESSES		2
1810 #define	PCI_TYPE2_ADDRESSES		5
1811 
1812 struct mrsas_pci_common_header {
1813 	uint16_t	vendorID;		/* (ro) */
1814 	uint16_t	deviceID;		/* (ro) */
1815 	uint16_t	command;		/* Device control */
1816 	uint16_t	status;
1817 	uint8_t		revisionID;		/* (ro) */
1818 	uint8_t		progIf;			/* (ro) */
1819 	uint8_t		subClass;		/* (ro) */
1820 	uint8_t		baseClass;		/* (ro) */
1821 	uint8_t		cacheLineSize;		/* (ro+) */
1822 	uint8_t		latencyTimer;		/* (ro+) */
1823 	uint8_t		headerType;		/* (ro) */
1824 	uint8_t		bist;			/* Built in self test */
1825 
1826 	union {
1827 	    struct {
1828 		uint32_t	baseAddresses[PCI_TYPE0_ADDRESSES];
1829 		uint32_t	cis;
1830 		uint16_t	subVendorID;
1831 		uint16_t	subSystemID;
1832 		uint32_t	romBaseAddress;
1833 		uint8_t		capabilitiesPtr;
1834 		uint8_t		reserved1[3];
1835 		uint32_t	reserved2;
1836 		uint8_t		interruptLine;
1837 		uint8_t		interruptPin;	/* (ro) */
1838 		uint8_t		minimumGrant;	/* (ro) */
1839 		uint8_t		maximumLatency;	/* (ro) */
1840 	    } type_0;
1841 
1842 	    struct {
1843 		uint32_t	baseAddresses[PCI_TYPE1_ADDRESSES];
1844 		uint8_t		primaryBus;
1845 		uint8_t		secondaryBus;
1846 		uint8_t		subordinateBus;
1847 		uint8_t		secondaryLatency;
1848 		uint8_t		ioBase;
1849 		uint8_t		ioLimit;
1850 		uint16_t	secondaryStatus;
1851 		uint16_t	memoryBase;
1852 		uint16_t	memoryLimit;
1853 		uint16_t	prefetchBase;
1854 		uint16_t	prefetchLimit;
1855 		uint32_t	prefetchBaseUpper32;
1856 		uint32_t	prefetchLimitUpper32;
1857 		uint16_t	ioBaseUpper16;
1858 		uint16_t	ioLimitUpper16;
1859 		uint8_t		capabilitiesPtr;
1860 		uint8_t		reserved1[3];
1861 		uint32_t	romBaseAddress;
1862 		uint8_t		interruptLine;
1863 		uint8_t		interruptPin;
1864 		uint16_t	bridgeControl;
1865 	    } type_1;
1866 
1867 	    struct {
1868 		uint32_t	socketRegistersBaseAddress;
1869 		uint8_t		capabilitiesPtr;
1870 		uint8_t		reserved;
1871 		uint16_t	secondaryStatus;
1872 		uint8_t		primaryBus;
1873 		uint8_t		secondaryBus;
1874 		uint8_t		subordinateBus;
1875 		uint8_t		secondaryLatency;
1876 		struct {
1877 			uint32_t	base;
1878 			uint32_t	limit;
1879 		} range[PCI_TYPE2_ADDRESSES-1];
1880 		uint8_t		interruptLine;
1881 		uint8_t		interruptPin;
1882 		uint16_t	bridgeControl;
1883 	    } type_2;
1884 	} header;
1885 };
1886 
1887 struct mrsas_pci_link_capability {
1888 	union {
1889 	    struct {
1890 		uint32_t linkSpeed		:4;
1891 		uint32_t linkWidth		:6;
1892 		uint32_t aspmSupport		:2;
1893 		uint32_t losExitLatency		:3;
1894 		uint32_t l1ExitLatency		:3;
1895 		uint32_t rsvdp			:6;
1896 		uint32_t portNumber		:8;
1897 	    } bits;
1898 
1899 	    uint32_t asUlong;
1900 	} cap;
1901 
1902 };
1903 
1904 struct mrsas_pci_link_status_capability {
1905 	union {
1906 	    struct {
1907 		uint16_t linkSpeed		:4;
1908 		uint16_t negotiatedLinkWidth	:6;
1909 		uint16_t linkTrainingError	:1;
1910 		uint16_t linkTraning		:1;
1911 		uint16_t slotClockConfig	:1;
1912 		uint16_t rsvdZ			:3;
1913 	    } bits;
1914 
1915 	    uint16_t asUshort;
1916 	} stat_cap;
1917 
1918 	uint16_t reserved;
1919 
1920 };
1921 
1922 struct mrsas_pci_capabilities {
1923 	struct mrsas_pci_link_capability	linkCapability;
1924 	struct mrsas_pci_link_status_capability linkStatusCapability;
1925 };
1926 
1927 struct mrsas_pci_information
1928 {
1929 	uint32_t		busNumber;
1930 	uint8_t			deviceNumber;
1931 	uint8_t			functionNumber;
1932 	uint8_t			interruptVector;
1933 	uint8_t			reserved;
1934 	struct mrsas_pci_common_header pciHeaderInfo;
1935 	struct mrsas_pci_capabilities capability;
1936 	uint8_t			reserved2[32];
1937 };
1938 
1939 struct mrsas_ioctl {
1940 	uint16_t	version;
1941 	uint16_t	controller_id;
1942 	uint8_t		signature[8];
1943 	uint32_t	reserved_1;
1944 	uint32_t	control_code;
1945 	uint32_t	reserved_2[2];
1946 	uint8_t		frame[64];
1947 	union mrsas_sgl_frame sgl_frame;
1948 	uint8_t		sense_buff[MRSAS_MAX_SENSE_LENGTH];
1949 	uint8_t		data[1];
1950 };
1951 
1952 struct mrsas_aen {
1953 	uint16_t	host_no;
1954 	uint16_t	cmd_status;
1955 	uint32_t	seq_num;
1956 	uint32_t	class_locale_word;
1957 };
1958 
1959 #pragma pack()
1960 
1961 #ifndef	DDI_VENDOR_LSI
1962 #define	DDI_VENDOR_LSI		"LSI"
1963 #endif /* DDI_VENDOR_LSI */
1964 
1965 int mrsas_config_scsi_device(struct mrsas_instance *,
1966     struct scsi_device *, dev_info_t **);
1967 
1968 int mrsas_tbolt_config_pd(struct mrsas_instance *, uint16_t,
1969     uint8_t, dev_info_t **);
1970 
1971 dev_info_t *mrsas_find_child(struct mrsas_instance *, uint16_t, uint8_t);
1972 int mrsas_service_evt(struct mrsas_instance *, int, int, int, uint64_t);
1973 void return_raid_msg_pkt(struct mrsas_instance *, struct mrsas_cmd *);
1974 struct mrsas_cmd *get_raid_msg_mfi_pkt(struct mrsas_instance *);
1975 void return_raid_msg_mfi_pkt(struct mrsas_instance *, struct mrsas_cmd *);
1976 
1977 int	alloc_space_for_mpi2(struct mrsas_instance *);
1978 void	fill_up_drv_ver(struct mrsas_drv_ver *dv);
1979 
1980 int	mrsas_issue_init_mpi2(struct mrsas_instance *);
1981 struct scsi_pkt *mrsas_tbolt_tran_init_pkt(struct scsi_address *, register
1982 		    struct scsi_pkt *, struct buf *, int, int, int, int,
1983 		    int (*)(), caddr_t);
1984 int	mrsas_tbolt_tran_start(struct scsi_address *,
1985 		    register struct scsi_pkt *);
1986 uint32_t tbolt_read_fw_status_reg(struct mrsas_instance *);
1987 void 	tbolt_issue_cmd(struct mrsas_cmd *, struct mrsas_instance *);
1988 int	tbolt_issue_cmd_in_poll_mode(struct mrsas_instance *,
1989 		    struct mrsas_cmd *);
1990 int	tbolt_issue_cmd_in_sync_mode(struct mrsas_instance *,
1991 		    struct mrsas_cmd *);
1992 void	tbolt_enable_intr(struct mrsas_instance *);
1993 void	tbolt_disable_intr(struct mrsas_instance *);
1994 int	tbolt_intr_ack(struct mrsas_instance *);
1995 uint_t	mr_sas_tbolt_process_outstanding_cmd(struct mrsas_instance *);
1996     uint_t tbolt_softintr();
1997 int 	mrsas_tbolt_dma(struct mrsas_instance *, uint32_t, int, int (*)());
1998 int	mrsas_check_dma_handle(ddi_dma_handle_t handle);
1999 int	mrsas_check_acc_handle(ddi_acc_handle_t handle);
2000 int	mrsas_dma_alloc(struct mrsas_instance *, struct scsi_pkt *,
2001 		    struct buf *, int, int (*)());
2002 int	mrsas_dma_move(struct mrsas_instance *,
2003 			struct scsi_pkt *, struct buf *);
2004 int	mrsas_alloc_dma_obj(struct mrsas_instance *, dma_obj_t *,
2005 		    uchar_t);
2006 void 	mr_sas_tbolt_build_mfi_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2007 int 	mrsas_dma_alloc_dmd(struct mrsas_instance *, dma_obj_t *);
2008 void 	tbolt_complete_cmd_in_sync_mode(struct mrsas_instance *,
2009 	struct mrsas_cmd *);
2010 int 	alloc_req_rep_desc(struct mrsas_instance *);
2011 int		mrsas_mode_sense_build(struct scsi_pkt *);
2012 void		push_pending_mfi_pkt(struct mrsas_instance *,
2013 			struct mrsas_cmd *);
2014 int	mrsas_issue_pending_cmds(struct mrsas_instance *);
2015 int 	mrsas_print_pending_cmds(struct mrsas_instance *);
2016 int  	mrsas_complete_pending_cmds(struct mrsas_instance *);
2017 
2018 int	create_mfi_frame_pool(struct mrsas_instance *);
2019 void	destroy_mfi_frame_pool(struct mrsas_instance *);
2020 int 	create_mfi_mpi_frame_pool(struct mrsas_instance *);
2021 void 	destroy_mfi_mpi_frame_pool(struct mrsas_instance *);
2022 int 	create_mpi2_frame_pool(struct mrsas_instance *);
2023 void 	destroy_mpi2_frame_pool(struct mrsas_instance *);
2024 int	mrsas_free_dma_obj(struct mrsas_instance *, dma_obj_t);
2025 void 	mrsas_tbolt_free_additional_dma_buffer(struct mrsas_instance *);
2026 void 	free_req_desc_pool(struct mrsas_instance *);
2027 void 	free_space_for_mpi2(struct mrsas_instance *);
2028 void 	mrsas_dump_reply_desc(struct mrsas_instance *);
2029 void 	tbolt_complete_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2030 void	display_scsi_inquiry(caddr_t);
2031 void	service_mfi_aen(struct mrsas_instance *, struct mrsas_cmd *);
2032 int	mrsas_mode_sense_build(struct scsi_pkt *);
2033 int 	mrsas_tbolt_get_ld_map_info(struct mrsas_instance *);
2034 struct mrsas_cmd *mrsas_tbolt_build_poll_cmd(struct mrsas_instance *,
2035 	struct scsi_address *, struct scsi_pkt *, uchar_t *);
2036 int	mrsas_tbolt_reset_ppc(struct mrsas_instance *instance);
2037 void	mrsas_tbolt_kill_adapter(struct mrsas_instance *instance);
2038 int 	abort_syncmap_cmd(struct mrsas_instance *, struct mrsas_cmd *);
2039 void	mrsas_tbolt_prepare_cdb(struct mrsas_instance *instance, U8 cdb[],
2040     struct IO_REQUEST_INFO *, Mpi2RaidSCSIIORequest_t *, U32);
2041 
2042 
2043 int mrsas_init_adapter_ppc(struct mrsas_instance *instance);
2044 int mrsas_init_adapter_tbolt(struct mrsas_instance *instance);
2045 int mrsas_init_adapter(struct mrsas_instance *instance);
2046 
2047 int mrsas_alloc_cmd_pool(struct mrsas_instance *instance);
2048 void mrsas_free_cmd_pool(struct mrsas_instance *instance);
2049 
2050 void mrsas_print_cmd_details(struct mrsas_instance *, struct mrsas_cmd *, int);
2051 struct mrsas_cmd *get_raid_msg_pkt(struct mrsas_instance *);
2052 
2053 int mfi_state_transition_to_ready(struct mrsas_instance *);
2054 
2055 struct mrsas_cmd *mrsas_get_mfi_pkt(struct mrsas_instance *);
2056 void mrsas_return_mfi_pkt(struct mrsas_instance *, struct mrsas_cmd *);
2057 
2058 
2059 /* FMA functions. */
2060 int mrsas_common_check(struct mrsas_instance *, struct  mrsas_cmd *);
2061 void mrsas_fm_ereport(struct mrsas_instance *, char *);
2062 
2063 
2064 #ifdef	__cplusplus
2065 }
2066 #endif
2067 
2068 #endif /* _MR_SAS_H_ */
2069