xref: /illumos-gate/usr/src/uts/sun4u/sys/mc-us3i.h (revision c6701b14)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef	_SYS_MC_US3I_H
28 #define	_SYS_MC_US3I_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #ifdef	__cplusplus
33 extern "C" {
34 #endif
35 
36 #if defined(_KERNEL)
37 
38 #define	NDGRPS_PER_MC		2		/* max dimm groups per mctrl */
39 #define	NDIMMS_PER_DGRP		2		/* max dimms in a group/pair */
40 #define	NLOGBANKS_PER_DGRP	2		/* max logical banks per grp */
41 #define	NLOGBANKS_PER_MC	16		/* max logical banks per mc */
42 #define	NLOGBANKS_PER_SEG	16		/* max logical banks per seg */
43 #define	MAX_DEVLEN		8
44 #define	TRANSFER_SIZE		64
45 
46 #define	MC_SELECT_MASK		0x3000000000LL	/* upto 4 MCs at 64GB boundry */
47 #define	MC_SELECT_SHIFT		36
48 #define	DIMM_PAIR_SELECT_MASK	0x200000000LL	/* at 8GB boundry */
49 #define	DIMM_PAIR_SELECT_SHIFT	33
50 #define	LOG_BANK_SELECT_MASK	0x100000000LL	/* at 4GB boundry */
51 #define	LOG_BANK_SELECT_SHIFT	32
52 #define	XOR_DEVICE_SELECT_MASK	0x200000LL	/* at 2MB boundry */
53 #define	XOR_DEVICE_SELECT_SHIFT	21
54 #define	XOR_BANK_SELECT_MASK	0x100000LL	/* at 1MB boundry */
55 #define	XOR_BANK_SELECT_SHIFT	20
56 
57 #define	MC_SIZE_MAX		0x1000000000LL	/* 64GB */
58 #define	DGRP_SIZE_MAX		0x200000000LL	/*  8GB */
59 #define	BANK_SIZE_MAX		0x100000000LL	/*  4GB */
60 
61 #define	MC_BASE(id)		(id * MC_SIZE_MAX)
62 #define	DGRP_BASE(id)		((id & (NDGRPS_PER_MC - 1)) * DGRP_SIZE_MAX)
63 #define	LOGBANK_BASE(id)	((id & (NLOGBANKS_PER_SEG - 1)) * BANK_SIZE_MAX)
64 
65 #define	ADDR_GEN_128Mb_X8_ROW_0	14
66 #define	ADDR_GEN_512Mb_X8_ROW_0	15
67 
68 #ifndef	_ASM
69 
70 struct mc_soft_state {
71 	dev_info_t	*dip;	/* dev info of myself */
72 	int		portid;
73 	int		mcr_read_ok;
74 	uint64_t	mcreg1;
75 	int		reglen;
76 	void		*reg;
77 	int		memlayoutlen;
78 	void		*memlayoutp;
79 };
80 
81 struct memory_reg_info {
82 	uint64_t base;
83 	uint64_t size;
84 };
85 
86 struct dimm_info {
87 	char	label[NDGRPS_PER_MC * NDIMMS_PER_DGRP][MAX_DEVLEN];
88 	char	table_width;	/* 1: symmetric 0: asymmetric */
89 	char	data[1];
90 };
91 
92 struct pin_info {
93 	uchar_t	dimmtable[18];
94 	uchar_t	pintable[144];
95 };
96 
97 /* This struct is included at the following structs to set up list */
98 typedef struct mc_dlist {
99 	struct mc_dlist *next;
100 	struct mc_dlist *prev;
101 	int id;
102 } mc_dlist_t;
103 
104 /* unique segment id */
105 struct seg_info {
106 	mc_dlist_t seg_node;
107 	int nbanks;		/* The number of banks at this segment */
108 	uint32_t ifactor;	/* Max interleave factor at this segment */
109 	uint64_t base;
110 	uint64_t size;		/* memory size per segment */
111 	struct bank_info *head;	/* first bank at this segment */
112 	struct bank_info *tail;	/* last bank at this segment */
113 };
114 
115 /* id = mc_id * nbanks + bank_no */
116 struct bank_info {
117 	mc_dlist_t bank_node;
118 	int local_id;		/* unique local bank id per segment */
119 	int seg_id;		/* unique segment id */
120 	int devgrp_id;		/* unique device group id */
121 	uint64_t mask;		/* If (Physical Address & MASK) == MATCH */
122 	uint64_t match;		/* Physic Address is located at this bank. */
123 	uint64_t base;		/* base address of the logical bank */
124 	uint64_t size;		/* memory size per logical bank */
125 	struct bank_info *next; /* next bank at the same segment */
126 };
127 
128 /* id = id of dgrp_info * ndevices + device_no */
129 struct device_info {
130 	mc_dlist_t dev_node;
131 	char label[MAX_DEVLEN];
132 	uint64_t size;		/* memory size per physical dimm */
133 };
134 
135 /* id = mc_id * ndevgrps + devgrp_no */
136 struct dgrp_info {
137 	mc_dlist_t dgrp_node;
138 	int ndevices;		/* number of physical dimms - always a pair */
139 	int nlogbanks;		/* number of logical banks - single or dual */
140 	int base_device;	/* base density - 128Mb, 256Mb, 512Mb or 1Gb */
141 	int part_type;		/* part type - x4, x8 */
142 	uint64_t base;		/* physical memory base of the dev group */
143 	uint64_t size;		/* total memory size of the dev group */
144 	int deviceids[NDIMMS_PER_DGRP];	/* 2 dimms per group on Jalapeno */
145 };
146 
147 /* id = portid */
148 struct mctrl_info {
149 	mc_dlist_t mctrl_node;
150 	int ndevgrps;		/* The number of dimm groups */
151 	int devgrpids[NDGRPS_PER_MC];
152 	struct dimm_info *dimminfop;
153 };
154 
155 extern int (*p2get_mem_unum)(int, uint64_t, char *, int, int *);
156 extern int (*p2get_mem_info)(int, uint64_t, uint64_t *, uint64_t *,
157     uint64_t *, int *, int *, int *);
158 extern void plat_add_mem_unum_label(char *, int, int, int);
159 
160 uint64_t get_mcr(int);
161 
162 /* #ifdef	DEBUG */
163 
164 #include <sys/promif.h>
165 
166 /* useful debugging level of DPRINTF */
167 #define	MC_ATTACH_DEBUG	0x00000001
168 #define	MC_DETACH_DEBUG	0x00000002
169 #define	MC_CMD_DEBUG	0x00000004
170 #define	MC_REG_DEBUG	0x00000008
171 #define	MC_GUNUM_DEBUG	0x00000010
172 #define	MC_CNSTRC_DEBUG	0x00000020
173 #define	MC_DESTRC_DEBUG	0x00000040
174 #define	MC_LIST_DEBUG	0x00000080
175 
176 
177 #define	_PRINTF printf
178 #define	DPRINTF(flag, args)	if (mc_debug & flag) _PRINTF args;
179 #else
180 #define	DPRINTF(flag, args)
181 
182 /* #endif  DEBUG */
183 
184 #endif	/* !_ASM */
185 
186 /* Memory Control Registers */
187 #define	ASI_MCU_CTRL		0x72
188 #define	MCREG1OFFSET		0x00
189 
190 /* Mask and shift constants for Memory Control Register I */
191 #define	MCREG1_DIMM2_BANK3	0x8000000000000000ULL	/* bit 63 */
192 #define	MCREG1_DIMM1_BANK1	0x4000000000000000ULL	/* bit 62 */
193 #define	MCREG1_DIMM2_BANK2	0x2000000000000000ULL	/* bit 61 */
194 #define	MCREG1_DIMM1_BANK0	0x1000000000000000ULL	/* bit 60 */
195 
196 #define	MCREG1_XOR_ENABLE	0x10000000000LL		/* bit 40 */
197 #define	MCREG1_ADDRGEN2_MASK	0xE000000000LL		/* bits 39:37 */
198 #define	MCREG1_ADDRGEN2_SHIFT	37
199 #define	MCREG1_ADDRGEN1_MASK	0x1C00000000LL		/* bits 36:34 */
200 #define	MCREG1_ADDRGEN1_SHIFT	34
201 #define	BASE_DEVICE_128Mb	0
202 #define	BASE_DEVICE_256Mb	1
203 #define	BASE_DEVICE_512Mb	2
204 #define	BASE_DEVICE_1Gb		3
205 
206 #define	MCREG1_INTERLEAVE_MASK			0x1800000LL	/* bits 24:23 */
207 #define	MCREG1_INTERLEAVE_SHIFT			23
208 #define	INTERLEAVE_DISABLE			0
209 #define	INTERLEAVE_INTEXT_SAME_DIMM_PAIR	1
210 #define	INTERLEAVE_INTERNAL			2
211 #define	INTERLEAVE_INTEXT_BOTH_DIMM_PAIR	3
212 
213 #define	MCREG1_X4DIMM2_MASK	0x200000LL		/* bit 21 */
214 #define	MCREG1_X4DIMM2_SHIFT	21
215 #define	MCREG1_X4DIMM1_MASK	0x100000LL		/* bit 20 */
216 #define	MCREG1_X4DIMM1_SHIFT	20
217 #define	PART_TYPE_X4		1
218 #define	PART_TYPE_X8		0
219 
220 #endif	/* _KERNEL */
221 
222 #ifdef	__cplusplus
223 }
224 #endif
225 
226 #endif	/* _SYS_MC_US3I_H */
227