1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	AUDIO1575_H
27 #define	AUDIO1575_H
28 
29 /*
30  * Header file for the audio1575 device driver
31  */
32 
33 /*
34  * Driver supported configuration information
35  */
36 #define	M1575_NAME			"audio1575"
37 #define	M1575_MOD_NAME			"M1575 audio driver"
38 
39 /*
40  * Implementation specific header file for the audio1575 device driver.
41  */
42 
43 /* Misc. defines */
44 #define	M1575_AUDIO_IO_SPACE		(1)
45 
46 #define	M1575_LOOP_CTR			(100)
47 
48 /* audio direction */
49 #define	M1575_PLAY			(0)
50 #define	M1575_REC			(1)
51 
52 /* Buffer Descriptor  List defines */
53 #define	M1575_BD_NUMS			(32)
54 #define	M1575_NUM_PORTS			(2)
55 #define	M1575_MOD_SIZE			(16)
56 
57 /* kstat interrupt counter define */
58 #define	M1575_ROUNDUP(x, algn)		(((x) + ((algn) - 1)) & ~((algn) - 1))
59 
60 /* PCI CFG SPACE REGISTERS for Audio (Device 29, Function 0) */
61 #define	M1575_PCIPMR_REG	0x42	/* Power Capabilities 16 */
62 #define	M1575_PCIPMCSR_REG	0x44	/* Power Cmd & Status 16 */
63 #define	M1575_PCISCCR_REG	0x48	/* System Cfg Cntrl 16 */
64 #define	M1575_PCIAPMUCR1_REG	0x54	/* Add. PMU Cntrl Reg  8 */
65 #define	M1575_PCISCRR_REG	0x57	/* Scratch Reg  8 */
66 #define	M1575_PCIMISC_REG	0x58	/* Misc Reg  8 */
67 #define	M1575_PCIGCC_REG	0x59	/* Global Clk Control 16 */
68 #define	M1575_PCIACD_REG	0x5C	/* AC97 Codec Detect  8 */
69 #define	M1575_PCIMISC_REG	0x58	/* Misc Reg  8 */
70 #define	M1575_PCIGCLK_REG	0x59	/* Misc Reg  8 */
71 #define	M1575_PCIMSICTRL_REG	0x62	/* MSI Control Reg 16 */
72 #define	M1575_PCIMSIADDR_REG	0x64	/* MSI Address Reg 32 */
73 #define	M1575_PCIMSIDATA_REG	0x68	/* MSI Data Reg 16 */
74 #define	M1575_PCIMSIMASK_REG	0x6C	/* MSI Data Reg 32 */
75 #define	M1575_PCIMSIPEND_REG	0x70	/* MSI Pend Reg 32 */
76 
77 /* Bit definitions for PCI AC97 Clk detect Reg */
78 #define	M1575_PCIACD_CLKDET	0x01
79 #define	M1575_PCIMISC_INTENB	0x40
80 #define	M1575_PCIINT_LINE	0x05
81 
82 /* Base Line Audio I/O Memory Registers */
83 #define	M1575_SCR_REG		0x00	/* System Control Reg 32 */
84 #define	M1575_SSR_REG		0x04	/* System System Reg 32 */
85 #define	M1575_DMACR_REG		0x08	/* DMA Control Reg 32 */
86 #define	M1575_FIFOCR1_REG	0x0C	/* FIFO 1 Control Reg 32 */
87 #define	M1575_INTFCR_REG	0x10	/* Interface Ctrl Reg 32 */
88 #define	M1575_INTRCR_REG	0x14	/* Interrupt Ctrl Reg 32 */
89 #define	M1575_INTRSR_REG	0x18	/* Interrupt Status Reg 32 */
90 #define	M1575_FIFOCR2_REG	0x1C	/* FIFO 2 Control Reg 32 */
91 #define	M1575_CPR_REG		0x20	/* Cmd Port Reg 32 */
92 #define	M1575_SPR_REG		0x24	/* Status Port Reg 32 */
93 #define	M1575_FIFOCR3_REG	0x2C	/* FIFO 3 Control Reg 32 */
94 #define	M1575_TTSR_REG		0x30	/* Tx Tag Slot Reg 32 */
95 #define	M1575_RTSR_REG		0x34	/* Rx Tag Slot Reg 32 */
96 #define	M1575_CSPSR_REG		0x38	/* CSP Status Reg 32 */
97 #define	M1575_CASR_REG		0x3C	/* Codec Access Sem Reg 32 */
98 
99 /* PCM IN Registers */
100 #define	M1575_PCMIBDBAR_REG	0x40 	/* 32 */
101 #define	M1575_PCMICIV_REG	0x44 	/* 8 */
102 #define	M1575_PCMILVIV_REG	0x45 	/* 8 */
103 #define	M1575_PCMISR_REG	0x46 	/* 16 */
104 #define	M1575_PCMIPICB_REG	0x48 	/* 16 */
105 #define	M1575_PCMICR_REG	0x4B 	/* 8 */
106 
107 /* PCM OUT Registers */
108 #define	M1575_PCMOBDBAR_REG	0x50 	/* 32 */
109 #define	M1575_PCMOCIV_REG	0x54 	/* 8 */
110 #define	M1575_PCMOLVIV_REG	0x55 	/* 8 */
111 #define	M1575_PCMOSR_REG	0x56 	/* 16 */
112 #define	M1575_PCMOPICB_REG	0x58 	/* 16 */
113 #define	M1575_PCMOCR_REG	0x5B 	/* 8 */
114 
115 /* MIC In Registers */
116 #define	M1575_MICIBDBAR_REG	0x60 	/* 32 */
117 #define	M1575_MICICIV_REG	0x64 	/* 8 */
118 #define	M1575_MICILVIV_REG	0x65 	/* 8 */
119 #define	M1575_MICISR_REG	0x66 	/* 16 */
120 #define	M1575_MICIPICB_REG	0x68 	/* 16 */
121 #define	M1575_MICICR_REG	0x6B 	/* 8 */
122 
123 /* SPIDOF Registers */
124 #define	M1575_CSPOBDBAR_REG	0x70 	/* 32 */
125 #define	M1575_CSPOCIV_REG	0x74 	/* 8 */
126 #define	M1575_CSPOLVIV_REG	0x75 	/* 8 */
127 #define	M1575_CSPOSR_REG	0x76 	/* 16 */
128 #define	M1575_CSPOPICB_REG	0x78 	/* 16 */
129 #define	M1575_CSPOCR_REG	0x7B 	/* 8 */
130 
131 /* PCM IN2 Registers */
132 #define	M1575_PCMI2BDBAR_REG	0xd0 	/* 32 */
133 #define	M1575_PCMI2CIV_REG	0xd4 	/* 8 */
134 #define	M1575_PCMI2LVIV_REG	0xd5 	/* 8 */
135 #define	M1575_PCMI2SR_REG	0xd6 	/* 16 */
136 #define	M1575_PCMI2PICB_REG	0xd8 	/* 16 */
137 #define	M1575_PCMI2CR_REG	0xdB 	/* 8 */
138 
139 /* MIC2 IN2 Registers */
140 #define	M1575_MICI2BDBAR_REG	0xe0 	/* 32 */
141 #define	M1575_MICI2CIV_REG	0xe4 	/* 8 */
142 #define	M1575_MICI2LVIV_REG	0xe5 	/* 8 */
143 #define	M1575_MICI2SR_REG	0xe6 	/* 16 */
144 #define	M1575_MICI2PICB_REG	0xe8 	/* 16 */
145 #define	M1575_MICI2CR_REG	0xeB 	/* 8 */
146 
147 /* Bits of FIFO Control Register1 */
148 #define	M1575_FIFOCR1_CSPORST	0x80000000 /* SPDIF Out Reset */
149 #define	M1575_FIFOCR1_MICIRST	0x00800000 /* MIC In Reset */
150 #define	M1575_FIFOCR1_PCMORST	0x00008000 /* PCM Out Reset */
151 #define	M1575_FIFOCR1_PCMIRST	0x00000080 /* PCM In Reset */
152 
153 /* Bits of FIFO Control Register2 */
154 #define	M1575_FIFOCR2_SPORST	0x80000000 /* SPDIF Out FIFO Reset */
155 #define	M1575_FIFOCR2_SPIRST	0x00800000 /* SPDIF In  FIFO Reset */
156 #define	M1575_FIFOCR2_LFEORST	0x00008000 /* LFE Out FIFO Reset */
157 #define	M1575_FIFOCR2_CENORST	0x00000080 /* CENTER Out Reset */
158 
159 /* Bits of FIFO Control Register3 */
160 #define	M1575_FIFOCR3_PCMI2RST	0x00800000 /* PCM In2 FIFO  Reset */
161 #define	M1575_FIFOCR3_MICI2RST	0x00008000 /* MIC In2 FIFO Reset */
162 #define	M1575_FIFOCR3_I2SIRST	0x00000080 /* I2S In FIFO Reset */
163 
164 /* Bits of DMA Control Register */
165 #define	M1575_DMACR_PCMISTART	0x00000001
166 #define	M1575_DMACR_PCMOSTART	0x00000002
167 #define	M1575_DMACR_MICISTART	0x00000004
168 #define	M1575_DMACR_CSPOSTART	0x00000008
169 #define	M1575_DMACR_CENOSTART	0x00000010
170 #define	M1575_DMACR_LFEOSTART	0x00000020
171 #define	M1575_DMACR_SPISTART	0x00000040
172 #define	M1575_DMACR_SPOSTART	0x00000080
173 #define	M1575_DMACR_I2SISTART	0x00000100
174 #define	M1575_DMACR_PCMI2START	0x00000200
175 #define	M1575_DMACR_MICI2START	0x00000400
176 #define	M1575_DMACR_PCMIPAUSE	0x00010000
177 #define	M1575_DMACR_PCMOPAUSE	0x00020000
178 #define	M1575_DMACR_MICIPAUSE	0x00040000
179 #define	M1575_DMACR_CSPOPAUSE	0x00080000
180 #define	M1575_DMACR_CENOPAUSE	0x00100000
181 #define	M1575_DMACR_LFEOPAUSE	0x00200000
182 #define	M1575_DMACR_SPIPAUSE	0x00400000
183 #define	M1575_DMACR_SPOPAUSE	0x00800000
184 #define	M1575_DMACR_I2SIPAUSE	0x01000000
185 #define	M1575_DMACR_PCMI2PAUSE	0x02000000
186 #define	M1575_DMACR_MICI2PAUSE	0x04000000
187 
188 #define	M1575_DMACR_PAUSE_ALL	0x07ff0000
189 
190 /* Bits of INTRSR Interrupt Status Register */
191 #define	M1575_INTRSR_GPIOINTR	0x0000002
192 #define	M1575_INTRSR_SPRINTR	0x0000020
193 #define	M1575_INTRSR_CPRINTR	0x0000080
194 #define	M1575_INTRSR_PCMIINTR   0x0010000
195 #define	M1575_INTRSR_PCMOINTR 	0x0020000
196 #define	M1575_INTRSR_MICIINTR  	0x0040000
197 #define	M1575_INTRSR_CSPOINTR  	0x0080000
198 #define	M1575_INTRSR_CENOINTR  	0x0100000
199 #define	M1575_INTRSR_LFEOINTR  	0x0200000
200 #define	M1575_INTRSR_SPIINTR	0x0400000
201 #define	M1575_INTRSR_SPOINTR	0x0800000
202 #define	M1575_INTRSR_I2SIINTR	0x1000000
203 #define	M1575_INTRSR_PCMI2INTR	0x2000000
204 #define	M1575_INTRSR_MICI2INTR	0x4000000
205 
206 #define	M1575_INTR_MASK (M1575_INTRSR_GPIOINTR |\
207 	M1575_INTRSR_SPRINTR  |\
208 	M1575_INTRSR_CPRINTR  |\
209 	M1575_INTRSR_PCMIINTR |\
210 	M1575_INTRSR_PCMOINTR |\
211 	M1575_INTRSR_MICIINTR |\
212 	M1575_INTRSR_CSPOINTR |\
213 	M1575_INTRSR_CENOINTR |\
214 	M1575_INTRSR_LFEOINTR |\
215 	M1575_INTRSR_SPIINTR  |\
216 	M1575_INTRSR_SPOINTR  |\
217 	M1575_INTRSR_I2SIINTR |\
218 	M1575_INTRSR_PCMI2INTR|\
219 	M1575_INTRSR_MICI2INTR)
220 
221 #define	M1575_UNUSED_INTR_MASK (M1575_INTRSR_GPIOINTR |\
222 	M1575_INTRSR_SPRINTR  |\
223 	M1575_INTRSR_CPRINTR  |\
224 	M1575_INTRSR_MICIINTR |\
225 	M1575_INTRSR_CSPOINTR |\
226 	M1575_INTRSR_CENOINTR |\
227 	M1575_INTRSR_LFEOINTR |\
228 	M1575_INTRSR_SPIINTR  |\
229 	M1575_INTRSR_SPOINTR  |\
230 	M1575_INTRSR_I2SIINTR |\
231 	M1575_INTRSR_PCMI2INTR|\
232 	M1575_INTRSR_MICI2INTR)
233 
234 /* Defines a generic clear for all MIC and PCM Status Registers */
235 #define	M1575_SR_CLR		0x001e
236 #define	M1575_SR_DMACS		0x0001
237 
238 /* Defines a generic RESET for all MIC and PCM Control Registers */
239 #define	M1575_CR_IOCE		0x10
240 #define	M1575_CR_RR		0x02
241 
242 /* Bits of PCM In Status Register */
243 #define	M1575_PCMISR_DMACS	0x01 	/* DMACS=0 if DMA Engine is IDLE */
244 #define	M1575_PCMISR_CELV	0x02
245 #define	M1575_PCMISR_LVBCI	0x04
246 #define	M1575_PCMISR_BCIS	0x08
247 #define	M1575_PCMISR_FIFOE	0x10
248 
249 /* Bits in PCM In Control Register */
250 #define	M1575_PCMICR_RR		0x02	/* Reset */
251 #define	M1575_PCMICR_LVBIE	0x04	/* Last valid Buffer Intr Enable */
252 #define	M1575_PCMICR_IOCE	0x10	/* Intr On Completion Enable */
253 
254 /* Bits of PCM Out Status Register */
255 #define	M1575_PCMOSR_DMACS	0x01	/* DMACS=0 if DMA Engine is IDLE */
256 #define	M1575_PCMOSR_CELV	0x02
257 #define	M1575_PCMOSR_LVBCI	0x04
258 #define	M1575_PCMOSR_BCIS	0x08
259 #define	M1575_PCMOSR_FIFOE	0x10
260 
261 /* Bits in PCM Out Control Register */
262 #define	M1575_PCMOCR_RR		0x02	/* Reset */
263 #define	M1575_PCMOCR_LVBIE	0x04	/* Last valid Buffer Intr Enable */
264 #define	M1575_PCMOCR_IOCE	0x10	/* Intr On Completion Enable */
265 
266 /* Bits of MIC In Status Register */
267 #define	M1575_MICISR_DMACS	0x01	/* DMACS=0 if DMA Engine is IDLE */
268 #define	M1575_MICISR_CELV	0x02
269 #define	M1575_MICISR_LVBCI	0x04
270 #define	M1575_MICISR_BCIS	0x08
271 #define	M1575_MICISR_FIFOE	0x10
272 
273 /* Bits in PCM In Control Register */
274 #define	M1575_MICICR_RR		0x02	/* Reset */
275 #define	M1575_MICICR_LVBIE	0x04	/* Last valid Buffer Intr Enable */
276 #define	M1575_MICICR_IOCE	0x10	/* Intr On Completion Enable */
277 
278 /* Bits in System Control  Register */
279 #define	M1575_SCR_WARMRST	0x00000001
280 #define	M1575_SCR_COLDRST	0x00000002
281 #define	M1575_SCR_SPDIF_SLOT	0x00300000	/* 1=7/8, 2=6/9, 3=10/11 */
282 #define	M1575_SCR_RECMOD	0x000c0000	/* 0 = 16bit, 1=20 bit */
283 #define	M1575_SCR_PCMMOD	0x00030000	/* 0 = 16bit, 1=20 bit */
284 #define	M1575_SCR_6CHL_MASK	0x0000c000	/* FL, FR, C, BL, BR, LFE */
285 #define	M1575_SCR_6CHL_0	0x00000000	/* channel ordering */
286 #define	M1575_SCR_6CHL_1	0x00004000	/* FL, C, FR, BL, BR, LFE */
287 #define	M1575_SCR_6CHL_2	0x00008000	/* FL, FR, C, LFE, BL, BR */
288 #define	M1575_SCR_6CHL_3	0x0000c000	/* FL, C, FR, LFE, BL, BR */
289 #define	M1575_SCR_CHAMOD_MASK	0x00000300	/* 2, 4, or 6 channel */
290 #define	M1575_SCR_CHAMOD_2	0x00000000	/* 2 channel */
291 #define	M1575_SCR_CHAMOD_4	0x00000100	/* 4 channel surround */
292 #define	M1575_SCR_CHAMOD_6	0x00000200	/* 6 channel (5.1) surround */
293 #define	M1575_SCR_DRENT		0x40000000
294 #define	M1575_SCR_MSTRST	0x80000000
295 
296 /* Bits in System Status Register */
297 #define	M1575_SSR_RSTBLK	0x00000002
298 #define	M1575_SSR_FACCS_MSK	0x00000018
299 #define	M1575_SSR_SCID		0x00000040
300 
301 /* Bits in Command Port Register */
302 #define	M1575_CPR_ACSCS		0x0100 /* Audio Codec for cmd 1=codec 2 */
303 #define	M1575_CPR_READ		0x0080
304 
305 /* Bits in Cmd Status Port Register */
306 #define	M1575_CSPSR_SUCC	0x08	/* cmd successful */
307 #define	M1575_CSPSR_RDRDY	0x02	/* ready for read cmd */
308 #define	M1575_CSPSR_WRRDY	0x01	/* ready for write cmd */
309 #define	M1575_PCMI2CR_RR	0x02	/* Reset */
310 #define	M1575_MICI2CR_RR	0x02	/* Reset */
311 #define	M1575_CSPOCR_RR		0x02	/* Reset */
312 
313 /* Bits in  Interface  Control  Register */
314 #define	M1575_INTFCR_RSTREL		0x02000000
315 #define	M1575_INTFCR_RSTBLK		0x00200000
316 #define	M1575_INTFCR_MICENB		0x00100000
317 #define	M1575_INTFCR_PCMIENB		0x00080000
318 #define	M1575_INTFCR_MICI2ENB		0x00040000
319 #define	M1575_INTFCR_PCMI2ENB		0x00020000
320 #define	M1575_INTFCR_MICI2SEL		0x00008000
321 #define	M1575_INTFCR_MICISEL		0x00004000
322 #define	M1575_INTFCR_PCMOENB		0x00000002
323 
324 #define	M1575_INTRCR_CPRINTR		0x00000080
325 #define	M1575_INTRCR_SPRINTR		0x00000020
326 #define	M1575_INTRCR_GPIOINTR		0x00000002
327 
328 /* Bits of Recv Tag Slot Register */
329 #define	M1575_RTSR_SACRDY	0x20u	/* 2nd Audio Codec Rdy */
330 #define	M1575_RTSR_FACRDY	0x80u	/* 1st Audio Codec Rdy */
331 
332 /* Semaphore busy */
333 #define	M1575_CASR_SEMBSY	0x80000000
334 
335 /*
336  * buffer descripter list entry, see M1575 datasheet
337  */
338 #define	IOC 0x8000
339 #define	BUP 0x4000
340 
341 struct m1575_bd_entry {
342 	uint32_t buf_base;	/* the address of the buffer */
343 	uint16_t buf_len;	/* the number of samples */
344 	uint16_t buf_cmd;
345 };
346 typedef struct m1575_bd_entry m1575_bd_entry_t;
347 
348 struct audio1575_port {
349 	struct audio1575_state	*statep;
350 	ddi_dma_handle_t	samp_dmah;
351 	ddi_acc_handle_t	samp_acch;
352 	size_t			samp_size;
353 	caddr_t			samp_kaddr;
354 	uint32_t		samp_paddr;
355 
356 	ddi_dma_handle_t	bdl_dmah;
357 	ddi_acc_handle_t	bdl_acch;
358 	size_t			bdl_size;
359 	caddr_t			bdl_kaddr;
360 	uint32_t		bdl_paddr;
361 
362 	int			num;
363 	unsigned		nframes;
364 	uint32_t		offset;
365 	uint64_t		count;
366 	uint8_t			nchan;
367 
368 	unsigned		sync_dir;
369 
370 	audio_engine_t		*engine;
371 };
372 typedef struct audio1575_port audio1575_port_t;
373 
374 
375 /*
376  * audio1575_state_t per instance state and operation data
377  */
378 struct audio1575_state	{
379 	kmutex_t		lock;			/* intr mutex */
380 	dev_info_t		*dip;			/* dev instance ptr */
381 	audio_dev_t		*adev;			/* audio handle */
382 	ac97_t			*ac97;			/* ac'97 handle */
383 	audio1575_port_t	*ports[2];		/* DMA engines */
384 
385 	ddi_acc_handle_t	pcih;			/* pci config space */
386 
387 	ddi_acc_handle_t	regsh;			/* audio i/o regs */
388 	caddr_t			regsp;			/* base of i/o regs */
389 
390 	uint8_t			maxch;			/* maximum channels */
391 };
392 typedef struct audio1575_state audio1575_state_t;
393 
394 /* audio i/o register macros */
395 #define	GET8(reg)						\
396 	ddi_get8(statep->regsh, (void *)(statep->regsp + (reg)))
397 
398 #define	GET16(reg)						\
399 	ddi_get16(statep->regsh, (void *)(statep->regsp + (reg)))
400 
401 #define	GET32(reg)						\
402 	ddi_get32(statep->regsh, (void *)(statep->regsp + (reg)))
403 
404 #define	PUT8(reg, val)						\
405 	ddi_put8(statep->regsh,	(void *)(statep->regsp + (reg)), (val))
406 
407 #define	PUT16(reg, val)						\
408 	ddi_put16(statep->regsh, (void *)(statep->regsp + (reg)), (val))
409 
410 #define	PUT32(reg, val)						\
411 	ddi_put32(statep->regsh, (void *)(statep->regsp + (reg)), (val))
412 
413 #define	SET8(reg, bit)		PUT8(reg, GET8(reg) | (bit))
414 #define	SET16(reg, bit)		PUT16(reg, GET16(reg) | (bit))
415 #define	SET32(reg, bit)		PUT32(reg, GET32(reg) | (bit))
416 #define	CLR8(reg, bit)		PUT8(reg, GET8(reg) & ~(bit))
417 #define	CLR16(reg, bit)		PUT16(reg, GET16(reg) & ~(bit))
418 #define	CLR32(reg, bit)		PUT32(reg, GET32(reg) & ~(bit))
419 
420 
421 #endif	/* AUDIO1575_H */
422