xref: /illumos-gate/usr/src/uts/common/sys/1394/ieee1394.h (revision 2d6eb4a5)
1 /*
2  * CDDL HEADER START
3  *
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5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
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10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
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14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
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18  * information: Portions Copyright [yyyy] [name of copyright owner]
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20  * CDDL HEADER END
21  */
22 /*
23  * Copyright (c) 1999-2000 by Sun Microsystems, Inc.
24  * All rights reserved.
25  */
26 
27 #ifndef _SYS_1394_IEEE1394_H
28 #define	_SYS_1394_IEEE1394_H
29 
30 /*
31  * ieee1394.h
32  *    This file contains various defines that go with IEEE 1394
33  */
34 
35 #ifdef	__cplusplus
36 extern "C" {
37 #endif
38 
39 
40 /*
41  * IEEE1394_MAX_NODES defines the maximum number of nodes
42  * that can be addressed on a single 1394 bus.  There are
43  * a 63 physical nodes that can be present and 1 broadcast
44  * node id.  The range of 1394 nodeid's are
45  * 0 ... (IEEE1394_MAX_NODES - 1)
46  */
47 #define	IEEE1394_MAX_NODES		64
48 
49 /* The node id for broadcast writes */
50 #define	IEEE1394_BROADCAST_NODEID	63
51 
52 /* Maximum number of ports per node */
53 #define	IEEE1394_MAX_NUM_PORTS		16
54 
55 #define	IEEE1394_BUS_NUM_MASK		0x0000FFC0
56 #define	IEEE1394_LOCAL_BUS		0x3FF
57 
58 #define	IEEE1394_NODE_NUM_MASK		0x0000003F
59 #define	IEEE1394_NODE_NUM(DATA)		((DATA) & IEEE1394_NODE_NUM_MASK)
60 
61 #define	IEEE1394_BUS_CYCLES_PER_SEC	8000
62 
63 /* IEEE 1394 Bus related definitions */
64 #define	IEEE1394_ADDR_NODE_ID_MASK	0xFFFF000000000000
65 #define	IEEE1394_ADDR_NODE_ID_SHIFT	48
66 #define	IEEE1394_ADDR_NODE_ID(ADDR)				\
67 	(((ADDR) & IEEE1394_ADDR_NODE_ID_MASK) >>		\
68 	    IEEE1394_ADDR_NODE_ID_SHIFT)
69 
70 #define	IEEE1394_ADDR_BUS_ID_MASK	0xFFC0000000000000
71 #define	IEEE1394_ADDR_BUS_ID_SHIFT	54
72 #define	IEEE1394_ADDR_BUS_ID(ADDR)				\
73 	(((ADDR) & IEEE1394_ADDR_BUS_ID_MASK) >>		\
74 	    IEEE1394_ADDR_BUS_ID_SHIFT)
75 
76 #define	IEEE1394_ADDR_PHY_ID_MASK	0x003F000000000000
77 #define	IEEE1394_ADDR_PHY_ID_SHIFT	48
78 #define	IEEE1394_ADDR_PHY_ID(ADDR)				\
79 	(((ADDR) & IEEE1394_ADDR_PHY_ID_MASK) >>		\
80 	    IEEE1394_ADDR_PHY_ID_SHIFT)
81 
82 #define	IEEE1394_ADDR_OFFSET_MASK	0x0000FFFFFFFFFFFF
83 
84 /* IEEE 1394 data sizes */
85 #define	IEEE1394_QUADLET		(sizeof (uint32_t))
86 #define	IEEE1394_OCTLET			(sizeof (uint64_t))
87 
88 /* Still need to look at these */
89 /* TCODES - packet transaction codes (as defined in 1394-1995 6.2.4.5) */
90 #define	IEEE1394_TCODE_WRITE_QUADLET		0x0
91 #define	IEEE1394_TCODE_WRITE_BLOCK		0x1
92 #define	IEEE1394_TCODE_WRITE_RESP		0x2
93 #define	IEEE1394_TCODE_RES1			0x3
94 #define	IEEE1394_TCODE_READ_QUADLET		0x4
95 #define	IEEE1394_TCODE_READ_BLOCK		0x5
96 #define	IEEE1394_TCODE_READ_QUADLET_RESP	0x6
97 #define	IEEE1394_TCODE_READ_BLOCK_RESP		0x7
98 #define	IEEE1394_TCODE_CYCLE_START		0x8
99 #define	IEEE1394_TCODE_LOCK			0x9
100 #define	IEEE1394_TCODE_ISOCH			0xA
101 #define	IEEE1394_TCODE_LOCK_RESP		0xB
102 #define	IEEE1394_TCODE_RES2			0xC
103 #define	IEEE1394_TCODE_RES3			0xD
104 #define	IEEE1394_TCODE_PHY			0xE
105 #define	IEEE1394_TCODE_RES4			0xF
106 
107 #define	IEEE1394_RESP_COMPLETE			0x0
108 #define	IEEE1394_RESP_CONFLICT_ERROR		0x4
109 #define	IEEE1394_RESP_DATA_ERROR		0x5
110 #define	IEEE1394_RESP_TYPE_ERROR		0x6
111 #define	IEEE1394_RESP_ADDRESS_ERROR		0x7
112 
113 #define	IEEE1394_ISOCH_HDR_QUAD_SZ	3
114 
115 /* Self ID packet definitions */
116 #define	IEEE1394_SELFID_PCKT_ID_MASK	0xC0000000
117 #define	IEEE1394_SELFID_PCKT_ID_SHIFT	30
118 #define	IEEE1394_SELFID_PCKT_ID_VALID	0x2
119 #define	IEEE1394_SELFID_ISVALID(S_PKT)				\
120 	(~((S_PKT)->spkt_data ^ (S_PKT)->spkt_inverse) ? 0 : 1)
121 
122 #define	IEEE1394_SELFID_PHYID_MASK	0x3F000000
123 #define	IEEE1394_SELFID_PHYID_SHIFT	24
124 #define	IEEE1394_SELFID_PHYID(S_PKT)				\
125 	(((S_PKT)->spkt_data & IEEE1394_SELFID_PHYID_MASK) >>	\
126 	    IEEE1394_SELFID_PHYID_SHIFT)
127 
128 /* SelfID PKT #0 */
129 #define	IEEE1394_SELFID_L_MASK		0x00400000
130 #define	IEEE1394_SELFID_L_SHIFT		22
131 #define	IEEE1394_SELFID_ISLINKON(S_PKT)				\
132 	(((S_PKT)->spkt_data & IEEE1394_SELFID_L_MASK) >>	\
133 	    IEEE1394_SELFID_L_SHIFT)
134 
135 #define	IEEE1394_SELFID_GAP_CNT_MASK	0x003F0000
136 #define	IEEE1394_SELFID_GAP_CNT_SHIFT	16
137 #define	IEEE1394_SELFID_GAP_CNT(S_PKT)				\
138 	(((S_PKT)->spkt_data & IEEE1394_SELFID_GAP_CNT_MASK) >>	\
139 	    IEEE1394_SELFID_GAP_CNT_SHIFT)
140 
141 #define	IEEE1394_SELFID_SP_MASK		0x0000C000
142 #define	IEEE1394_SELFID_SP_SHIFT	14
143 
144 #define	IEEE1394_SELFID_DEL_MASK	(0x00003000)
145 #define	IEEE1394_SELFID_DEL_SHIFT	12
146 #define	IEEE1394_SELFID_DELAY(S_PKT)				\
147 	(((S_PKT)->spkt_data & IEEE1394_SELFID_DEL_MASK) >>	\
148 	    IEEE1394_SELFID_DEL_SHIFT)
149 
150 #define	IEEE1394_SELFID_C_MASK		0x00000800
151 #define	IEEE1394_SELFID_C_SHIFT		11
152 #define	IEEE1394_SELFID_ISCONTENDER(S_PKT)			\
153 	(((S_PKT)->spkt_data & IEEE1394_SELFID_C_MASK) >>	\
154 	    IEEE1394_SELFID_C_SHIFT)
155 
156 #define	IEEE1394_SELFID_PWR_MASK	0x00000700
157 #define	IEEE1394_SELFID_PWR_SHIFT	8
158 #define	IEEE1394_SELFID_POWER(S_PKT)				\
159 	(((S_PKT)->spkt_data & IEEE1394_SELFID_PWR_MASK) >>	\
160 	    IEEE1394_SELFID_PWR_SHIFT)
161 
162 #define	IEEE1394_SELFID_PORT_TO_CHILD		0x3
163 #define	IEEE1394_SELFID_PORT_TO_PARENT		0x2
164 #define	IEEE1394_SELFID_PORT_NOT_CONNECTED	0x1
165 #define	IEEE1394_SELFID_PORT_NO_PORT		0x0
166 
167 #define	IEEE1394_SELFID_I_MASK		0x00000002
168 #define	IEEE1394_SELFID_I_SHIFT		1
169 #define	IEEE1394_SELFID_INITIATED_RESET(S_PKT)			\
170 	(((S_PKT)->spkt_data & IEEE1394_SELFID_I_MASK) >>	\
171 	    IEEE1394_SELFID_I_SHIFT)
172 
173 #define	IEEE1394_SELFID_M_MASK		0x00000001
174 #define	IEEE1394_SELFID_M_SHIFT		0
175 #define	IEEE1394_SELFID_ISMORE(S_PKT)				\
176 	(((S_PKT)->spkt_data & IEEE1394_SELFID_M_MASK) >>	\
177 	    IEEE1394_SELFID_M_SHIFT)
178 
179 #define	IEEE1394_SELFID_PORT_OFFSET_FIRST	6
180 
181 /* SelfID PKT #1 (n=0) */
182 #define	IEEE1394_SELFID_N_MASK		0x00700000
183 #define	IEEE1394_SELFID_N_SHIFT		20
184 #define	IEEE1394_SELFID_PKT_NUM(S_PKT)				\
185 	(((S_PKT)->spkt_data & IEEE1394_SELFID_N_MASK) >>	\
186 	    IEEE1394_SELFID_N_SHIFT)
187 
188 #define	IEEE1394_SELFID_PORT_OFFSET_OTHERS	16
189 
190 /* PHY Config Packet definitions */
191 #define	IEEE1394_PHY_CONFIG_T_BIT_MASK		0x00400000
192 #define	IEEE1394_PHY_CONFIG_T_BIT_SHIFT		22
193 #define	IEEE1394_PHY_CONFIG_GAP_CNT_MASK	0x003F0000
194 #define	IEEE1394_PHY_CONFIG_GAP_CNT_SHIFT	16
195 
196 #define	IEEE1394_PHY_CONFIG_R_BIT_MASK		0x00800000
197 #define	IEEE1394_PHY_CONFIG_R_BIT_SHIFT		23
198 #define	IEEE1394_PHY_CONFIG_ROOT_HOLD_MASK	0x3F000000
199 #define	IEEE1394_PHY_CONFIG_ROOT_HOLD_SHIFT	24
200 
201 
202 /*
203  * CSR Registers and register fields.
204  */
205 /* CSR Register Addresses (IEEE1394-1995 8.3.2.2) */
206 #define	IEEE1394_CSR_STATE_CLEAR	0xFFFFF0000000
207 #define	IEEE1394_CSR_STATE_SET		0xFFFFF0000004
208 #define	IEEE1394_CSR_NODE_IDS		0xFFFFF0000008
209 #define	IEEE1394_CSR_RESET_START	0xFFFFF000000C
210 #define	IEEE1394_CSR_SPLIT_TIMEOUT_HI	0xFFFFF0000018
211 #define	IEEE1394_CSR_SPLIT_TIMEOUT_LO	0xFFFFF000001C
212 #define	IEEE1394_CSR_ARG_HI		0xFFFFF0000020
213 #define	IEEE1394_CSR_ARG_LO		0xFFFFF0000024
214 #define	IEEE1394_CSR_TEST_START		0xFFFFF0000028
215 #define	IEEE1394_CSR_TEST_STATUS	0xFFFFF000002C
216 
217 /* Optional Register Addresses */
218 #define	IEEE1394_CSR_INTERRUPT_TARGET	0xFFFFF0000050
219 #define	IEEE1394_CSR_INTERRUPT_MASK	0xFFFFF0000054
220 #define	IEEE1394_CSR_CLOCK_VALUE	0xFFFFF0000058
221 #define	IEEE1394_CSR_CLOCK_VALUE_SZ	0x28
222 #define	IEEE1394_CSR_MESSAGE_REQUEST	0xFFFFF0000080
223 #define	IEEE1394_CSR_MESSAGE_REQUEST_SZ	0x80
224 
225 /* Serial Bus CSR Register Addresss (IEEE1394-1995 8.3.2.3) */
226 #define	IEEE1394_SCSR_CYCLE_TIME	0xFFFFF0000200
227 #define	IEEE1394_SCSR_BUS_TIME		0xFFFFF0000204
228 #define	IEEE1394_SCSR_PWRFAIL_IMMINENT	0xFFFFF0000208
229 #define	IEEE1394_SCSR_PWRSRC		0xFFFFF000020C
230 #define	IEEE1394_SCSR_BUSY_TIMEOUT	0xFFFFF0000210
231 #define	IEEE1394_SCSR_BUSMGR_ID		0xFFFFF000021C
232 #define	IEEE1394_SCSR_BANDWIDTH_AVAIL	0xFFFFF0000220
233 #define	IEEE1394_SCSR_CHANS_AVAIL_HI	0xFFFFF0000224
234 #define	IEEE1394_SCSR_CHANS_AVAIL_LO	0xFFFFF0000228
235 
236 /* Config ROM Address */
237 #define	IEEE1394_CONFIG_ROM_ADDR	0xFFFFF0000400
238 #define	IEEE1394_CONFIG_ROM_SZ		0x400
239 #define	IEEE1394_CONFIG_ROM_QUAD_SZ	0x100
240 
241 /*  Unit CSR Register Addresses */
242 #define	IEEE1394_UCSR_TOPOLOGY_MAP	0xFFFFF0001000
243 #define	IEEE1394_UCSR_TOPOLOGY_MAP_SZ	0x400
244 #define	IEEE1394_UCSR_SPEED_MAP		0xFFFFF0002000
245 #define	IEEE1394_UCSR_SPEED_MAP_SZ	0x1000
246 
247 /* Boundary for "reserved" CSR registers */
248 #define	IEEE1394_UCSR_RESERVED_BOUNDARY	0xFFFFF0010000
249 
250 #define	IEEE1394_CSR_OFFSET_MASK	0x00000000FFFF
251 
252 /* 1394 Bus Speeds */
253 #define	IEEE1394_S100			0
254 #define	IEEE1394_S200			1
255 #define	IEEE1394_S400			2
256 #define	IEEE1394_S800			3
257 #define	IEEE1394_S1600			4
258 #define	IEEE1394_S3200			5
259 
260 /* IEEE 1394 Bandwidth bounds */
261 #define	IEEE1394_BANDWIDTH_MIN		0
262 #define	IEEE1394_BANDWIDTH_MAX		0x1333
263 
264 /* Speed Map specific defines */
265 #define	IEEE1394_SPEED_MAP_CRC_LEN	0x03F1
266 #define	IEEE1394_SPEED_MAP_LEN_MASK	0x0000FFFF
267 #define	IEEE1394_SPEED_MAP_LEN_SHIFT	16
268 #define	IEEE1394_SPEED_MAP_DATA_LEN	0x0FBE
269 
270 /* Topology Map specific defines */
271 #define	IEEE1394_TOP_MAP_LEN_MASK	0x0000FFFF
272 #define	IEEE1394_TOP_MAP_LEN_SHIFT	16
273 
274 /* Config ROM specific defines */
275 #define	IEEE1394_CFG_ROM_CRC_VALUE_MASK	0x0000FFFF
276 #define	IEEE1394_CFG_ROM_CRC_LEN_SHIFT	16
277 #define	IEEE1394_CFG_ROM_CRC_LEN_MASK	0xFF
278 #define	IEEE1394_CFG_ROM_LEN_SHIFT	16
279 
280 /* CRC16 defines */
281 #define	IEEE1394_CRC16_MASK		0xFFFF
282 
283 /* Bit positions in the STATE register */
284 #define	IEEE1394_CSR_STATE_CMSTR	0x00000100
285 #define	IEEE1394_CSR_STATE_DREQ		0x00000040
286 #define	IEEE1394_CSR_STATE_ABDICATE	0x00000400
287 
288 /* Positions in the BUS_INFO_BLOCK */
289 #define	IEEE1394_BIB_LNK_SPD_MASK	0x00000007
290 #define	IEEE1394_BIB_LNK_SPD_SHIFT	0
291 #define	IEEE1394_BIB_GEN_MASK		0x000000F0
292 #define	IEEE1394_BIB_GEN_SHIFT		4
293 #define	IEEE1394_BIB_MROM_MASK		0x00000300
294 #define	IEEE1394_BIB_MROM_SHIFT		8
295 #define	IEEE1394_BIB_IRMC_MASK		0x80000000
296 #define	IEEE1394_BIB_IRMC_SHIFT		31
297 #define	IEEE1394_BIB_BMC_MASK		0x10000000
298 #define	IEEE1394_BIB_BMC_SHIFT		28
299 #define	IEEE1394_BIB_CMC_MASK		0x40000000
300 #define	IEEE1394_BIB_CMC_SHIFT		30
301 #define	IEEE1394_BIB_MAXREC_MASK	0x0000F000
302 #define	IEEE1394_BIB_MAXREC_SHIFT	12
303 
304 #define	IEEE1394_BIB_QUAD_SZ		5
305 #define	IEEE1394_BIB_SZ			0x14
306 
307 /* Bus Manager specific defines */
308 #define	IEEE1394_BM_IRM_TIMEOUT		625000
309 #define	IEEE1394_BM_INCUMBENT_TIMEOUT	125000
310 #ifdef __cplusplus
311 }
312 #endif
313 
314 #endif	/* _SYS_1394_IEEE1394_H */
315