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2 
3   Copyright (c) 2013-2018, Intel Corporation
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5 
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12    2. Redistributions in binary form must reproduce the above copyright
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32 ******************************************************************************/
33 /*$FreeBSD$*/
34 
35 #ifndef _I40E_DCB_H_
36 #define _I40E_DCB_H_
37 
38 #include "i40e_type.h"
39 
40 #define I40E_DCBX_OFFLOAD_DISABLED	0
41 #define I40E_DCBX_OFFLOAD_ENABLED	1
42 
43 #define I40E_DCBX_STATUS_NOT_STARTED	0
44 #define I40E_DCBX_STATUS_IN_PROGRESS	1
45 #define I40E_DCBX_STATUS_DONE		2
46 #define I40E_DCBX_STATUS_MULTIPLE_PEERS	3
47 #define I40E_DCBX_STATUS_DISABLED	7
48 
49 #define I40E_TLV_TYPE_END		0
50 #define I40E_TLV_TYPE_ORG		127
51 
52 #define I40E_IEEE_8021QAZ_OUI		0x0080C2
53 #define I40E_IEEE_SUBTYPE_ETS_CFG	9
54 #define I40E_IEEE_SUBTYPE_ETS_REC	10
55 #define I40E_IEEE_SUBTYPE_PFC_CFG	11
56 #define I40E_IEEE_SUBTYPE_APP_PRI	12
57 
58 #define I40E_CEE_DCBX_OUI		0x001b21
59 #define I40E_CEE_DCBX_TYPE		2
60 
61 #define I40E_CEE_SUBTYPE_CTRL		1
62 #define I40E_CEE_SUBTYPE_PG_CFG		2
63 #define I40E_CEE_SUBTYPE_PFC_CFG	3
64 #define I40E_CEE_SUBTYPE_APP_PRI	4
65 
66 #define I40E_CEE_MAX_FEAT_TYPE		3
67 #define I40E_LLDP_ADMINSTATUS_DISABLED		0
68 #define I40E_LLDP_ADMINSTATUS_ENABLED_RX	1
69 #define I40E_LLDP_ADMINSTATUS_ENABLED_TX	2
70 #define I40E_LLDP_ADMINSTATUS_ENABLED_RXTX	3
71 
72 #define I40E_LLDP_CURRENT_STATUS_XL710_OFFSET	0x2B
73 #define I40E_LLDP_CURRENT_STATUS_X722_OFFSET	0x31
74 #define I40E_LLDP_CURRENT_STATUS_OFFSET		1
75 #define I40E_LLDP_CURRENT_STATUS_SIZE		1
76 
77 /* Defines for LLDP TLV header */
78 #define I40E_LLDP_MIB_HLEN		14
79 #define I40E_LLDP_TLV_LEN_SHIFT		0
80 #define I40E_LLDP_TLV_LEN_MASK		(0x01FF << I40E_LLDP_TLV_LEN_SHIFT)
81 #define I40E_LLDP_TLV_TYPE_SHIFT	9
82 #define I40E_LLDP_TLV_TYPE_MASK		(0x7F << I40E_LLDP_TLV_TYPE_SHIFT)
83 #define I40E_LLDP_TLV_SUBTYPE_SHIFT	0
84 #define I40E_LLDP_TLV_SUBTYPE_MASK	(0xFF << I40E_LLDP_TLV_SUBTYPE_SHIFT)
85 #define I40E_LLDP_TLV_OUI_SHIFT		8
86 #define I40E_LLDP_TLV_OUI_MASK		(0xFFFFFF << I40E_LLDP_TLV_OUI_SHIFT)
87 
88 /* Defines for IEEE ETS TLV */
89 #define I40E_IEEE_ETS_MAXTC_SHIFT	0
90 #define I40E_IEEE_ETS_MAXTC_MASK	(0x7 << I40E_IEEE_ETS_MAXTC_SHIFT)
91 #define I40E_IEEE_ETS_CBS_SHIFT		6
92 #define I40E_IEEE_ETS_CBS_MASK		BIT(I40E_IEEE_ETS_CBS_SHIFT)
93 #define I40E_IEEE_ETS_WILLING_SHIFT	7
94 #define I40E_IEEE_ETS_WILLING_MASK	BIT(I40E_IEEE_ETS_WILLING_SHIFT)
95 #define I40E_IEEE_ETS_PRIO_0_SHIFT	0
96 #define I40E_IEEE_ETS_PRIO_0_MASK	(0x7 << I40E_IEEE_ETS_PRIO_0_SHIFT)
97 #define I40E_IEEE_ETS_PRIO_1_SHIFT	4
98 #define I40E_IEEE_ETS_PRIO_1_MASK	(0x7 << I40E_IEEE_ETS_PRIO_1_SHIFT)
99 #define I40E_CEE_PGID_PRIO_0_SHIFT	0
100 #define I40E_CEE_PGID_PRIO_0_MASK	(0xF << I40E_CEE_PGID_PRIO_0_SHIFT)
101 #define I40E_CEE_PGID_PRIO_1_SHIFT	4
102 #define I40E_CEE_PGID_PRIO_1_MASK	(0xF << I40E_CEE_PGID_PRIO_1_SHIFT)
103 #define I40E_CEE_PGID_STRICT		15
104 
105 /* Defines for IEEE TSA types */
106 #define I40E_IEEE_TSA_STRICT		0
107 #define I40E_IEEE_TSA_CBS		1
108 #define I40E_IEEE_TSA_ETS		2
109 #define I40E_IEEE_TSA_VENDOR		255
110 
111 /* Defines for IEEE PFC TLV */
112 #define I40E_IEEE_PFC_CAP_SHIFT		0
113 #define I40E_IEEE_PFC_CAP_MASK		(0xF << I40E_IEEE_PFC_CAP_SHIFT)
114 #define I40E_IEEE_PFC_MBC_SHIFT		6
115 #define I40E_IEEE_PFC_MBC_MASK		BIT(I40E_IEEE_PFC_MBC_SHIFT)
116 #define I40E_IEEE_PFC_WILLING_SHIFT	7
117 #define I40E_IEEE_PFC_WILLING_MASK	BIT(I40E_IEEE_PFC_WILLING_SHIFT)
118 
119 /* Defines for IEEE APP TLV */
120 #define I40E_IEEE_APP_SEL_SHIFT		0
121 #define I40E_IEEE_APP_SEL_MASK		(0x7 << I40E_IEEE_APP_SEL_SHIFT)
122 #define I40E_IEEE_APP_PRIO_SHIFT	5
123 #define I40E_IEEE_APP_PRIO_MASK		(0x7 << I40E_IEEE_APP_PRIO_SHIFT)
124 
125 /* TLV definitions for preparing MIB */
126 #define I40E_TLV_ID_CHASSIS_ID		0
127 #define I40E_TLV_ID_PORT_ID		1
128 #define I40E_TLV_ID_TIME_TO_LIVE	2
129 #define I40E_IEEE_TLV_ID_ETS_CFG	3
130 #define I40E_IEEE_TLV_ID_ETS_REC	4
131 #define I40E_IEEE_TLV_ID_PFC_CFG	5
132 #define I40E_IEEE_TLV_ID_APP_PRI	6
133 #define I40E_TLV_ID_END_OF_LLDPPDU	7
134 #define I40E_TLV_ID_START		I40E_IEEE_TLV_ID_ETS_CFG
135 
136 #define I40E_IEEE_ETS_TLV_LENGTH	25
137 #define I40E_IEEE_PFC_TLV_LENGTH	6
138 #define I40E_IEEE_APP_TLV_LENGTH	11
139 
140 #pragma pack(1)
141 
142 /* IEEE 802.1AB LLDP TLV structure */
143 struct i40e_lldp_generic_tlv {
144 	__be16 typelength;
145 	u8 tlvinfo[1];
146 };
147 
148 /* IEEE 802.1AB LLDP Organization specific TLV */
149 struct i40e_lldp_org_tlv {
150 	__be16 typelength;
151 	__be32 ouisubtype;
152 	u8 tlvinfo[1];
153 };
154 
155 struct i40e_cee_tlv_hdr {
156 	__be16 typelen;
157 	u8 operver;
158 	u8 maxver;
159 };
160 
161 struct i40e_cee_ctrl_tlv {
162 	struct i40e_cee_tlv_hdr hdr;
163 	__be32 seqno;
164 	__be32 ackno;
165 };
166 
167 struct i40e_cee_feat_tlv {
168 	struct i40e_cee_tlv_hdr hdr;
169 	u8 en_will_err; /* Bits: |En|Will|Err|Reserved(5)| */
170 #define I40E_CEE_FEAT_TLV_ENABLE_MASK	0x80
171 #define I40E_CEE_FEAT_TLV_WILLING_MASK	0x40
172 #define I40E_CEE_FEAT_TLV_ERR_MASK	0x20
173 	u8 subtype;
174 	u8 tlvinfo[1];
175 };
176 
177 struct i40e_cee_app_prio {
178 	__be16 protocol;
179 	u8 upper_oui_sel; /* Bits: |Upper OUI(6)|Selector(2)| */
180 #define I40E_CEE_APP_SELECTOR_MASK	0x03
181 	__be16 lower_oui;
182 	u8 prio_map;
183 };
184 #pragma pack()
185 
186 /*
187  * TODO: The below structures related LLDP/DCBX variables
188  * and statistics are defined but need to find how to get
189  * the required information from the Firmware to use them
190  */
191 
192 /* IEEE 802.1AB LLDP Agent Statistics */
193 struct i40e_lldp_stats {
194 	u64 remtablelastchangetime;
195 	u64 remtableinserts;
196 	u64 remtabledeletes;
197 	u64 remtabledrops;
198 	u64 remtableageouts;
199 	u64 txframestotal;
200 	u64 rxframesdiscarded;
201 	u64 rxportframeerrors;
202 	u64 rxportframestotal;
203 	u64 rxporttlvsdiscardedtotal;
204 	u64 rxporttlvsunrecognizedtotal;
205 	u64 remtoomanyneighbors;
206 };
207 
208 /* IEEE 802.1Qaz DCBX variables */
209 struct i40e_dcbx_variables {
210 	u32 defmaxtrafficclasses;
211 	u32 defprioritytcmapping;
212 	u32 deftcbandwidth;
213 	u32 deftsaassignment;
214 };
215 
216 
217 enum i40e_get_fw_lldp_status_resp {
218 	I40E_GET_FW_LLDP_STATUS_DISABLED = 0,
219 	I40E_GET_FW_LLDP_STATUS_ENABLED = 1
220 };
221 
222 enum i40e_status_code i40e_get_dcbx_status(struct i40e_hw *hw,
223 					   u16 *status);
224 enum i40e_status_code i40e_lldp_to_dcb_config(u8 *lldpmib,
225 					      struct i40e_dcbx_config *dcbcfg);
226 enum i40e_status_code i40e_aq_get_dcb_config(struct i40e_hw *hw, u8 mib_type,
227 					     u8 bridgetype,
228 					     struct i40e_dcbx_config *dcbcfg);
229 enum i40e_status_code i40e_get_dcb_config(struct i40e_hw *hw);
230 enum i40e_status_code i40e_init_dcb(struct i40e_hw *hw,
231 				    bool enable_mib_change);
232 enum i40e_status_code
233 i40e_get_fw_lldp_status(struct i40e_hw *hw,
234 			enum i40e_get_fw_lldp_status_resp *lldp_status);
235 enum i40e_status_code i40e_set_dcb_config(struct i40e_hw *hw);
236 enum i40e_status_code i40e_dcb_config_to_lldp(u8 *lldpmib, u16 *miblen,
237 					      struct i40e_dcbx_config *dcbcfg);
238 #endif /* _I40E_DCB_H_ */
239