Searched defs:False (Results 1 - 25 of 28) sorted by relevance

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/freebsd-head/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DLazyValueInfo.h61 Unknown = -1, False = 0, True = 1 enumerator in enum:llvm::LazyValueInfo::Tristate
/freebsd-head/sbin/adjkerntz/
H A Dadjkerntz.c64 #define False (0) macro
92 int need_restore = False, sleep_mode = False, looping,
106 init = False;
149 looping = False;
153 init = False;
350 need_restore = False;
362 sleep_mode = False;
/freebsd-head/contrib/libarchive/libarchive/
H A Darchive_ppmd_private.h56 #define False 0 macro
/freebsd-head/contrib/llvm-project/clang/lib/AST/
H A DExprClassification.cpp582 const Expr *False) {
589 if (True->getType()->isVoidType() || False->getType()->isVoidType()) {
594 bool FalseIsThrow = isa<CXXThrowExpr>(False->IgnoreParenImpCasts());
595 if (const Expr *NonThrow = TrueIsThrow ? (FalseIsThrow ? nullptr : False)
609 RCl = ClassifyInternal(Ctx, False);
581 ClassifyConditional(ASTContext &Ctx, const Expr *True, const Expr *False) argument
/freebsd-head/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUPostLegalizerCombiner.cpp36 Register False; member in struct:FMinFMaxLegacyInfo
59 Info.False = MI.getOperand(3).getReg();
61 if (!(Info.LHS == Info.True && Info.RHS == Info.False) &&
62 !(Info.LHS == Info.False && Info.RHS == Info.True))
H A DR600ISelLowering.cpp954 SDValue False = Op.getOperand(3); local
960 SDValue MinMax = combineFMinMaxLegacy(DL, VT, LHS, RHS, True, False, CC, DCI);
979 // Move hardware True/False values to the correct operand.
980 if (isHWTrueValue(False) && isHWFalseValue(True)) {
984 std::swap(False, True);
989 std::swap(False, True);
996 if (isHWTrueValue(True) && isHWFalseValue(False) &&
999 return DAG.getNode(ISD::SELECT_CC, DL, VT, LHS, RHS, True, False, CC);
1025 std::swap(True, False);
1036 // Bitcast True / False t
1983 SDValue False = N->getOperand(3); local
[all...]
H A DAMDGPURegisterBankInfo.cpp139 auto False = B.buildConstant(S32, 0); local
140 B.buildSelect(DstReg, SrcReg, True, False);
142 MRI.setRegBank(False.getReg(0), *NewBank);
2583 auto False = B.buildConstant(SelType, 0); local
2586 MRI.setRegBank(False.getReg(0), *DstBank);
2590 B.buildSelect(DefRegs[0], SrcReg, True, False);
2593 auto Sel = B.buildSelect(SelType, SrcReg, True, False);
2597 B.buildSelect(DstReg, SrcReg, True, False);
H A DAMDGPUISelLowering.cpp1371 SDValue True, SDValue False,
1374 if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
3586 SDValue False = N->getOperand(2); local
3591 !DAG.isConstantValueOfAnyType(False)) {
3601 return DAG.getNode(ISD::SELECT, SL, VT, NewCond, False, True);
3606 = combineFMinMaxLegacy(SDLoc(N), VT, LHS, RHS, True, False, CC, DCI);
3614 return performCtlz_CttzCombine(SDLoc(N), Cond, True, False, DCI);
1369 combineFMinMaxLegacy(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, SDValue True, SDValue False, SDValue CC, DAGCombinerInfo &DCI) const argument
H A DSIISelLowering.cpp6006 SDValue False = DAG.getTargetConstant(0, DL, MVT::i1); local
6016 Unorm = UnormConst->getZExtValue() ? True : False;
6099 ST->hasFeature(AMDGPU::FeatureR128A16) ? True : False);
6101 Ops.push_back(IsA16 ? True : False);
6105 Ops.push_back(DimInfo->DA ? True : False);
6107 Ops.push_back(IsD16 ? True : False);
/freebsd-head/contrib/bmake/unit-tests/
H A Dvarmisc.mk16 False= ${echo false >&2:L:sh}FALSE macro
23 @echo ${VSET:U${False}}
27 @echo ${UNDEF:D${False}}
39 @echo ${1:L:?${True}:${False}}
43 @echo ${0:L:?${True}:${False}}
47 @echo ${VSET:U${1:L:?${True}:${False}}}
91 SD_VALUES= 0 1 2 False True false true Yes No yes no On Off ON OFF on off
/freebsd-head/contrib/bzip2/
H A Dbzip2recover.c57 #define False ((Bool)0) macro
264 if (n <= 4) return False;
H A Dbzip2.c170 #define False ((Bool)0) macro
323 return False;
535 return False;
617 return False;
623 return False;
629 return False;
988 if (MY_S_ISREG(statBuf.st_mode)) return False;
1089 return False;
1096 return False;
1114 if (ns < nx) return False;
[all...]
H A Dbzlib_private.h50 #define False ((Bool)0) macro
/freebsd-head/contrib/llvm-project/llvm/lib/Transforms/Coroutines/
H A DCoroElide.cpp137 auto *False = ConstantInt::getFalse(C); local
139 CA->replaceAllUsesWith(False);
/freebsd-head/contrib/one-true-awk/
H A Drun.c82 Cell *False = &falsecell; variable
586 return(False);
629 return(False);
648 else return(False);
650 if ( !i ) return(False);
655 else return(False);
657 if (i) return(False);
683 else return(False);
685 else return(False);
687 else return(False);
[all...]
/freebsd-head/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h1081 SDValue False, ISD::CondCode Cond) {
1083 False, getCondCode(Cond));
1080 getSelectCC(const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue True, SDValue False, ISD::CondCode Cond) argument
/freebsd-head/contrib/llvm-project/llvm/lib/IR/
H A DIRBuilder.cpp918 Value *IRBuilderBase::CreateSelect(Value *C, Value *True, Value *False, argument
922 if (auto *FC = dyn_cast<Constant>(False))
925 SelectInst *Sel = SelectInst::Create(C, True, False);
/freebsd-head/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp1063 SDValue False = getZero(dl, ResTy, DAG); local
1064 return DAG.getSelect(dl, ResTy, VecV, True, False);
/freebsd-head/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineCasts.cpp208 Value *False = EvaluateInDifferentType(I->getOperand(2), Ty, isSigned); local
209 Res = SelectInst::Create(I->getOperand(0), True, False);
H A DInstructionCombining.cpp790 Value *Cond, *True = nullptr, *False = nullptr; local
795 False = SimplifyBinOp(Opcode, C, F, FMF, Q);
798 if (False && !True)
800 else if (True && !False)
801 False = Builder.CreateBinOp(Opcode, C, F);
807 False = SimplifyBinOp(Opcode, C, RHS, FMF, Q);
812 False = SimplifyBinOp(Opcode, LHS, F, FMF, Q);
815 if (!True || !False)
818 Value *SI = Builder.CreateSelect(Cond, True, False);
2770 // Change br (not X), label True, label False t
[all...]
/freebsd-head/contrib/llvm-project/llvm/include/llvm/IR/
H A DIRBuilder.h958 BranchInst *CreateCondBr(Value *Cond, BasicBlock *True, BasicBlock *False, argument
961 return Insert(addBranchMetadata(BranchInst::Create(True, False, Cond),
967 BranchInst *CreateCondBr(Value *Cond, BasicBlock *True, BasicBlock *False, argument
969 BranchInst *Br = BranchInst::Create(True, False, Cond);
2372 Value *CreateSelect(Value *C, Value *True, Value *False,
/freebsd-head/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp667 SDValue False, const SDLoc &DL) {
673 True.getValueType(), True, FCC0, False, Cond);
688 SDValue False = N->getOperand(2);
689 EVT FalseTy = False.getValueType();
694 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(False);
696 // If the RHS (False) is 0, we swap the order of the operands
716 return DAG.getNode(ISD::SELECT, DL, FalseTy, SetCC, False, True);
739 return DAG.getNode(ISD::ADD, DL, SetCC.getValueType(), SetCC, False);
769 // Since RHS (False) is 0, we swap the order of the True/False operand
666 createCMovFP(SelectionDAG &DAG, SDValue Cond, SDValue True, SDValue False, const SDLoc &DL) argument
2074 SDValue False = DAG.getConstant(0, DL, MVT::i32); local
[all...]
/freebsd-head/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelDAGToDAG.cpp573 // If Dest BasicBlock is False-BasicBlock (FBB), swap branch probabilities,
5690 False = cast<ConstantSDNode>(FalseRes)->getZExtValue(); local
5691 if (!isInt<16>(True) || !isInt<16>(False))
/freebsd-head/contrib/llvm-project/clang/include/clang/Parse/
H A DParser.h2489 True, False, Ambiguous, Error member in class:clang::TPResult
2502 /// declaration specifier, TPResult::False if it is not,
2509 isCXXDeclarationSpecifier(TPResult BracedCastResult = TPResult::False,
2534 // Returning TPResult::True/False indicates that the ambiguity was
/freebsd-head/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DLegalizerHelper.cpp4499 auto False = MIRBuilder.buildFConstant(DstTy, 0.0); local
4500 MIRBuilder.buildSelect(Dst, Src, True, False);
4532 auto False = MIRBuilder.buildFConstant(DstTy, 0.0); local
4533 MIRBuilder.buildSelect(Dst, Src, True, False);

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