1 
2 /*
3  * CDDL HEADER START
4  *
5  * The contents of this file are subject to the terms of the
6  * Common Development and Distribution License (the "License").
7  * You may not use this file except in compliance with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  *
22  * Copyright 2014 QLogic Corporation
23  * The contents of this file are subject to the terms of the
24  * QLogic End User License (the "License").
25  * You may not use this file except in compliance with the License.
26  *
27  * You can obtain a copy of the License at
28  * http://www.qlogic.com/Resources/Documents/DriverDownloadHelp/
29  * QLogic_End_User_Software_License.txt
30  * See the License for the specific language governing permissions
31  * and limitations under the License.
32  *
33  * Generated On Date:  07/24/2009 20:59
34  *
35  */
36 
37 #ifndef EMAC_REG_H
38 #define EMAC_REG_H
39 
40 /*
41  *  emac_reg definition
42  *  offset: 0x1400
43  */
44 #define EMAC_REG_EMAC_MODE                                        0x0	//ACCESS:??  DataWidth:0x20
45         #define EMAC_MODE_RESET                            (1L<<0)
46         #define EMAC_MODE_RESET_BITSHIFT                   0
47         #define EMAC_MODE_HALF_DUPLEX                      (1L<<1)
48         #define EMAC_MODE_HALF_DUPLEX_BITSHIFT             1
49         #define EMAC_MODE_PORT                             (0x3L<<2)
50         #define EMAC_MODE_PORT_BITSHIFT                    2
51             #define EMAC_MODE_PORT_NONE                    (0L<<2)
52             #define EMAC_MODE_PORT_NONE_BITSHIFT           2
53             #define EMAC_MODE_PORT_MII                     (1L<<2)
54             #define EMAC_MODE_PORT_MII_BITSHIFT            2
55             #define EMAC_MODE_PORT_GMII                    (2L<<2)
56             #define EMAC_MODE_PORT_GMII_BITSHIFT           2
57             #define EMAC_MODE_PORT_MII_10M                 (3L<<2)
58             #define EMAC_MODE_PORT_MII_10M_BITSHIFT        2
59         #define EMAC_MODE_MAC_LOOP                         (1L<<4)
60         #define EMAC_MODE_MAC_LOOP_BITSHIFT                4
61         #define EMAC_MODE_25G_MODE                         (1L<<5)
62         #define EMAC_MODE_25G_MODE_BITSHIFT                5
63         #define EMAC_MODE_TAGGED_MAC_CTL                   (1L<<7)
64         #define EMAC_MODE_TAGGED_MAC_CTL_BITSHIFT          7
65         #define EMAC_MODE_TX_BURST                         (1L<<8)
66         #define EMAC_MODE_TX_BURST_BITSHIFT                8
67         #define EMAC_MODE_MAX_DEFER_DROP_ENA               (1L<<9)
68         #define EMAC_MODE_MAX_DEFER_DROP_ENA_BITSHIFT      9
69         #define EMAC_MODE_EXT_LINK_POL                     (1L<<10)
70         #define EMAC_MODE_EXT_LINK_POL_BITSHIFT            10
71         #define EMAC_MODE_FORCE_LINK                       (1L<<11)
72         #define EMAC_MODE_FORCE_LINK_BITSHIFT              11
73         #define EMAC_MODE_MPKT                             (1L<<18)
74         #define EMAC_MODE_MPKT_BITSHIFT                    18
75         #define EMAC_MODE_MPKT_RCVD                        (1L<<19)
76         #define EMAC_MODE_MPKT_RCVD_BITSHIFT               19
77         #define EMAC_MODE_ACPI_RCVD                        (1L<<20)
78         #define EMAC_MODE_ACPI_RCVD_BITSHIFT               20
79 #define EMAC_REG_EMAC_STATUS                                      0x4	//ACCESS:??  DataWidth:0x20
80         #define EMAC_STATUS_LINK                           (1L<<11)
81         #define EMAC_STATUS_LINK_BITSHIFT                  11
82         #define EMAC_STATUS_LINK_CHANGE                    (1L<<12)
83         #define EMAC_STATUS_LINK_CHANGE_BITSHIFT           12
84         #define EMAC_STATUS_SERDES_AUTONEG_COMPLETE        (1L<<13)
85         #define EMAC_STATUS_SERDES_AUTONEG_COMPLETE_BITSHIFT 13
86         #define EMAC_STATUS_SERDES_AUTONEG_CHANGE          (1L<<14)
87         #define EMAC_STATUS_SERDES_AUTONEG_CHANGE_BITSHIFT 14
88         #define EMAC_STATUS_SERDES_NXT_PG_CHANGE           (1L<<16)
89         #define EMAC_STATUS_SERDES_NXT_PG_CHANGE_BITSHIFT  16
90         #define EMAC_STATUS_SERDES_RX_CONFIG_IS_0          (1L<<17)
91         #define EMAC_STATUS_SERDES_RX_CONFIG_IS_0_BITSHIFT 17
92         #define EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE   (1L<<18)
93         #define EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE_BITSHIFT 18
94         #define EMAC_STATUS_MI_COMPLETE                    (1L<<22)
95         #define EMAC_STATUS_MI_COMPLETE_BITSHIFT           22
96         #define EMAC_STATUS_MI_INT                         (1L<<23)
97         #define EMAC_STATUS_MI_INT_BITSHIFT                23
98         #define EMAC_STATUS_AP_ERROR                       (1L<<24)
99         #define EMAC_STATUS_AP_ERROR_BITSHIFT              24
100         #define EMAC_STATUS_PARITY_ERROR_STATE             (1L<<31)
101         #define EMAC_STATUS_PARITY_ERROR_STATE_BITSHIFT    31
102 #define EMAC_REG_EMAC_ATTENTION_ENA                               0x8	//ACCESS:??  DataWidth:0x20
103         #define EMAC_ATTENTION_ENA_LINK                    (1L<<11)
104         #define EMAC_ATTENTION_ENA_LINK_BITSHIFT           11
105         #define EMAC_ATTENTION_ENA_AUTONEG_CHANGE          (1L<<14)
106         #define EMAC_ATTENTION_ENA_AUTONEG_CHANGE_BITSHIFT 14
107         #define EMAC_ATTENTION_ENA_NXT_PG_CHANGE           (1L<<16)
108         #define EMAC_ATTENTION_ENA_NXT_PG_CHANGE_BITSHIFT  16
109         #define EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE  (1L<<18)
110         #define EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE_BITSHIFT 18
111         #define EMAC_ATTENTION_ENA_MI_COMPLETE             (1L<<22)
112         #define EMAC_ATTENTION_ENA_MI_COMPLETE_BITSHIFT    22
113         #define EMAC_ATTENTION_ENA_MI_INT                  (1L<<23)
114         #define EMAC_ATTENTION_ENA_MI_INT_BITSHIFT         23
115         #define EMAC_ATTENTION_ENA_AP_ERROR                (1L<<24)
116         #define EMAC_ATTENTION_ENA_AP_ERROR_BITSHIFT       24
117 #define EMAC_REG_EMAC_LED                                         0xc	//ACCESS:??  DataWidth:0x20
118         #define EMAC_LED_OVERRIDE                          (1L<<0)
119         #define EMAC_LED_OVERRIDE_BITSHIFT                 0
120         #define EMAC_LED_1000MB_OVERRIDE                   (1L<<1)
121         #define EMAC_LED_1000MB_OVERRIDE_BITSHIFT          1
122         #define EMAC_LED_100MB_OVERRIDE                    (1L<<2)
123         #define EMAC_LED_100MB_OVERRIDE_BITSHIFT           2
124         #define EMAC_LED_10MB_OVERRIDE                     (1L<<3)
125         #define EMAC_LED_10MB_OVERRIDE_BITSHIFT            3
126         #define EMAC_LED_TRAFFIC_OVERRIDE                  (1L<<4)
127         #define EMAC_LED_TRAFFIC_OVERRIDE_BITSHIFT         4
128         #define EMAC_LED_BLNK_TRAFFIC                      (1L<<5)
129         #define EMAC_LED_BLNK_TRAFFIC_BITSHIFT             5
130         #define EMAC_LED_TRAFFIC                           (1L<<6)
131         #define EMAC_LED_TRAFFIC_BITSHIFT                  6
132         #define EMAC_LED_1000MB                            (1L<<7)
133         #define EMAC_LED_1000MB_BITSHIFT                   7
134         #define EMAC_LED_100MB                             (1L<<8)
135         #define EMAC_LED_100MB_BITSHIFT                    8
136         #define EMAC_LED_10MB                              (1L<<9)
137         #define EMAC_LED_10MB_BITSHIFT                     9
138         #define EMAC_LED_TRAFFIC_STAT                      (1L<<10)
139         #define EMAC_LED_TRAFFIC_STAT_BITSHIFT             10
140         #define EMAC_LED_2500MB                            (1L<<11)
141         #define EMAC_LED_2500MB_BITSHIFT                   11
142         #define EMAC_LED_2500MB_OVERRIDE                   (1L<<12)
143         #define EMAC_LED_2500MB_OVERRIDE_BITSHIFT          12
144         #define EMAC_LED_ACTIVITY_SEL                      (0x3L<<17)
145         #define EMAC_LED_ACTIVITY_SEL_BITSHIFT             17
146             #define EMAC_LED_ACTIVITY_SEL_0                (0L<<17)
147             #define EMAC_LED_ACTIVITY_SEL_0_BITSHIFT       17
148             #define EMAC_LED_ACTIVITY_SEL_1                (1L<<17)
149             #define EMAC_LED_ACTIVITY_SEL_1_BITSHIFT       17
150             #define EMAC_LED_ACTIVITY_SEL_2                (2L<<17)
151             #define EMAC_LED_ACTIVITY_SEL_2_BITSHIFT       17
152             #define EMAC_LED_ACTIVITY_SEL_3                (3L<<17)
153             #define EMAC_LED_ACTIVITY_SEL_3_BITSHIFT       17
154         #define EMAC_LED_BLNK_RATE                         (0xfffL<<19)
155         #define EMAC_LED_BLNK_RATE_BITSHIFT                19
156         #define EMAC_LED_BLNK_RATE_ENA                     (1L<<31)
157         #define EMAC_LED_BLNK_RATE_ENA_BITSHIFT            31
158 #define EMAC_REG_EMAC_MAC_MATCH                                   0x10	//ACCESS:??  DataWidth:0x20
159 #define EMAC_REG_EMAC_MAC_MATCH_COUNT                             32
160 #define EMAC_REG_EMAC_LED2                                        0x90	//ACCESS:??  DataWidth:0x20
161         #define EMAC_LED2_PHY_10MB_SOFT                    (1L<<0)
162         #define EMAC_LED2_PHY_10MB_SOFT_BITSHIFT           0
163         #define EMAC_LED2_PHY_10MB_MSK                     (0x7L<<1)
164         #define EMAC_LED2_PHY_10MB_MSK_BITSHIFT            1
165         #define EMAC_LED2_PHY_10MB_CMP                     (0x7L<<4)
166         #define EMAC_LED2_PHY_10MB_CMP_BITSHIFT            4
167         #define EMAC_LED2_PHY_100MB_SOFT                   (1L<<8)
168         #define EMAC_LED2_PHY_100MB_SOFT_BITSHIFT          8
169         #define EMAC_LED2_PHY_100MB_MSK                    (0x7L<<9)
170         #define EMAC_LED2_PHY_100MB_MSK_BITSHIFT           9
171         #define EMAC_LED2_PHY_100MB_CMP                    (0x7L<<12)
172         #define EMAC_LED2_PHY_100MB_CMP_BITSHIFT           12
173         #define EMAC_LED2_PHY_1GB_SOFT                     (1L<<16)
174         #define EMAC_LED2_PHY_1GB_SOFT_BITSHIFT            16
175         #define EMAC_LED2_PHY_1GB_MSK                      (0x7L<<17)
176         #define EMAC_LED2_PHY_1GB_MSK_BITSHIFT             17
177         #define EMAC_LED2_PHY_1GB_CMP                      (0x7L<<20)
178         #define EMAC_LED2_PHY_1GB_CMP_BITSHIFT             20
179         #define EMAC_LED2_PHY_10GB_SOFT                    (1L<<24)
180         #define EMAC_LED2_PHY_10GB_SOFT_BITSHIFT           24
181         #define EMAC_LED2_PHY_10GB_MSK                     (0x7L<<25)
182         #define EMAC_LED2_PHY_10GB_MSK_BITSHIFT            25
183         #define EMAC_LED2_PHY_10GB_CMP                     (0x7L<<28)
184         #define EMAC_LED2_PHY_10GB_CMP_BITSHIFT            28
185 #define EMAC_REG_EMAC_LED3                                        0x94	//ACCESS:??  DataWidth:0x20
186         #define EMAC_LED3_PHY_ACT_MSK                      (0x3L<<0)
187         #define EMAC_LED3_PHY_ACT_MSK_BITSHIFT             0
188         #define EMAC_LED3_PHY_ACT_CMP                      (0x3L<<2)
189         #define EMAC_LED3_PHY_ACT_CMP_BITSHIFT             2
190         #define EMAC_LED3_PHY_QUAL_MSK                     (0x3L<<4)
191         #define EMAC_LED3_PHY_QUAL_MSK_BITSHIFT            4
192         #define EMAC_LED3_PHY_QUAL_CMP                     (0x3L<<6)
193         #define EMAC_LED3_PHY_QUAL_CMP_BITSHIFT            6
194         #define EMAC_LED3_PHY_QUAL_SOFT                    (1L<<8)
195         #define EMAC_LED3_PHY_QUAL_SOFT_BITSHIFT           8
196 #define EMAC_REG_EMAC_BACKOFF_SEED                                0x98	//ACCESS:??  DataWidth:0x20
197         #define EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED        (0x3ffL<<0)
198         #define EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED_BITSHIFT 0
199 #define EMAC_REG_EMAC_RX_MTU_SIZE                                 0x9c	//ACCESS:??  DataWidth:0x20
200         #define EMAC_RX_MTU_SIZE_MTU_SIZE                  (0xffffL<<0)
201         #define EMAC_RX_MTU_SIZE_MTU_SIZE_BITSHIFT         0
202         #define EMAC_RX_MTU_SIZE_JUMBO_ENA                 (1L<<31)
203         #define EMAC_RX_MTU_SIZE_JUMBO_ENA_BITSHIFT        31
204 #define EMAC_REG_EMAC_UNUSED2                                     0xa0	//ACCESS:??  DataWidth:0x20
205 #define EMAC_REG_EMAC_UNUSED2_COUNT                               2
206 #define EMAC_REG_EMAC_MDIO_AUTO_POLL                              0xa8	//ACCESS:??  DataWidth:0x20
207         #define EMAC_MDIO_AUTO_POLL_DATA_MASK              (0xffffL<<0)
208         #define EMAC_MDIO_AUTO_POLL_DATA_MASK_BITSHIFT     0
209         #define EMAC_MDIO_AUTO_POLL_REG_ADDR               (0xffffL<<16)
210         #define EMAC_MDIO_AUTO_POLL_REG_ADDR_BITSHIFT      16
211 #define EMAC_REG_EMAC_MDIO_COMM                                   0xac	//ACCESS:??  DataWidth:0x20
212         #define EMAC_MDIO_COMM_DATA                        (0xffffL<<0)
213         #define EMAC_MDIO_COMM_DATA_BITSHIFT               0
214         #define EMAC_MDIO_COMM_REG_ADDR                    (0x1fL<<16)
215         #define EMAC_MDIO_COMM_REG_ADDR_BITSHIFT           16
216         #define EMAC_MDIO_COMM_PHY_ADDR                    (0x1fL<<21)
217         #define EMAC_MDIO_COMM_PHY_ADDR_BITSHIFT           21
218         #define EMAC_MDIO_COMM_COMMAND                     (0x3L<<26)
219         #define EMAC_MDIO_COMM_COMMAND_BITSHIFT            26
220             #define EMAC_MDIO_COMM_COMMAND_UNDEFINED_0     (0L<<26)
221             #define EMAC_MDIO_COMM_COMMAND_UNDEFINED_0_BITSHIFT 26
222             #define EMAC_MDIO_COMM_COMMAND_ADDRESS         (0L<<26)
223             #define EMAC_MDIO_COMM_COMMAND_ADDRESS_BITSHIFT 26
224             #define EMAC_MDIO_COMM_COMMAND_WRITE_22        (1L<<26)
225             #define EMAC_MDIO_COMM_COMMAND_WRITE_22_BITSHIFT 26
226             #define EMAC_MDIO_COMM_COMMAND_WRITE_45        (1L<<26)
227             #define EMAC_MDIO_COMM_COMMAND_WRITE_45_BITSHIFT 26
228             #define EMAC_MDIO_COMM_COMMAND_READ_22         (2L<<26)
229             #define EMAC_MDIO_COMM_COMMAND_READ_22_BITSHIFT 26
230             #define EMAC_MDIO_COMM_COMMAND_READ_INC_45     (2L<<26)
231             #define EMAC_MDIO_COMM_COMMAND_READ_INC_45_BITSHIFT 26
232             #define EMAC_MDIO_COMM_COMMAND_UNDEFINED_3     (3L<<26)
233             #define EMAC_MDIO_COMM_COMMAND_UNDEFINED_3_BITSHIFT 26
234             #define EMAC_MDIO_COMM_COMMAND_READ_45         (3L<<26)
235             #define EMAC_MDIO_COMM_COMMAND_READ_45_BITSHIFT 26
236         #define EMAC_MDIO_COMM_FAIL                        (1L<<28)
237         #define EMAC_MDIO_COMM_FAIL_BITSHIFT               28
238         #define EMAC_MDIO_COMM_START_BUSY                  (1L<<29)
239         #define EMAC_MDIO_COMM_START_BUSY_BITSHIFT         29
240 #define EMAC_REG_EMAC_MDIO_STATUS                                 0xb0	//ACCESS:??  DataWidth:0x20
241         #define EMAC_MDIO_STATUS_LINK                      (1L<<0)
242         #define EMAC_MDIO_STATUS_LINK_BITSHIFT             0
243         #define EMAC_MDIO_STATUS_10MB                      (1L<<1)
244         #define EMAC_MDIO_STATUS_10MB_BITSHIFT             1
245 #define EMAC_REG_EMAC_MDIO_MODE                                   0xb4	//ACCESS:??  DataWidth:0x20
246         #define EMAC_MDIO_MODE_SHORT_PREAMBLE              (1L<<1)
247         #define EMAC_MDIO_MODE_SHORT_PREAMBLE_BITSHIFT     1
248         #define EMAC_MDIO_MODE_AUTO_POLL                   (1L<<4)
249         #define EMAC_MDIO_MODE_AUTO_POLL_BITSHIFT          4
250         #define EMAC_MDIO_MODE_BIT_BANG                    (1L<<8)
251         #define EMAC_MDIO_MODE_BIT_BANG_BITSHIFT           8
252         #define EMAC_MDIO_MODE_MDIO                        (1L<<9)
253         #define EMAC_MDIO_MODE_MDIO_BITSHIFT               9
254         #define EMAC_MDIO_MODE_MDIO_OE                     (1L<<10)
255         #define EMAC_MDIO_MODE_MDIO_OE_BITSHIFT            10
256         #define EMAC_MDIO_MODE_MDC                         (1L<<11)
257         #define EMAC_MDIO_MODE_MDC_BITSHIFT                11
258         #define EMAC_MDIO_MODE_MDINT                       (1L<<12)
259         #define EMAC_MDIO_MODE_MDINT_BITSHIFT              12
260         #define EMAC_MDIO_MODE_EXT_MDINT                   (1L<<13)
261         #define EMAC_MDIO_MODE_EXT_MDINT_BITSHIFT          13
262         #define EMAC_MDIO_MODE_CLOCK_CNT                   (0x3ffL<<16)
263         #define EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT          16
264         #define EMAC_MDIO_MODE_CLAUSE_45                   (1L<<31)
265         #define EMAC_MDIO_MODE_CLAUSE_45_BITSHIFT          31
266 #define EMAC_REG_EMAC_MDIO_AUTO_STATUS                            0xb8	//ACCESS:??  DataWidth:0x20
267         #define EMAC_MDIO_AUTO_STATUS_AUTO_ERR             (1L<<0)
268         #define EMAC_MDIO_AUTO_STATUS_AUTO_ERR_BITSHIFT    0
269 #define EMAC_REG_EMAC_TX_MODE                                     0xbc	//ACCESS:??  DataWidth:0x20
270         #define EMAC_TX_MODE_RESET                         (1L<<0)
271         #define EMAC_TX_MODE_RESET_BITSHIFT                0
272         #define EMAC_TX_MODE_CS16_TEST                     (1L<<2)
273         #define EMAC_TX_MODE_CS16_TEST_BITSHIFT            2
274         #define EMAC_TX_MODE_EXT_PAUSE_EN                  (1L<<3)
275         #define EMAC_TX_MODE_EXT_PAUSE_EN_BITSHIFT         3
276         #define EMAC_TX_MODE_FLOW_EN                       (1L<<4)
277         #define EMAC_TX_MODE_FLOW_EN_BITSHIFT              4
278         #define EMAC_TX_MODE_BIG_BACKOFF                   (1L<<5)
279         #define EMAC_TX_MODE_BIG_BACKOFF_BITSHIFT          5
280         #define EMAC_TX_MODE_LONG_PAUSE                    (1L<<6)
281         #define EMAC_TX_MODE_LONG_PAUSE_BITSHIFT           6
282         #define EMAC_TX_MODE_LINK_AWARE                    (1L<<7)
283         #define EMAC_TX_MODE_LINK_AWARE_BITSHIFT           7
284 #define EMAC_REG_EMAC_TX_STATUS                                   0xc0	//ACCESS:??  DataWidth:0x20
285         #define EMAC_TX_STATUS_XOFFED                      (1L<<0)
286         #define EMAC_TX_STATUS_XOFFED_BITSHIFT             0
287         #define EMAC_TX_STATUS_XOFF_SENT                   (1L<<1)
288         #define EMAC_TX_STATUS_XOFF_SENT_BITSHIFT          1
289         #define EMAC_TX_STATUS_XON_SENT                    (1L<<2)
290         #define EMAC_TX_STATUS_XON_SENT_BITSHIFT           2
291         #define EMAC_TX_STATUS_LINK_UP                     (1L<<3)
292         #define EMAC_TX_STATUS_LINK_UP_BITSHIFT            3
293         #define EMAC_TX_STATUS_UNDERRUN                    (1L<<4)
294         #define EMAC_TX_STATUS_UNDERRUN_BITSHIFT           4
295         #define EMAC_TX_STATUS_CS16_ERROR                  (1L<<5)
296         #define EMAC_TX_STATUS_CS16_ERROR_BITSHIFT         5
297 #define EMAC_REG_EMAC_TX_LENGTHS                                  0xc4	//ACCESS:??  DataWidth:0x20
298         #define EMAC_TX_LENGTHS_SLOT                       (0xffL<<0)
299         #define EMAC_TX_LENGTHS_SLOT_BITSHIFT              0
300         #define EMAC_TX_LENGTHS_IPG                        (0xfL<<8)
301         #define EMAC_TX_LENGTHS_IPG_BITSHIFT               8
302         #define EMAC_TX_LENGTHS_IPG_CRS                    (0x3L<<12)
303         #define EMAC_TX_LENGTHS_IPG_CRS_BITSHIFT           12
304 #define EMAC_REG_EMAC_RX_MODE                                     0xc8	//ACCESS:??  DataWidth:0x20
305         #define EMAC_RX_MODE_RESET                         (1L<<0)
306         #define EMAC_RX_MODE_RESET_BITSHIFT                0
307         #define EMAC_RX_MODE_FLOW_EN                       (1L<<2)
308         #define EMAC_RX_MODE_FLOW_EN_BITSHIFT              2
309         #define EMAC_RX_MODE_KEEP_MAC_CONTROL              (1L<<3)
310         #define EMAC_RX_MODE_KEEP_MAC_CONTROL_BITSHIFT     3
311         #define EMAC_RX_MODE_KEEP_PAUSE                    (1L<<4)
312         #define EMAC_RX_MODE_KEEP_PAUSE_BITSHIFT           4
313         #define EMAC_RX_MODE_ACCEPT_OVERSIZE               (1L<<5)
314         #define EMAC_RX_MODE_ACCEPT_OVERSIZE_BITSHIFT      5
315         #define EMAC_RX_MODE_ACCEPT_RUNTS                  (1L<<6)
316         #define EMAC_RX_MODE_ACCEPT_RUNTS_BITSHIFT         6
317         #define EMAC_RX_MODE_LLC_CHK                       (1L<<7)
318         #define EMAC_RX_MODE_LLC_CHK_BITSHIFT              7
319         #define EMAC_RX_MODE_PROMISCUOUS                   (1L<<8)
320         #define EMAC_RX_MODE_PROMISCUOUS_BITSHIFT          8
321         #define EMAC_RX_MODE_NO_CRC_CHK                    (1L<<9)
322         #define EMAC_RX_MODE_NO_CRC_CHK_BITSHIFT           9
323         #define EMAC_RX_MODE_KEEP_VLAN_TAG                 (1L<<10)
324         #define EMAC_RX_MODE_KEEP_VLAN_TAG_BITSHIFT        10
325         #define EMAC_RX_MODE_FILT_BROADCAST                (1L<<11)
326         #define EMAC_RX_MODE_FILT_BROADCAST_BITSHIFT       11
327         #define EMAC_RX_MODE_SORT_MODE                     (1L<<12)
328         #define EMAC_RX_MODE_SORT_MODE_BITSHIFT            12
329 #define EMAC_REG_EMAC_RX_STATUS                                   0xcc	//ACCESS:??  DataWidth:0x20
330         #define EMAC_RX_STATUS_FFED                        (1L<<0)
331         #define EMAC_RX_STATUS_FFED_BITSHIFT               0
332         #define EMAC_RX_STATUS_FF_RECEIVED                 (1L<<1)
333         #define EMAC_RX_STATUS_FF_RECEIVED_BITSHIFT        1
334         #define EMAC_RX_STATUS_N_RECEIVED                  (1L<<2)
335         #define EMAC_RX_STATUS_N_RECEIVED_BITSHIFT         2
336 #define EMAC_REG_EMAC_MULTICAST_HASH                              0xd0	//ACCESS:??  DataWidth:0x20
337 #define EMAC_REG_EMAC_MULTICAST_HASH_COUNT                        8
338 #define EMAC_REG_EMAC_CKSUM_ERROR_STATUS                          0xf0	//ACCESS:??  DataWidth:0x20
339         #define EMAC_CKSUM_ERROR_STATUS_CALCULATED         (0xffffL<<0)
340         #define EMAC_CKSUM_ERROR_STATUS_CALCULATED_BITSHIFT 0
341         #define EMAC_CKSUM_ERROR_STATUS_EXPECTED           (0xffffL<<16)
342         #define EMAC_CKSUM_ERROR_STATUS_EXPECTED_BITSHIFT  16
343 #define EMAC_REG_EMAC_EEE_MODE                                    0xf4	//ACCESS:??  DataWidth:0x20
344         #define EMAC_EEE_MODE_RX_LPI_ENA                   (1L<<0)
345         #define EMAC_EEE_MODE_RX_LPI_ENA_BITSHIFT          0
346         #define EMAC_EEE_MODE_TX_LPI_ENA                   (1L<<1)
347         #define EMAC_EEE_MODE_TX_LPI_ENA_BITSHIFT          1
348         #define EMAC_EEE_MODE_AUTO_WAKE_ENA                (1L<<2)
349         #define EMAC_EEE_MODE_AUTO_WAKE_ENA_BITSHIFT       2
350         #define EMAC_EEE_MODE_BLOCK_TIME                   (0xffL<<24)
351         #define EMAC_EEE_MODE_BLOCK_TIME_BITSHIFT          24
352 #define EMAC_REG_EMAC_EEE_TIMER                                   0xf8	//ACCESS:??  DataWidth:0x20
353         #define EMAC_EEE_TIMER_EXIT_TIME                   (0xffffL<<0)
354         #define EMAC_EEE_TIMER_EXIT_TIME_BITSHIFT          0
355         #define EMAC_EEE_TIMER_MIN_ASSERT                  (0xffffL<<16)
356         #define EMAC_EEE_TIMER_MIN_ASSERT_BITSHIFT         16
357 #define EMAC_REG_EMAC_EEE_DEBUG                                   0xfc	//ACCESS:??  DataWidth:0x20
358 #define EMAC_REG_EMAC_RX_STAT_IFHCINOCTETS                        0x100	//ACCESS:??  DataWidth:0x20
359 #define EMAC_REG_EMAC_RX_STAT_IFHCINBADOCTETS                     0x104	//ACCESS:??  DataWidth:0x20
360 #define EMAC_REG_EMAC_RX_STAT_ETHERSTATSFRAGMENTS                 0x108	//ACCESS:??  DataWidth:0x20
361 #define EMAC_REG_EMAC_RX_STAT_IFHCINUCASTPKTS                     0x10c	//ACCESS:??  DataWidth:0x20
362 #define EMAC_REG_EMAC_RX_STAT_IFHCINMULTICASTPKTS                 0x110	//ACCESS:??  DataWidth:0x20
363 #define EMAC_REG_EMAC_RX_STAT_IFHCINBROADCASTPKTS                 0x114	//ACCESS:??  DataWidth:0x20
364 #define EMAC_REG_EMAC_RX_STAT_DOT3STATSFCSERRORS                  0x118	//ACCESS:??  DataWidth:0x20
365 #define EMAC_REG_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS            0x11c	//ACCESS:??  DataWidth:0x20
366 #define EMAC_REG_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS         0x120	//ACCESS:??  DataWidth:0x20
367 #define EMAC_REG_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED              0x124	//ACCESS:??  DataWidth:0x20
368 #define EMAC_REG_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED             0x128	//ACCESS:??  DataWidth:0x20
369 #define EMAC_REG_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED            0x12c	//ACCESS:??  DataWidth:0x20
370 #define EMAC_REG_EMAC_RX_STAT_XOFFSTATEENTERED                    0x130	//ACCESS:??  DataWidth:0x20
371 #define EMAC_REG_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG              0x134	//ACCESS:??  DataWidth:0x20
372 #define EMAC_REG_EMAC_RX_STAT_ETHERSTATSJABBERS                   0x138	//ACCESS:??  DataWidth:0x20
373 #define EMAC_REG_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS             0x13c	//ACCESS:??  DataWidth:0x20
374 #define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS              0x140	//ACCESS:??  DataWidth:0x20
375 #define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS   0x144	//ACCESS:??  DataWidth:0x20
376 #define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS  0x148	//ACCESS:??  DataWidth:0x20
377 #define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS  0x14c	//ACCESS:??  DataWidth:0x20
378 #define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x150	//ACCESS:??  DataWidth:0x20
379 #define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS0x154	//ACCESS:??  DataWidth:0x20
380 #define EMAC_REG_EMAC_RX_STAT_ETHERSTATSPKTSOVER1522OCTETS        0x158	//ACCESS:??  DataWidth:0x20
381 #define EMAC_REG_EMAC_RXMAC_DEBUG0                                0x15c	//ACCESS:??  DataWidth:0x20
382 #define EMAC_REG_EMAC_RXMAC_DEBUG1                                0x160	//ACCESS:??  DataWidth:0x20
383         #define EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT     (1L<<0)
384         #define EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT_BITSHIFT 0
385         #define EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE         (1L<<1)
386         #define EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE_BITSHIFT 1
387         #define EMAC_RXMAC_DEBUG1_BAD_CRC                  (1L<<2)
388         #define EMAC_RXMAC_DEBUG1_BAD_CRC_BITSHIFT         2
389         #define EMAC_RXMAC_DEBUG1_RX_ERROR                 (1L<<3)
390         #define EMAC_RXMAC_DEBUG1_RX_ERROR_BITSHIFT        3
391         #define EMAC_RXMAC_DEBUG1_ALIGN_ERROR              (1L<<4)
392         #define EMAC_RXMAC_DEBUG1_ALIGN_ERROR_BITSHIFT     4
393         #define EMAC_RXMAC_DEBUG1_LAST_DATA                (1L<<5)
394         #define EMAC_RXMAC_DEBUG1_LAST_DATA_BITSHIFT       5
395         #define EMAC_RXMAC_DEBUG1_ODD_BYTE_START           (1L<<6)
396         #define EMAC_RXMAC_DEBUG1_ODD_BYTE_START_BITSHIFT  6
397         #define EMAC_RXMAC_DEBUG1_BYTE_COUNT               (0xffffL<<7)
398         #define EMAC_RXMAC_DEBUG1_BYTE_COUNT_BITSHIFT      7
399         #define EMAC_RXMAC_DEBUG1_SLOT_TIME                (0xffL<<23)
400         #define EMAC_RXMAC_DEBUG1_SLOT_TIME_BITSHIFT       23
401 #define EMAC_REG_EMAC_RXMAC_DEBUG2                                0x164	//ACCESS:??  DataWidth:0x20
402         #define EMAC_RXMAC_DEBUG2_SM_STATE                 (0x7L<<0)
403         #define EMAC_RXMAC_DEBUG2_SM_STATE_BITSHIFT        0
404             #define EMAC_RXMAC_DEBUG2_SM_STATE_IDLE        (0L<<0)
405             #define EMAC_RXMAC_DEBUG2_SM_STATE_IDLE_BITSHIFT 0
406             #define EMAC_RXMAC_DEBUG2_SM_STATE_SFD         (1L<<0)
407             #define EMAC_RXMAC_DEBUG2_SM_STATE_SFD_BITSHIFT 0
408             #define EMAC_RXMAC_DEBUG2_SM_STATE_DATA        (2L<<0)
409             #define EMAC_RXMAC_DEBUG2_SM_STATE_DATA_BITSHIFT 0
410             #define EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP       (3L<<0)
411             #define EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP_BITSHIFT 0
412             #define EMAC_RXMAC_DEBUG2_SM_STATE_EXT         (4L<<0)
413             #define EMAC_RXMAC_DEBUG2_SM_STATE_EXT_BITSHIFT 0
414             #define EMAC_RXMAC_DEBUG2_SM_STATE_DROP        (5L<<0)
415             #define EMAC_RXMAC_DEBUG2_SM_STATE_DROP_BITSHIFT 0
416             #define EMAC_RXMAC_DEBUG2_SM_STATE_SDROP       (6L<<0)
417             #define EMAC_RXMAC_DEBUG2_SM_STATE_SDROP_BITSHIFT 0
418             #define EMAC_RXMAC_DEBUG2_SM_STATE_FC          (7L<<0)
419             #define EMAC_RXMAC_DEBUG2_SM_STATE_FC_BITSHIFT 0
420         #define EMAC_RXMAC_DEBUG2_IDI_STATE                (0xfL<<3)
421         #define EMAC_RXMAC_DEBUG2_IDI_STATE_BITSHIFT       3
422             #define EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE       (0L<<3)
423             #define EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE_BITSHIFT 3
424             #define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0      (1L<<3)
425             #define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0_BITSHIFT 3
426             #define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1      (2L<<3)
427             #define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1_BITSHIFT 3
428             #define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2      (3L<<3)
429             #define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2_BITSHIFT 3
430             #define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3      (4L<<3)
431             #define EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3_BITSHIFT 3
432             #define EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT      (5L<<3)
433             #define EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT_BITSHIFT 3
434             #define EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT       (6L<<3)
435             #define EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT_BITSHIFT 3
436             #define EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS     (7L<<3)
437             #define EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS_BITSHIFT 3
438             #define EMAC_RXMAC_DEBUG2_IDI_STATE_LAST       (8L<<3)
439             #define EMAC_RXMAC_DEBUG2_IDI_STATE_LAST_BITSHIFT 3
440         #define EMAC_RXMAC_DEBUG2_BYTE_IN                  (0xffL<<7)
441         #define EMAC_RXMAC_DEBUG2_BYTE_IN_BITSHIFT         7
442         #define EMAC_RXMAC_DEBUG2_FALSEC                   (1L<<15)
443         #define EMAC_RXMAC_DEBUG2_FALSEC_BITSHIFT          15
444         #define EMAC_RXMAC_DEBUG2_TAGGED                   (1L<<16)
445         #define EMAC_RXMAC_DEBUG2_TAGGED_BITSHIFT          16
446         #define EMAC_RXMAC_DEBUG2_PAUSE_STATE              (1L<<18)
447         #define EMAC_RXMAC_DEBUG2_PAUSE_STATE_BITSHIFT     18
448             #define EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE     (0L<<18)
449             #define EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE_BITSHIFT 18
450             #define EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED   (1L<<18)
451             #define EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED_BITSHIFT 18
452         #define EMAC_RXMAC_DEBUG2_SE_COUNTER               (0xfL<<19)
453         #define EMAC_RXMAC_DEBUG2_SE_COUNTER_BITSHIFT      19
454         #define EMAC_RXMAC_DEBUG2_QUANTA                   (0x1fL<<23)
455         #define EMAC_RXMAC_DEBUG2_QUANTA_BITSHIFT          23
456 #define EMAC_REG_EMAC_RXMAC_DEBUG3                                0x168	//ACCESS:??  DataWidth:0x20
457         #define EMAC_RXMAC_DEBUG3_PAUSE_CTR                (0xffffL<<0)
458         #define EMAC_RXMAC_DEBUG3_PAUSE_CTR_BITSHIFT       0
459         #define EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR            (0xffffL<<16)
460         #define EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR_BITSHIFT   16
461 #define EMAC_REG_EMAC_RXMAC_DEBUG4                                0x16c	//ACCESS:??  DataWidth:0x20
462         #define EMAC_RXMAC_DEBUG4_TYPE_FIELD               (0xffffL<<0)
463         #define EMAC_RXMAC_DEBUG4_TYPE_FIELD_BITSHIFT      0
464         #define EMAC_RXMAC_DEBUG4_FILT_STATE               (0x3fL<<16)
465         #define EMAC_RXMAC_DEBUG4_FILT_STATE_BITSHIFT      16
466             #define EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE      (0L<<16)
467             #define EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE_BITSHIFT 16
468             #define EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2     (1L<<16)
469             #define EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2_BITSHIFT 16
470             #define EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3     (2L<<16)
471             #define EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3_BITSHIFT 16
472             #define EMAC_RXMAC_DEBUG4_FILT_STATE_UNI       (3L<<16)
473             #define EMAC_RXMAC_DEBUG4_FILT_STATE_UNI_BITSHIFT 16
474             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3     (5L<<16)
475             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3_BITSHIFT 16
476             #define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1      (6L<<16)
477             #define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1_BITSHIFT 16
478             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2     (7L<<16)
479             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2_BITSHIFT 16
480             #define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2      (7L<<16)
481             #define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2_BITSHIFT 16
482             #define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3      (8L<<16)
483             #define EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3_BITSHIFT 16
484             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MC2       (9L<<16)
485             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MC2_BITSHIFT 16
486             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MC3       (10L<<16)
487             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MC3_BITSHIFT 16
488             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1    (14L<<16)
489             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1_BITSHIFT 16
490             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2    (15L<<16)
491             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2_BITSHIFT 16
492             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK    (16L<<16)
493             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK_BITSHIFT 16
494             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MC        (17L<<16)
495             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MC_BITSHIFT 16
496             #define EMAC_RXMAC_DEBUG4_FILT_STATE_BC2       (18L<<16)
497             #define EMAC_RXMAC_DEBUG4_FILT_STATE_BC2_BITSHIFT 16
498             #define EMAC_RXMAC_DEBUG4_FILT_STATE_BC3       (19L<<16)
499             #define EMAC_RXMAC_DEBUG4_FILT_STATE_BC3_BITSHIFT 16
500             #define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1      (20L<<16)
501             #define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1_BITSHIFT 16
502             #define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2      (21L<<16)
503             #define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2_BITSHIFT 16
504             #define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3      (22L<<16)
505             #define EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3_BITSHIFT 16
506             #define EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE     (23L<<16)
507             #define EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE_BITSHIFT 16
508             #define EMAC_RXMAC_DEBUG4_FILT_STATE_BC        (24L<<16)
509             #define EMAC_RXMAC_DEBUG4_FILT_STATE_BC_BITSHIFT 16
510             #define EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE     (25L<<16)
511             #define EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE_BITSHIFT 16
512             #define EMAC_RXMAC_DEBUG4_FILT_STATE_CMD       (26L<<16)
513             #define EMAC_RXMAC_DEBUG4_FILT_STATE_CMD_BITSHIFT 16
514             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MAC       (27L<<16)
515             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MAC_BITSHIFT 16
516             #define EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH     (28L<<16)
517             #define EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH_BITSHIFT 16
518             #define EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF      (29L<<16)
519             #define EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF_BITSHIFT 16
520             #define EMAC_RXMAC_DEBUG4_FILT_STATE_XON       (30L<<16)
521             #define EMAC_RXMAC_DEBUG4_FILT_STATE_XON_BITSHIFT 16
522             #define EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED    (31L<<16)
523             #define EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED_BITSHIFT 16
524             #define EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED   (32L<<16)
525             #define EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED_BITSHIFT 16
526             #define EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE     (33L<<16)
527             #define EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE_BITSHIFT 16
528             #define EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL      (34L<<16)
529             #define EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL_BITSHIFT 16
530             #define EMAC_RXMAC_DEBUG4_FILT_STATE_USA1      (35L<<16)
531             #define EMAC_RXMAC_DEBUG4_FILT_STATE_USA1_BITSHIFT 16
532             #define EMAC_RXMAC_DEBUG4_FILT_STATE_USA2      (36L<<16)
533             #define EMAC_RXMAC_DEBUG4_FILT_STATE_USA2_BITSHIFT 16
534             #define EMAC_RXMAC_DEBUG4_FILT_STATE_USA3      (37L<<16)
535             #define EMAC_RXMAC_DEBUG4_FILT_STATE_USA3_BITSHIFT 16
536             #define EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE     (38L<<16)
537             #define EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE_BITSHIFT 16
538             #define EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE    (39L<<16)
539             #define EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE_BITSHIFT 16
540             #define EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL     (40L<<16)
541             #define EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL_BITSHIFT 16
542             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE     (41L<<16)
543             #define EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE_BITSHIFT 16
544             #define EMAC_RXMAC_DEBUG4_FILT_STATE_DROP      (42L<<16)
545             #define EMAC_RXMAC_DEBUG4_FILT_STATE_DROP_BITSHIFT 16
546         #define EMAC_RXMAC_DEBUG4_DROP_PKT                 (1L<<22)
547         #define EMAC_RXMAC_DEBUG4_DROP_PKT_BITSHIFT        22
548         #define EMAC_RXMAC_DEBUG4_SLOT_FILLED              (1L<<23)
549         #define EMAC_RXMAC_DEBUG4_SLOT_FILLED_BITSHIFT     23
550         #define EMAC_RXMAC_DEBUG4_FALSE_CARRIER            (1L<<24)
551         #define EMAC_RXMAC_DEBUG4_FALSE_CARRIER_BITSHIFT   24
552         #define EMAC_RXMAC_DEBUG4_LAST_DATA                (1L<<25)
553         #define EMAC_RXMAC_DEBUG4_LAST_DATA_BITSHIFT       25
554         #define EMAC_RXMAC_DEBUG4_SFD_FOUND                (1L<<26)
555         #define EMAC_RXMAC_DEBUG4_SFD_FOUND_BITSHIFT       26
556         #define EMAC_RXMAC_DEBUG4_ADVANCE                  (1L<<27)
557         #define EMAC_RXMAC_DEBUG4_ADVANCE_BITSHIFT         27
558         #define EMAC_RXMAC_DEBUG4_START                    (1L<<28)
559         #define EMAC_RXMAC_DEBUG4_START_BITSHIFT           28
560 #define EMAC_REG_EMAC_RXMAC_DEBUG5                                0x170	//ACCESS:??  DataWidth:0x20
561         #define EMAC_RXMAC_DEBUG5_PS_IDISM                 (0x7L<<0)
562         #define EMAC_RXMAC_DEBUG5_PS_IDISM_BITSHIFT        0
563             #define EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE        (0L<<0)
564             #define EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE_BITSHIFT 0
565             #define EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF    (1L<<0)
566             #define EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF_BITSHIFT 0
567             #define EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT   (2L<<0)
568             #define EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT_BITSHIFT 0
569             #define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC  (3L<<0)
570             #define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC_BITSHIFT 0
571             #define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE  (4L<<0)
572             #define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE_BITSHIFT 0
573             #define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL  (5L<<0)
574             #define EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL_BITSHIFT 0
575             #define EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT  (6L<<0)
576             #define EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT_BITSHIFT 0
577         #define EMAC_RXMAC_DEBUG5_CCODE_BUF1               (0x7L<<4)
578         #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_BITSHIFT      4
579             #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW       (0L<<4)
580             #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW_BITSHIFT 4
581             #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT      (1L<<4)
582             #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT_BITSHIFT 4
583             #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF      (2L<<4)
584             #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF_BITSHIFT 4
585             #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF      (3L<<4)
586             #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF_BITSHIFT 4
587             #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF       (4L<<4)
588             #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF_BITSHIFT 4
589             #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF     (6L<<4)
590             #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF_BITSHIFT 4
591             #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF     (7L<<4)
592             #define EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF_BITSHIFT 4
593         #define EMAC_RXMAC_DEBUG5_EOF_DETECTED             (1L<<7)
594         #define EMAC_RXMAC_DEBUG5_EOF_DETECTED_BITSHIFT    7
595         #define EMAC_RXMAC_DEBUG5_CCODE_BUF0               (0x7L<<8)
596         #define EMAC_RXMAC_DEBUG5_CCODE_BUF0_BITSHIFT      8
597         #define EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL        (1L<<11)
598         #define EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL_BITSHIFT 11
599         #define EMAC_RXMAC_DEBUG5_LOAD_CCODE               (1L<<12)
600         #define EMAC_RXMAC_DEBUG5_LOAD_CCODE_BITSHIFT      12
601         #define EMAC_RXMAC_DEBUG5_LOAD_DATA                (1L<<13)
602         #define EMAC_RXMAC_DEBUG5_LOAD_DATA_BITSHIFT       13
603         #define EMAC_RXMAC_DEBUG5_LOAD_STAT                (1L<<14)
604         #define EMAC_RXMAC_DEBUG5_LOAD_STAT_BITSHIFT       14
605         #define EMAC_RXMAC_DEBUG5_CLR_STAT                 (1L<<15)
606         #define EMAC_RXMAC_DEBUG5_CLR_STAT_BITSHIFT        15
607         #define EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE            (0x3L<<16)
608         #define EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE_BITSHIFT   16
609         #define EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT           (1L<<19)
610         #define EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT_BITSHIFT  19
611         #define EMAC_RXMAC_DEBUG5_FMLEN                    (0xfffL<<20)
612         #define EMAC_RXMAC_DEBUG5_FMLEN_BITSHIFT           20
613 #define EMAC_REG_EMAC_RX_STAT_FALSECARRIERERRORS                  0x174	//ACCESS:??  DataWidth:0x20
614 #define EMAC_REG_EMAC_UNUSED4                                     0x178	//ACCESS:??  DataWidth:0x20
615 #define EMAC_REG_EMAC_UNUSED4_COUNT                               2
616 #define EMAC_REG_EMAC_RX_STAT_AC                                  0x180	//ACCESS:??  DataWidth:0x20
617 #define EMAC_REG_EMAC_RX_STAT_AC_COUNT                            23
618 #define EMAC_REG_EMAC_RXMAC_SUC_DBG_OVERRUNVEC                    0x1dc	//ACCESS:??  DataWidth:0x20
619 #define EMAC_REG_EMAC_RXMAC_MPKT_MODE                             0x1e0	//ACCESS:??  DataWidth:0x20
620         #define EMAC_RXMAC_MPKT_MODE_MAC_ADDR_EN            (0xfL<<0)
621         #define EMAC_RXMAC_MPKT_MODE_MAC_ADDR_EN_BITSHIFT   0
622         #define EMAC_RXMAC_MPKT_MODE_MPKT_RCVD              (1L<<19)
623         #define EMAC_RXMAC_MPKT_MODE_MPKT_RCVD_BITSHIFT     19
624         #define EMAC_RXMAC_MPKT_MODE_ACPI_RCVD              (1L<<20)
625         #define EMAC_RXMAC_MPKT_MODE_ACPI_RCVD_BITSHIFT     20
626 #define EMAC_REG_EMAC_UNUSED5                                     0x1e4	//ACCESS:??  DataWidth:0x20
627 #define EMAC_REG_EMAC_UNUSED5_COUNT                               4
628 #define EMAC_REG_EMAC_RX_STAT_AC_28                               0x1f4	//ACCESS:??  DataWidth:0x20
629 #define EMAC_REG_EMAC_UNUSED9                                     0x1f8	//ACCESS:??  DataWidth:0x20
630 #define EMAC_REG_EMAC_UNUSED9_COUNT                               2
631 #define EMAC_REG_EMAC_TX_STAT_IFHCOUTOCTETS                       0x200	//ACCESS:??  DataWidth:0x20
632 #define EMAC_REG_EMAC_TX_STAT_IFHCOUTBADOCTETS                    0x204	//ACCESS:??  DataWidth:0x20
633 #define EMAC_REG_EMAC_TX_STAT_ETHERSTATSCOLLISIONS                0x208	//ACCESS:??  DataWidth:0x20
634 #define EMAC_REG_EMAC_TX_STAT_OUTXONSENT                          0x20c	//ACCESS:??  DataWidth:0x20
635 #define EMAC_REG_EMAC_TX_STAT_OUTXOFFSENT                         0x210	//ACCESS:??  DataWidth:0x20
636 #define EMAC_REG_EMAC_TX_STAT_FLOWCONTROLDONE                     0x214	//ACCESS:??  DataWidth:0x20
637 #define EMAC_REG_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES      0x218	//ACCESS:??  DataWidth:0x20
638 #define EMAC_REG_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES    0x21c	//ACCESS:??  DataWidth:0x20
639 #define EMAC_REG_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS      0x220	//ACCESS:??  DataWidth:0x20
640 #define EMAC_REG_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS        0x224	//ACCESS:??  DataWidth:0x20
641 #define EMAC_REG_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS             0x228	//ACCESS:??  DataWidth:0x20
642 #define EMAC_REG_EMAC_TX_STAT_IFHCOUTUCASTPKTS                    0x22c	//ACCESS:??  DataWidth:0x20
643 #define EMAC_REG_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS                0x230	//ACCESS:??  DataWidth:0x20
644 #define EMAC_REG_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS                0x234	//ACCESS:??  DataWidth:0x20
645 #define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS              0x238	//ACCESS:??  DataWidth:0x20
646 #define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS   0x23c	//ACCESS:??  DataWidth:0x20
647 #define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS  0x240	//ACCESS:??  DataWidth:0x20
648 #define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS  0x244	//ACCESS:??  DataWidth:0x20
649 #define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x248	//ACCESS:??  DataWidth:0x20
650 #define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS0x24c	//ACCESS:??  DataWidth:0x20
651 #define EMAC_REG_EMAC_TX_STAT_ETHERSTATSPKTSOVER1522OCTETS        0x250	//ACCESS:??  DataWidth:0x20
652 #define EMAC_REG_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS  0x254	//ACCESS:??  DataWidth:0x20
653 #define EMAC_REG_EMAC_TXMAC_DEBUG0                                0x258	//ACCESS:??  DataWidth:0x20
654 #define EMAC_REG_EMAC_TXMAC_DEBUG1                                0x25c	//ACCESS:??  DataWidth:0x20
655         #define EMAC_TXMAC_DEBUG1_ODI_STATE                (0xfL<<0)
656         #define EMAC_TXMAC_DEBUG1_ODI_STATE_BITSHIFT       0
657             #define EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE       (0L<<0)
658             #define EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE_BITSHIFT 0
659             #define EMAC_TXMAC_DEBUG1_ODI_STATE_START0     (1L<<0)
660             #define EMAC_TXMAC_DEBUG1_ODI_STATE_START0_BITSHIFT 0
661             #define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0      (4L<<0)
662             #define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0_BITSHIFT 0
663             #define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1      (5L<<0)
664             #define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1_BITSHIFT 0
665             #define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2      (6L<<0)
666             #define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2_BITSHIFT 0
667             #define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3      (7L<<0)
668             #define EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3_BITSHIFT 0
669             #define EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0      (8L<<0)
670             #define EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0_BITSHIFT 0
671             #define EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1      (9L<<0)
672             #define EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1_BITSHIFT 0
673         #define EMAC_TXMAC_DEBUG1_CRS_ENABLE               (1L<<4)
674         #define EMAC_TXMAC_DEBUG1_CRS_ENABLE_BITSHIFT      4
675         #define EMAC_TXMAC_DEBUG1_BAD_CRC                  (1L<<5)
676         #define EMAC_TXMAC_DEBUG1_BAD_CRC_BITSHIFT         5
677         #define EMAC_TXMAC_DEBUG1_SE_COUNTER               (0xfL<<6)
678         #define EMAC_TXMAC_DEBUG1_SE_COUNTER_BITSHIFT      6
679         #define EMAC_TXMAC_DEBUG1_SEND_PAUSE               (1L<<10)
680         #define EMAC_TXMAC_DEBUG1_SEND_PAUSE_BITSHIFT      10
681         #define EMAC_TXMAC_DEBUG1_LATE_COLLISION           (1L<<11)
682         #define EMAC_TXMAC_DEBUG1_LATE_COLLISION_BITSHIFT  11
683         #define EMAC_TXMAC_DEBUG1_MAX_DEFER                (1L<<12)
684         #define EMAC_TXMAC_DEBUG1_MAX_DEFER_BITSHIFT       12
685         #define EMAC_TXMAC_DEBUG1_DEFERRED                 (1L<<13)
686         #define EMAC_TXMAC_DEBUG1_DEFERRED_BITSHIFT        13
687         #define EMAC_TXMAC_DEBUG1_ONE_BYTE                 (1L<<14)
688         #define EMAC_TXMAC_DEBUG1_ONE_BYTE_BITSHIFT        14
689         #define EMAC_TXMAC_DEBUG1_IPG_TIME                 (0xfL<<15)
690         #define EMAC_TXMAC_DEBUG1_IPG_TIME_BITSHIFT        15
691         #define EMAC_TXMAC_DEBUG1_SLOT_TIME                (0xffL<<19)
692         #define EMAC_TXMAC_DEBUG1_SLOT_TIME_BITSHIFT       19
693 #define EMAC_REG_EMAC_TXMAC_DEBUG2                                0x260	//ACCESS:??  DataWidth:0x20
694         #define EMAC_TXMAC_DEBUG2_BACK_OFF                 (0x3ffL<<0)
695         #define EMAC_TXMAC_DEBUG2_BACK_OFF_BITSHIFT        0
696         #define EMAC_TXMAC_DEBUG2_BYTE_COUNT               (0xffffL<<10)
697         #define EMAC_TXMAC_DEBUG2_BYTE_COUNT_BITSHIFT      10
698         #define EMAC_TXMAC_DEBUG2_COL_COUNT                (0x1fL<<26)
699         #define EMAC_TXMAC_DEBUG2_COL_COUNT_BITSHIFT       26
700         #define EMAC_TXMAC_DEBUG2_COL_BIT                  (1L<<31)
701         #define EMAC_TXMAC_DEBUG2_COL_BIT_BITSHIFT         31
702 #define EMAC_REG_EMAC_TXMAC_DEBUG3                                0x264	//ACCESS:??  DataWidth:0x20
703         #define EMAC_TXMAC_DEBUG3_SM_STATE                 (0xfL<<0)
704         #define EMAC_TXMAC_DEBUG3_SM_STATE_BITSHIFT        0
705             #define EMAC_TXMAC_DEBUG3_SM_STATE_IDLE        (0L<<0)
706             #define EMAC_TXMAC_DEBUG3_SM_STATE_IDLE_BITSHIFT 0
707             #define EMAC_TXMAC_DEBUG3_SM_STATE_PRE1        (1L<<0)
708             #define EMAC_TXMAC_DEBUG3_SM_STATE_PRE1_BITSHIFT 0
709             #define EMAC_TXMAC_DEBUG3_SM_STATE_PRE2        (2L<<0)
710             #define EMAC_TXMAC_DEBUG3_SM_STATE_PRE2_BITSHIFT 0
711             #define EMAC_TXMAC_DEBUG3_SM_STATE_SFD         (3L<<0)
712             #define EMAC_TXMAC_DEBUG3_SM_STATE_SFD_BITSHIFT 0
713             #define EMAC_TXMAC_DEBUG3_SM_STATE_DATA        (4L<<0)
714             #define EMAC_TXMAC_DEBUG3_SM_STATE_DATA_BITSHIFT 0
715             #define EMAC_TXMAC_DEBUG3_SM_STATE_CRC1        (5L<<0)
716             #define EMAC_TXMAC_DEBUG3_SM_STATE_CRC1_BITSHIFT 0
717             #define EMAC_TXMAC_DEBUG3_SM_STATE_CRC2        (6L<<0)
718             #define EMAC_TXMAC_DEBUG3_SM_STATE_CRC2_BITSHIFT 0
719             #define EMAC_TXMAC_DEBUG3_SM_STATE_EXT         (7L<<0)
720             #define EMAC_TXMAC_DEBUG3_SM_STATE_EXT_BITSHIFT 0
721             #define EMAC_TXMAC_DEBUG3_SM_STATE_STATB       (8L<<0)
722             #define EMAC_TXMAC_DEBUG3_SM_STATE_STATB_BITSHIFT 0
723             #define EMAC_TXMAC_DEBUG3_SM_STATE_STATG       (9L<<0)
724             #define EMAC_TXMAC_DEBUG3_SM_STATE_STATG_BITSHIFT 0
725             #define EMAC_TXMAC_DEBUG3_SM_STATE_JAM         (10L<<0)
726             #define EMAC_TXMAC_DEBUG3_SM_STATE_JAM_BITSHIFT 0
727             #define EMAC_TXMAC_DEBUG3_SM_STATE_EJAM        (11L<<0)
728             #define EMAC_TXMAC_DEBUG3_SM_STATE_EJAM_BITSHIFT 0
729             #define EMAC_TXMAC_DEBUG3_SM_STATE_BJAM        (12L<<0)
730             #define EMAC_TXMAC_DEBUG3_SM_STATE_BJAM_BITSHIFT 0
731             #define EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT       (13L<<0)
732             #define EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT_BITSHIFT 0
733             #define EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF     (14L<<0)
734             #define EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF_BITSHIFT 0
735         #define EMAC_TXMAC_DEBUG3_FILT_STATE               (0x7L<<4)
736         #define EMAC_TXMAC_DEBUG3_FILT_STATE_BITSHIFT      4
737             #define EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE      (0L<<4)
738             #define EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE_BITSHIFT 4
739             #define EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT      (1L<<4)
740             #define EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT_BITSHIFT 4
741             #define EMAC_TXMAC_DEBUG3_FILT_STATE_UNI       (2L<<4)
742             #define EMAC_TXMAC_DEBUG3_FILT_STATE_UNI_BITSHIFT 4
743             #define EMAC_TXMAC_DEBUG3_FILT_STATE_MC        (3L<<4)
744             #define EMAC_TXMAC_DEBUG3_FILT_STATE_MC_BITSHIFT 4
745             #define EMAC_TXMAC_DEBUG3_FILT_STATE_BC2       (4L<<4)
746             #define EMAC_TXMAC_DEBUG3_FILT_STATE_BC2_BITSHIFT 4
747             #define EMAC_TXMAC_DEBUG3_FILT_STATE_BC3       (5L<<4)
748             #define EMAC_TXMAC_DEBUG3_FILT_STATE_BC3_BITSHIFT 4
749             #define EMAC_TXMAC_DEBUG3_FILT_STATE_BC        (6L<<4)
750             #define EMAC_TXMAC_DEBUG3_FILT_STATE_BC_BITSHIFT 4
751         #define EMAC_TXMAC_DEBUG3_CRS_DONE                 (1L<<7)
752         #define EMAC_TXMAC_DEBUG3_CRS_DONE_BITSHIFT        7
753         #define EMAC_TXMAC_DEBUG3_XOFF                     (1L<<8)
754         #define EMAC_TXMAC_DEBUG3_XOFF_BITSHIFT            8
755         #define EMAC_TXMAC_DEBUG3_SE_COUNTER               (0xfL<<9)
756         #define EMAC_TXMAC_DEBUG3_SE_COUNTER_BITSHIFT      9
757         #define EMAC_TXMAC_DEBUG3_QUANTA_COUNTER           (0x1fL<<13)
758         #define EMAC_TXMAC_DEBUG3_QUANTA_COUNTER_BITSHIFT  13
759 #define EMAC_REG_EMAC_TXMAC_DEBUG4                                0x268	//ACCESS:??  DataWidth:0x20
760         #define EMAC_TXMAC_DEBUG4_PAUSE_COUNTER            (0xffffL<<0)
761         #define EMAC_TXMAC_DEBUG4_PAUSE_COUNTER_BITSHIFT   0
762         #define EMAC_TXMAC_DEBUG4_PAUSE_STATE              (0xfL<<16)
763         #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_BITSHIFT     16
764             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE     (0L<<16)
765             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE_BITSHIFT 16
766             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1     (2L<<16)
767             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1_BITSHIFT 16
768             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2     (3L<<16)
769             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2_BITSHIFT 16
770             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3     (4L<<16)
771             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3_BITSHIFT 16
772             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2     (5L<<16)
773             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2_BITSHIFT 16
774             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3     (6L<<16)
775             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3_BITSHIFT 16
776             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1     (7L<<16)
777             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1_BITSHIFT 16
778             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1     (8L<<16)
779             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1_BITSHIFT 16
780             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2     (9L<<16)
781             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2_BITSHIFT 16
782             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME     (10L<<16)
783             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME_BITSHIFT 16
784             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE     (12L<<16)
785             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE_BITSHIFT 16
786             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT     (13L<<16)
787             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT_BITSHIFT 16
788             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD      (14L<<16)
789             #define EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD_BITSHIFT 16
790         #define EMAC_TXMAC_DEBUG4_STATS0_VALID             (1L<<20)
791         #define EMAC_TXMAC_DEBUG4_STATS0_VALID_BITSHIFT    20
792         #define EMAC_TXMAC_DEBUG4_APPEND_CRC               (1L<<21)
793         #define EMAC_TXMAC_DEBUG4_APPEND_CRC_BITSHIFT      21
794         #define EMAC_TXMAC_DEBUG4_SLOT_FILLED              (1L<<22)
795         #define EMAC_TXMAC_DEBUG4_SLOT_FILLED_BITSHIFT     22
796         #define EMAC_TXMAC_DEBUG4_MAX_DEFER                (1L<<23)
797         #define EMAC_TXMAC_DEBUG4_MAX_DEFER_BITSHIFT       23
798         #define EMAC_TXMAC_DEBUG4_SEND_EXTEND              (1L<<24)
799         #define EMAC_TXMAC_DEBUG4_SEND_EXTEND_BITSHIFT     24
800         #define EMAC_TXMAC_DEBUG4_SEND_PADDING             (1L<<25)
801         #define EMAC_TXMAC_DEBUG4_SEND_PADDING_BITSHIFT    25
802         #define EMAC_TXMAC_DEBUG4_EOF_LOC                  (1L<<26)
803         #define EMAC_TXMAC_DEBUG4_EOF_LOC_BITSHIFT         26
804         #define EMAC_TXMAC_DEBUG4_COLLIDING                (1L<<27)
805         #define EMAC_TXMAC_DEBUG4_COLLIDING_BITSHIFT       27
806         #define EMAC_TXMAC_DEBUG4_COL_IN                   (1L<<28)
807         #define EMAC_TXMAC_DEBUG4_COL_IN_BITSHIFT          28
808         #define EMAC_TXMAC_DEBUG4_BURSTING                 (1L<<29)
809         #define EMAC_TXMAC_DEBUG4_BURSTING_BITSHIFT        29
810         #define EMAC_TXMAC_DEBUG4_ADVANCE                  (1L<<30)
811         #define EMAC_TXMAC_DEBUG4_ADVANCE_BITSHIFT         30
812         #define EMAC_TXMAC_DEBUG4_GO                       (1L<<31)
813         #define EMAC_TXMAC_DEBUG4_GO_BITSHIFT              31
814 #define EMAC_REG_EMAC_UNUSED6                                     0x26c	//ACCESS:??  DataWidth:0x20
815 #define EMAC_REG_EMAC_UNUSED6_COUNT                               5
816 #define EMAC_REG_EMAC_TX_STAT_AC                                  0x280	//ACCESS:??  DataWidth:0x20
817 #define EMAC_REG_EMAC_TX_STAT_AC_COUNT                            22
818 #define EMAC_REG_EMAC_TXMAC_SUC_DBG_OVERRUNVEC                    0x2d8	//ACCESS:??  DataWidth:0x20
819 #define EMAC_REG_EMAC_UNUSED7                                     0x2dc	//ACCESS:??  DataWidth:0x20
820 #define EMAC_REG_EMAC_UNUSED7_COUNT                               8
821 #define EMAC_REG_EMAC_TX_RATE_LIMIT_CTRL                          0x2fc	//ACCESS:??  DataWidth:0x20
822         #define EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC    (0x7fL<<0)
823         #define EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC_BITSHIFT 0
824         #define EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM    (0x7fL<<16)
825         #define EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM_BITSHIFT 16
826         #define EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN    (1L<<31)
827         #define EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN_BITSHIFT 31
828 #define EMAC_REG_EMAC_UNUSED8                                     0x300	//ACCESS:??  DataWidth:0x20
829 #define EMAC_REG_EMAC_UNUSED8_COUNT                               64
830 #define EMAC_REG_RX_PFC_MODE					  0x320
831 	#define EMAC_REG_RX_PFC_MODE_TX_EN			  (1L<<0)
832 	#define EMAC_REG_RX_PFC_MODE_TX_EN_BITSHIFT		  0
833 	#define EMAC_REG_RX_PFC_MODE_RX_EN			  (1L<<1)
834 	#define EMAC_REG_RX_PFC_MODE_RX_EN_BITSHIFT		  1
835 	#define EMAC_REG_RX_PFC_MODE_PRIORITIES			  (1L<<2)
836 	#define EMAC_REG_RX_PFC_MODE_PRIORITIES_BITSHIFT	  2
837 	#define EMAC_REG_RX_PFC_MODE_KEEP_PFC			  (1L<<3)
838 	#define EMAC_REG_RX_PFC_MODE_KEEP_PFC_BITSHIFT	          3
839 
840 #define EMAC_REG_RX_PFC_PARAM					  0x324
841 	#define EMAC_REG_RX_PFC_PARAM_OPCODE			  (0xffff<<0)
842 	#define EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT		  0
843 	#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN		  (0xffff<<16)
844 	#define EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT	  16
845 
846 #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD                     0x328
847     #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT           (0xffff<<0)
848     #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT_BITSHIFT  0
849     #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_UNUSED          (0xffff<<16)
850     #define EMAC_REG_RX_PFC_STATS_XOFF_RCVD_UNUSED_BITSHIFT 16
851 
852 #define EMAC_REG_RX_PFC_STATS_XON_RCVD                      0x32c
853     #define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT            (0xffff<<0)
854     #define EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT_BITSHIFT   0
855     #define EMAC_REG_RX_PFC_STATS_XON_RCVD_UNUSED           (0xffff<<16)
856     #define EMAC_REG_RX_PFC_STATS_XON_RCVD_UNUSED_BITSHIFT  16
857 
858 #define EMAC_REG_RX_PFC_STATS_XOFF_SENT                     0x330
859     #define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT           (0xffff<<0)
860     #define EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT_BITSHIFT  0
861     #define EMAC_REG_RX_PFC_STATS_XOFF_SENT_UNUSED          (0xffff<<16)
862     #define EMAC_REG_RX_PFC_STATS_XOFF_SENT_UNUSED_BITSHIFT 16
863 
864 #define EMAC_REG_RX_PFC_STATS_XON_SENT                      0x334
865     #define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT            (0xffff<<0)
866     #define EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT_BITSHIFT   0
867     #define EMAC_REG_RX_PFC_STATS_XON_SENT_UNUSED           (0xffff<<16)
868     #define EMAC_REG_RX_PFC_STATS_XON_SENT_UNUSED_BITSHIFT  16
869 
870 #endif /* EMAC_REG_H */
871 
872