xref: /illumos-gate/usr/src/uts/common/sys/dma_i8237A.h (revision 2d6eb4a5)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _SYS_DMA_I8237A_H
28 #define	_SYS_DMA_I8237A_H
29 
30 #ifdef	__cplusplus
31 extern "C" {
32 #endif
33 
34 /*	Copyright (c) 1990, 1991 UNIX System Laboratories, Inc.	*/
35 /*	Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T	*/
36 /*	All Rights Reserved	*/
37 
38 #define	D37A_MAX_CHAN   8
39 #define	D37A_DFR_ALIGN  0xf
40 #define	D37A_MIN_CHAN   0x0
41 
42 /*
43  * Defines for PC AT DMA controllers.
44  */
45 
46 /*
47  * The PC/AT has two Intel 8237A-5 DMA controllers that provide 8 channels
48  */
49 #define	DMA_0WCNT	0x01	/* Channel  word count */
50 #define	DMA_1WCNT	0x03	/* Channel  word count */
51 #define	DMA_2WCNT	0x05	/* Channel  word count */
52 #define	DMA_3WCNT	0x07	/* Channel  word count */
53 #define	DMA_4WCNT	0xC2	/* (RESERVED) Channel  word count */
54 #define	DMA_5WCNT	0xC6	/* Channel  word count */
55 #define	DMA_6WCNT	0xCA	/* Channel  word count */
56 #define	DMA_7WCNT	0xCE	/* Channel  word count */
57 
58 #define	DMA_0ADR	0x00	/* Channel  address register */
59 #define	DMA_1ADR	0x02	/* Channel  address register */
60 #define	DMA_2ADR	0x04	/* Channel  address register */
61 #define	DMA_3ADR	0x06	/* Channel  address register */
62 #define	DMA_4ADR	0xC0	/* (RESERVED) Channel  address register */
63 #define	DMA_5ADR	0xC4	/* Channel  address register */
64 #define	DMA_6ADR	0xC8	/* Channel  address register */
65 #define	DMA_7ADR	0xCC	/* Channel  address register */
66 
67 /*
68  * The Intel DMA controllers are augmented with 8-bit page registers
69  * for each channel, allowing access to a 16MB address space.
70  */
71 #define	DMA_0PAGE	0x87	/* Channel 0 address extension reg */
72 #define	DMA_1PAGE	0x83	/* Channel 1 address extension reg */
73 #define	DMA_2PAGE	0x81	/* Channel 2 address extension reg */
74 #define	DMA_3PAGE	0x82	/* Channel 3 address extension reg */
75 #define	DMA_4PAGE	0	/* dummy address for dma chan. 4 page reg. */
76 #define	DMA_5PAGE	0x8B	/* Channel 5 address extension reg */
77 #define	DMA_6PAGE	0x89	/* Channel 6 address extension reg */
78 #define	DMA_7PAGE	0x8A	/* Channel 7 address extension reg */
79 
80 /*
81  * The EISA has an 8-bit high-page register for each channel
82  * for access to a 32-bit address space.
83  */
84 #define	DMA_0HPG	0x487   /* port address for dma channel 0 */
85 				/* high page reg */
86 #define	DMA_1HPG	0x483   /* port address for dma channel 1 */
87 				/* high page reg */
88 #define	DMA_2HPG	0x481   /* port address for dma channel 2 */
89 				/* high page reg */
90 #define	DMA_3HPG	0x482   /* port address for dma channel 3 */
91 				/* high page reg */
92 #define	DMA_4HPG	0	/* dummy address for dma channel 4 */
93 				/* high page reg */
94 #define	DMA_5HPG	0x48B   /* port address for dma channel 5 */
95 				/* high page reg */
96 #define	DMA_6HPG	0x489   /* port address for dma channel 6 */
97 				/* high page reg */
98 #define	DMA_7HPG	0x48A   /* port address for dma channel 7 */
99 				/* high page reg */
100 
101 /*
102  * The EISA has an 8-bit high-count register for each channel
103  * for xfer sizes up to 16MB.
104  */
105 #define	DMA_0XCNT	0x401   /* chan. 0 base and current count high */
106 #define	DMA_1XCNT	0x403   /* chan. 1 base and current count high */
107 #define	DMA_2XCNT	0x405   /* chan. 2 base and current count high */
108 #define	DMA_3XCNT	0x407   /* chan. 3 base and current count high */
109 #define	DMA_4XCNT	0	/* dummy chan. 4 base and current count high */
110 #define	DMA_5XCNT	0x4C6   /* chan. 5 base and current count high */
111 #define	DMA_6XCNT	0x4CA   /* chan. 6 base and current count high */
112 #define	DMA_7XCNT	0x4CE   /* chan. 7 base and current count high */
113 
114 /*
115  * I/O port addresses for controller 1
116  */
117 #define	DMAC1_CMD	0x08	/* Command reg */
118 #define	DMAC1_REQ	0x09	/* request reg */
119 #define	DMAC1_STAT	0x08	/* Status reg */
120 #define	DMAC1_MASK	0x0A	/* Mask set/reset register */
121 #define	DMAC1_MODE	0x0B	/* Mode reg */
122 #define	DMAC1_CLFF	0x0C	/* Clear byte pointer first/last flip-flop */
123 #define	DMA1RTRWMC	0x0D	/* read temp reg/write master clear */
124 #define	DMA1CMR		0x0E	/* clear mask register */
125 #define	DMAC1_ALLMASK	0x0F	/* Mask all registers */
126 #define	DMAC1_SCM	0x40A   /* set chain mode */
127 #define	DMAC1_EWM	0x40B	/* extended write mode */
128 
129 /*
130  * I/O port addresses for controller 2
131  */
132 #define	DMAC2_CMD	0xD0	/* Command reg */
133 #define	DMAC2_STAT	0xD0	/* Status reg */
134 #define	DMAC2_REQ	0xD2	/* request reg */
135 #define	DMAC2_MASK	0xD4	/* Mask set/reset register */
136 #define	DMAC2_MODE	0xD6	/* Mode reg */
137 #define	DMAC2_CLFF	0xD8	/* Clear byte pointer first/last flip-flop */
138 #define	DMA2RTRWMC	0xDA	/* read temp reg/write master clear */
139 #define	DMA2CMR		0xDC	/* clear mask register */
140 #define	DMAC2_ALLMASK	0xDE	/* Mask all registers */
141 #define	DMAC2_SCM	0x4D4   /* set chain mode */
142 #define	DMAC2_EWM	0x4D6   /* extended write mode */
143 
144 /*
145  * Write-only Command register definitions.
146  */
147 #define	DMACMD_MEM_TO_MEM	0x01	/* memory-to-memory copy (1=enable) */
148 #define	DMACMD_CHAN_HOLD	0x02	/* Channel 0 address hold (1=enable) */
149 #define	DMACMD_CTLR_ENABLE	0x04	/* Controller disable (0=enabled) */
150 #define	DMACMD_TIMING		0x08	/* normal/compressed timing (0=nrml) */
151 #define	DMACMD_FIX_PRIO		0x10	/* fixed/rotating priority (0=fixed) */
152 #define	DMACMD_WRT_SELECT	0x20	/* late/ext write selection (1=ext) */
153 #define	DMACMD_DREQ_LEVEL	0x40	/* DREQ sense active (0=actv. high) */
154 #define	DMACMD_DACK_LEVEL	0x80	/* DACK sense active (0=actv. low) */
155 
156 /*
157  * Initialization value for DMA controller.
158  */
159 #define	DMA_CTLR_INIT	~(DMACMD_MEM_TO_MEM | DMACMD_CHAN_HOLD | \
160 			DMACMD_CTLR_ENABLE | DMACMD_TIMING | \
161 			DMACMD_FIX_PRIO	| DMACMD_WRT_SELECT | \
162 			DMACMD_DREQ_LEVEL | DMACMD_DACK_LEVEL)
163 
164 /*
165  * Write-only Mode register.  There is actually a 6-bit Mode register
166  * associated with each channel.  These are written one at a time, with
167  * the channel number indicated by the low-order 2 bits.
168  */
169 
170 #define	DMAMODE_CHAN	0x03	/* Mask for the "channel select" bits. */
171 				/* These indicate channel 0-3 */
172 #define	DMAMODE_VERF	0x00	/* Verify Transfer */
173 #define	DMAMODE_READ	0x04	/* Read Transfer */
174 #define	DMAMODE_WRITE   0x08	/* Write Transfer */
175 				/* Note: Above settings for bits 2-3 are */
176 				/* "don't care" if bits 6-7 indicate */
177 				/* cascade mode */
178 #define	DMAMODE_AUTO	0x10	/* enable Autoinitialization on completion */
179 #define	DMAMODE_DECR	0x20	/* Address Decrement.  If 0, address incr */
180 #define	DMAMODE_DEMAND  0x00	/* Select Demand mode */
181 				/* Each DREQ causes transfers at full speed */
182 				/* until DREQ goes inactive (after which it */
183 				/* can be resumed) or either terminal-count */
184 				/* happens or EOP is asserted */
185 #define	DMAMODE_SINGLE  0x40	/* Select Single mode */
186 				/* Each DREQ causes a single byte/word xfer */
187 #define	DMAMODE_BLOCK   0x80	/* Select Block mode */
188 				/* Each DREQ causes transfers at full speed */
189 				/* until terminal count or EOP */
190 #define	DMAMODE_CASC	0xC0	/* Select Cascade mode.  On the PC-AT, this */
191 				/* should be set for DMA 2 channel 0 ONLY */
192 
193 
194 #define	EISA_DMAIS	0x40a   /* interrupt status register */
195 
196 #define	DMA_MSK		0x0A	/* Mask, enable disk, disable others */
197 #define	DMA_CLEAR	0x1A	/* Master clear */
198 #define	IOCR		0x56	/* IO controller */
199 
200 /*
201  * DMA Channels. d_chan field of dmareq.
202  */
203 
204 /* 8 bit channels */
205 #define	DMAE_CH0	0	/* Channel 0 */
206 #define	DMAE_CH1	1	/* Channel 1 */
207 #define	DMAE_CH2	2	/* Channel 2 */
208 #define	DMAE_CH3	3	/* Channel 3 */
209 #define	DMAE_CH4	4	/* Channel 4 */
210 /* 16 bit channels */
211 #define	DMAE_CH5	5	/* Channel 5 */
212 #define	DMAE_CH6	6	/* Channel 6 */
213 #define	DMAE_CH7	7	/* Channel 7 */
214 
215 /*
216  * DMA Masks.
217  */
218 #define	DMA_SETMSK	4	/* Set mask bit */
219 #define	DMA_CLRMSK	0	/* Clear mask bit */
220 
221 /* dma_alloc modes */
222 #define	DMA_BLOCK	0	/* blocking task time allocation */
223 #define	DMA_NBLOCK	1	/* non-blocking task time allocation */
224 
225 #define	EISA_DMA_8	0	/* 8-bit data path */
226 #define	EISA_DMA_16	1<<2	/* 16-bit data path, word count */
227 #define	EISA_DMA_32	2<<2	/* 32-bit data path */
228 #define	EISA_DMA_16B	3<<2	/* 16-bit data path, byte count */
229 
230 #define	EISA_ENCM	4	/* enable chaining mode */
231 #define	EISA_CMOK	8	/* chaining mode completed (OK) */
232 
233 
234 /*
235  * Channel Address Array - makes life much easier
236  */
237 struct d37A_chan_reg_addr {
238 	uchar_t	addr_reg;	/* address register */
239 	uchar_t	cnt_reg;	/* count register */
240 	uchar_t	page_reg;	/* page register */
241 	uchar_t	ff_reg;		/* first-last flipflop */
242 	uchar_t	cmd_reg;	/* command register */
243 	uchar_t	mode_reg;	/* mode register */
244 	uchar_t	mask_reg;	/* mask register */
245 	uchar_t	stat_reg;	/* status register */
246 	uchar_t	reqt_reg;	/* request register */
247 	ushort_t hpage_reg;	/* high page register */
248 	ushort_t hcnt_reg;	/* high count register */
249 	ushort_t emode_reg;	/* extended mode register */
250 	ushort_t scm_reg;	/* set chaining mode register */
251 };
252 
253 /*
254  * macro to initialize array of d37A_chan_reg_addr structures
255  */
256 #define	D37A_BASE_REGS_VALUES \
257 	{DMA_0ADR, DMA_0WCNT, DMA_0PAGE, DMAC1_CLFF, \
258 	    DMAC1_CMD, DMAC1_MODE, DMAC1_MASK, DMAC1_STAT, DMAC1_REQ, \
259 	    DMA_0HPG, DMA_0XCNT, DMAC1_EWM, DMAC1_SCM}, \
260 	{DMA_1ADR, DMA_1WCNT, DMA_1PAGE, DMAC1_CLFF, \
261 	    DMAC1_CMD, DMAC1_MODE, DMAC1_MASK, DMAC1_STAT, DMAC1_REQ, \
262 	    DMA_1HPG, DMA_1XCNT, DMAC1_EWM, DMAC1_SCM}, \
263 	{DMA_2ADR, DMA_2WCNT, DMA_2PAGE, DMAC1_CLFF, \
264 	    DMAC1_CMD, DMAC1_MODE, DMAC1_MASK, DMAC1_STAT, DMAC1_REQ, \
265 	    DMA_2HPG, DMA_2XCNT, DMAC1_EWM, DMAC1_SCM}, \
266 	{DMA_3ADR, DMA_3WCNT, DMA_3PAGE, DMAC1_CLFF, \
267 	    DMAC1_CMD, DMAC1_MODE, DMAC1_MASK, DMAC1_STAT, DMAC1_REQ, \
268 	    DMA_3HPG, DMA_3XCNT, DMAC1_EWM, DMAC1_SCM}, \
269 	{DMA_4ADR, DMA_4WCNT, DMA_4PAGE, DMAC2_CLFF, \
270 	    DMAC2_CMD, DMAC2_MODE, DMAC2_MASK, DMAC2_STAT, DMAC2_REQ, \
271 	    DMA_4HPG, DMA_4XCNT, DMAC2_EWM, DMAC2_SCM}, \
272 	{DMA_5ADR, DMA_5WCNT, DMA_5PAGE, DMAC2_CLFF, \
273 	    DMAC2_CMD, DMAC2_MODE, DMAC2_MASK, DMAC2_STAT, DMAC2_REQ, \
274 	    DMA_5HPG, DMA_5XCNT, DMAC2_EWM, DMAC2_SCM}, \
275 	{DMA_6ADR, DMA_6WCNT, DMA_6PAGE, DMAC2_CLFF, \
276 	    DMAC2_CMD, DMAC2_MODE, DMAC2_MASK, DMAC2_STAT, DMAC2_REQ, \
277 	    DMA_6HPG, DMA_6XCNT, DMAC2_EWM, DMAC2_SCM}, \
278 	{DMA_7ADR, DMA_7WCNT, DMA_7PAGE, DMAC2_CLFF, \
279 	    DMAC2_CMD, DMAC2_MODE, DMAC2_MASK, DMAC2_STAT, DMAC2_REQ, \
280 	    DMA_7HPG, DMA_7XCNT, DMAC2_EWM, DMAC2_SCM}
281 
282 extern int d37A_init(dev_info_t *);
283 extern void d37A_dma_disable(int);
284 extern void d37A_dma_enable(int);
285 extern void d37A_dma_swstart(int);
286 extern void d37A_dma_stop(int);
287 extern void d37A_get_chan_stat(int, ulong_t *, int *);
288 extern int d37A_dma_valid(int);
289 extern void d37A_dma_release(int);
290 
291 /* The following 3 routines are intel specific : man page ddi_dmae_req(9S) */
292 #if defined(__i386) || defined(__amd64)
293 extern uchar_t d37A_get_best_mode(struct ddi_dmae_req *);
294 extern int d37A_prog_chan(struct ddi_dmae_req *, ddi_dma_cookie_t *, int);
295 extern int d37A_dma_swsetup(struct ddi_dmae_req *, ddi_dma_cookie_t *, int);
296 #endif
297 
298 #ifdef	__cplusplus
299 }
300 #endif
301 
302 #endif /* _SYS_DMA_I8237A_H */
303